DARBHANGA COLLEGE OF ENGINEERING, DARBHANGA
DARBHANGA, BIHAR- 846005
(Under the Department of Science and Technology, Govt. of Bihar, Patna)
LABORATORY MANNUAL
Digital Electronics( )
PREPARED BY
Nitish Kumar,
Assistant Professor
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
Website: [Link]
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CONTENTS
Page
[Link]. ITEM NO.
No.
1 Vision, Mission Of The Institute 3
2 Vision, Mission and Program Educational Objective 4
3 Course Outcomes and Program Outcomes 5
4 Do’s and Don’ts in the Laboratory 6
5 List Of Experiments 7
6 Experiment No.1: Logic Gates 8
7 Experiment No.2: Half Adder & Full Adder 12
8 Experiment No.3: Half Subtractor & Full Subtractor 15
9 Experiment No.4: BCD to 7- Segment 18
10 Experiment No.5: MUX 22
11 Experiment No.6: DEMUX 24
12 Experiment No.7: S-R Flip Flop 26
13 Experiment No.8: J-K FlipFlop 28
14 Viva Questions
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Vision of the Institute
To produce quality engineers to pursue higher studies, serve the national and multinational
companies at large.
Mission of the Institute
M1: To produce quality engineers through good teaching learning ambience
M2: To promote the graduates for higher studies and research
M3: The graduates will serve the nation through public services
M4: To provide engineers to serve the society through ethical values
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Vision of the Department
To produce quality electrical and electronics engineers to pursue higher studies, serve the national,
multi-national companies and society at large.
Mission of the Department
M1: To provide high quality teaching and finest environment for learning to the
students.
M2: To promote the graduates for higher studies and research
M3: To embed ethical values in graduates through various activities.
M4: To expose our graduates to the latest technology and research through
collaboration with the industry and research institutes.
Program Educational Objectives (PEOs)
PEO 1. The graduate will apply the electrical and electronics engineering concepts to excel in higher
education and research & development activity having strong foundation in science and technology.
PEO 2. The graduate will demonstrate the knowledge and skills to solve real life engineering
problems and design electrical systems that are technically sound, economical and socially
acceptable.
PEO 3. The graduates will showcase the professional skills keeping team spirit, societal and ethical
values.
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Course Code Course Name Digital Electronics Laboratory
Course Outcomes (CO)
After completion of this course, students will be able to:
Bloom’s
CO Statement Taxonomy
Level
CO1 Analysis, Implementation and testing of logic gates and functions
CO2 Analysis, Implementation and testing of combinational circuits
CO3 Analysis, Implementation and testing of flip-flops and registers
CO4 Analysis, Implementation and testing of counters
CO – PO – PSO Mapping
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PEO1 PEO2 PEO
CO1 3
CO2
CO3
CO4
1- Low
2- Medium
3- High
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Do’s and Don’ts in the Laboratory
1. Keep the table clean. Do not put any object on table or nearby circuits.
2. Check for appropriate power supply before connecting to the equipment.
3. Make the connections without connecting the leads to the supply. Avoid loose connections.
4. Re-check the connections and show it to the teacher /instructor before switching-on the
power supply to the circuit.
5. After the experiment, disconnect the connections and put back the connecting wires/leads at
appropriate place.
6. Return all the apparatus to the lab-staff.
7. In case of shock, switch-off the power supply immediately.
8. Strictly follow the procedure given with the respective experiments.
9. Don’t touch the main power supply leads with bare hand and avoid body earth.
10. Don’t use the mobile phones during laboratory.
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LIST OF EXEPRIMENTS
Sr. No. Name Of The Experiment Page No.
1 Experiment No.1: Logic Gates 8
2 Experiment No.2: Half Adder & Full Adder 12
3 Experiment No.3: Half Subtractor & Full Subtractor 15
4 Experiment No.4: BCD to 7- Segment 18
5 Experiment No.5: MUX 22
6 Experiment No.6: DEMUX 24
7 Experiment No.7: S-R Flip Flop 26
8 Experiment No.8: J-K FlipFlop 28
9 Experiment No.9:
10 Experiment No.10:
11 Experiment No.11:
12 Experiment No.12:
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EXPERIMENT No. –01
AIM: Verification of the truth tables of all gates.
APPARATUS REQUIRED: -
Digital lab trainer kit, connecting wires, breadboard, IC’s AND (IC-7408), OR (IC-7432), NAND
(IC-7400), NOR (IC-7402), NOT (IC-7404) and NOR (IC-7486).
THEORY: -
Logic gates are idealized or physical devices implementing a Boolean function, which it performs
a logical operation on one or more logical inputs and produce a single output. Depending on the
context, the term may refer to an ideal logic gate.
The main hierarchy is as follows: -
1. Basic Gates
2. Universal Gates
3. Advanced Gates
BASIC GATES
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The output is
high when both the inputs are high. The output is low level when any one of the inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The output is low
when the input is high.
UNIVERSAL GATES
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low. The output is low level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
ADVANCED GATES
X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the inputs are
low and both the inputs are high.
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X-NOR GATE:
The output is low when any one of the inputs is high. The output is high when both the inputs are
low and both the inputs are high.
AND GATE:
SYMBOL: PIN DIAGRAM:
OR GATE:
SYMBOL: PIN DIAGRAM:
NOT GATE:
SYMBOL: PIN DIAGRAM:
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XOR GATE:
SYMBOL: PIN DIAGRAM:
2-INPUT NAND GATE:
SYMBOL: PIN DIAGRAM:
NOR GATE:
SYMBOL: PIN DIAGRAM:
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PROCEDURE:-
1. Place the breadboard gently on the observation table.
2. Fix the IC which is under observation between the half shadow line of breadboard, so there
is no shortage of voltage.
3. Connect the wire to the main voltage source (Vcc) whose other end is connected to last pin
of the IC (14 place from the notch).
4. Connect the ground of IC (7th place from the notch) to the ground terminal provided on the
digital lab kit.
5. Give the input at any one of the gate of the ICs i.e. 1st, 2nd, 3rd, 4th gate by using
connecting wires. (In accordance to IC provided).
6. Connect output pins to the led on digital lab kit.
7. Switch on the power supply.
8. If LED glows red then output is true, if it glows green output is false, which is numerically
denoted as 1 and 0 respectively. The Color can change based on the IC manufacturer it’s just
verification of the Truth Table not the color change.
RESULT:-
Thus the logic gates are studied and their truth tables were verified.
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EXPERIMENT NO.–2
AIM: - Design and verification of the truth tables of Half and Full adder circuits.
APPARATUS REQUIRED: -
(1) Logic trainer kit
(2) NAND gates (IC 7400)
(3) XOR gates (IC 7486)
(4) AND gates (IC 7408)
(5) Wires.
THEORY:
Half adder:
A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’
and other from the carry ‘C’ into the higher adder position. Above circuit is called as a carry signal
from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND
gate.
Truth Table for Half Adder
INPUT OUTPUT
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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Full Adder:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three
inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot
do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR
Gate.
Truth Table for Full Adder
INPUT OUTPUT
A B Ci S C
0 0 0 0 0
0 0 1 0 0
0 1 0 1 0
0 1 1 1 0
1 0 0 0 1
1 0 1 0 1
1 1 0 1 1
1 1 1 1 1
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PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the half adder &full adder was designed and their truth table is verified.
PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
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EXPERIMENT NO.–3
AIM: - Design and verification of the truth tables of Half and Full Subtractor circuits.
APPARATUS REQUIRED: -
1. logic trainer kit,
2. NAND gates (IC 7400),
3. XOR gates (IC 7486),
4. AND gates (IC 7408),
5. NOT gates (IC 7404),
6. Connecting wires.
THEORY:
Half Subtractor:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input
and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR
Gate, borrow output can be implemented using an AND Gate and an inverter.
Truth Table for Half Subtractor
INPUT OUTPUT
A B Bo Diff
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
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Full Subtractor:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic
circuit should have three inputs and two outputs. The two half subtractor put together gives a full
subtractor .The first half subtractor will be C and A B. The output will be difference output of full
subtractor. The expression AB assembles the borrow output of the half subtractor and the second
term is the inverted difference output of first X -OR.
Truth Table for Full Subtractor
INPUT OUTPUT
A B C Bo Diff
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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Using Only NAND Gates (Full Subtractor)
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the half subtractor and full subtractor was designed and their truth table is verified.
PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
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EXPERIMENT NO.–4
AIM: To set up and test a 7-segment static display system to display numbers 0 to 9.
APPARATUS REQUIRED:
1. Trainer kit
2. IC7447
3. 7-Segment display
4. Patch chords
THEORY:
The Light Emitting Diode (LED) finds its place in many applications in these modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contains the arrangement
of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode).
The purpose of arranging it in that passion is that we can make any number out of that by switching
ON and OFF the particular LED’s. Here is the block diagram of the Seven Segment LED
arrangement.
The Light Emitting Diode (LED), finds its place in many applications in this modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contains the arrangement
of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode).
The purpose of arranging it in that passion is that we can make any number out of that by switching
ON and OFF the particular LED’s. Here is the block diagram of the Seven Segment LED
arrangement.
Seven Segment DisplayLED’s are basically of two types-
Common Cathode (CC) -All the 8 anode legs uses only one cathode, which is common. Common
Anode (CA)-The common leg for all the cathode is of Anode type.
A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to a
maximum of 2n unique output lines. The IC7447 is a BCD to 7-segment pattern converter. The
IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7 segment code.
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Circuit Diagram:
Truth Table
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PROCEDURE:
1. Check all the components for their working.
2. Make connections as shown in the circuit diagram.
3. Verify the Truth Table and observe the outputs.
RESULT:
Thus the BCD to 7 – Segment display logic circuit was designed and their truth table is verified.
PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
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EXPERIMENT –5
AIM: - Verification of the truth table of the Multiplexer 74150
APPARATUS REQUIRED:-
1. Logic trainer kit
2. IC-74150
3. Wires.
THEORY:
A Multiplexer (or a data selector) is a logic circuit that accepts several data inputs and allows only
one of them at a time to get through to the output. The selection of the desired data input is
controlled by the SELECT (or ADDRESS) INPUTS. Multiplexer means transmitting a large
number of information units over a smaller number of channels or lines. A digital multiplexer is a
combinational circuit that selects binary information from one of many input lines and directs it to
a single output line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2𝑛 input line and n selection lines whose bit combination determine which input
is selected. Figure below shows the block diagram of Multiplexer
In this diagram the inputs and outputs are indicated by means of broad arrows to indicate that there
may be one or more lines. Depending upon the digital code applied at the SELECT inputs, one out
of the data sources is selected and transmitted to the single output channel. The Multiplexer
becomes enabled when the strobe signal is active LOW. The pin out of a 8:1 multiplexer IC 74150
is shown above. The output of this circuit is the inverted input. This is a 16-pin DIP.
Function Table
INPUT OUTPUT
S1 S0 Y
0 0 D0 = D0 S1’ S0’
0 1 D1 = D1 S1’ S0
1 0 D2 = D2 S1 S0’
1 1 D3 = D3 S1 S0
Y = D0 S1’ S0’ +D1 S1’ S0 +D2 S1 S0’ +D3 S1 S0
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PIN DIAGRAM: CIRCUIT DIAGRAM FOR MULTIPLEXER:
PROCEDURE: -
1) Assemble the circuit on bread board, as per above diagram.
2) Give the logical inputs and check for the proper output, as per the truth table.
RESULT:
Hence verified the Multiplexer (8:1) operation using IC-74150
PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
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EXPERIMENT – 6
AIM: - Verification of the truth table of the De-Multiplexer 74154
APPARATUS REQUIRED: -
1. Logic trainer kit
2. IC- 74154
3. Wires.
THEORY:
A Demultiplexer performs the reverse operation of a Multiplexer. It accepts a single input and
distributes it over several outputs. The SELECT input code determines to which output the data input
will be transmitted. The Demultiplexer becomes enabled when the strobe signal is active LOW. This
circuit can also be used as binary-to-decimal decoder with binary inputs applied at the select input
lines and the output will be obtained on the corresponding line. These devices are available as 2-line-
to-4-line decoder, 3-line-to- 8-line decoder, 4-line-to-16-line decoder. The output of these devices is
active LOW. Also there is an active low enable/data input terminal available.
Function Table
INPUT OUTPUT
S1 S0 INPUT
0 0 D0 = X S1’ S0
0 1 D1 = X S1’ S0
1 0 D2 = X S1 S0’
1 1 D3 = X S1 S0
Y = X S1’ S0 + X S1’ S0 + X S1 S0’ + X S1 S0
In this diagram the inputs and outputs are indicated by means of broad arrows to indicate that
there may be one or more lines. Depending upon the digital code applied at the SELECT inputs, one
data is transmitted to the single output channel out of many. The pin out of a 16:1
Demultiplexer IC 74154 is shown above. The output of this circuit is active low. This is a 24-pin
DIP.
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PROCEDURE: -
1) Assemble the circuit on bread board, as per above Pin diagram.
2) Give the logical inputs and check for the proper output, as per the truth table.
RESULT:
Hence verified the Demultiplexer (16:1) operation using IC-74154.
PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
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EXPERIMENT No:-– 7
AIM: - Design and test of an S-R flip-flop using NOR/NAND gates.
APPARATUS REQUIRED: -
1. Logic trainer kit
2. NAND gates ICs- 7400
3. NOR gates ICs-7402
4. Wires.
THEORY:
The SR flip-flop is one of the fundamental parts of the sequential circuit logic. SR flip-flop is a
memory device and a binary data of 1 – bit can be stored in it. SR flip-flop has two stable states in
which it can store data in the form of either binary zero or binary one. Like all flip-flops, an SR
flip-flop is also an edge sensitive device. SR flip–flop is one of the most vital components in digital
logic and it is also the most basic sequential circuit that is possible. The S and R in SR flip-flop
means ‘SET’ and ‘RESET’ respectively. Hence it is also called Set–Reset flip- flop. The symbolic
representation of the SR Flip Flop is shown below.
Working Principle:
SR flip-flop works during the transition of clock pulse either from low to high or from high to low
(depending on the design) i.e. it can be either positive edge triggered or negative edge triggered.
For a positive edge triggered SR flip-flop, suppose, if S input is at high level (logic 1) and R input
is at low level (logic 0) during a low to high transition on clock pulse, then the SR flip-flop is said
to be in SET state and the output of the SR flip-flop is SET to 1. For the same clock situation, if
the R input is at high level (logic 1) and S input is at low leve l (logic 0), then the SR flip-flop is
said to be in RESET state and the output of the SR flip-flop is RESET to 0. The SR flip-flops can
be designed by using logic gates like NOR gates and NAND gates.
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S-R Flip-Flop Using NAND Gate
SR flip flop can be designed by cross coupling of two NAND gates. It is an active low input SR
flip-flop. The circuit of SR flip-flop using NAND gates is shown in below figure:
R – S flip-flop using NOR gates
PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
RESULT:
Design of S-R Flip flop using NAND & NOR gates was verified successfully.
PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
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EXPERIMENT – 8
AIM: -Verify the truth table of a J-K flip-flop (7476 IC)
APPARATUS REQUIRED: -
1. Logic trainer kit
2. Flip-flop ICs- 7476
3. Wires
THEORY:
The JK flip-flop is the modified version of SR flip-flop with no invalid state; i.e. the state J=K=1 is
not forbidden. It works such that J serves as set input and K serves as reset. The only difference is
that for the combination J=K=1 this flip-flop; now performs an action: it inverts its state.
Truth Table
Q J K Q(t+1
0 0 0 0)
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
The flip-flop is constructed in such a way that the output Q is ANDed with K and CP. This
arrangement is made so that the flip-flop is cleared during a clock pulse only if Q was previously 1.
Similarly, Q’ is ANDed with J and CP, so that the flip-flop is cleared during a clock pulse only if
Q’ was previously 1.
When J = K = 0
When both J and K are 0, the clock pulse has no effect on the output and the output of the flip-flop
is the same as its previous value. This is because when both the J and K are 0, the output of their
respective AND gate becomes 0.
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When J=0, K=1
When J=0, the output of the AND gate corresponding to J becomes 0 (i.e.) S=0 and R=1.
Therefore, Q’ becomes 0.
This condition will reset the flip-flop. This represents the RESET state of Flip-flop.
When J=1, K=0
In this case, the AND gate corresponding to K becomes 0(i.e.) S=1 and R=0. Therefore, Q
becomes 0. This condition will set the Flip-flop. This represents the SET state of Flip-flop.
When J=K=1
Consider the condition of CP=1 and J=K=1. This will cause the output to complement again and
again. This complement operation continues until the Clock pulse goes back to 0. Since this
condition is undesirable, we have to find a way to eliminate this condition. This undesirable
behavior can be eliminated by Edge triggering of JK flip - flop or by using master slave JK Flip-
flops.
OBSERVATION TABLE:
Inputs Theoretical Experimental
Outputs Output
J K CLK PRE CLR Q & Condition Q & Condition
X X L 0 0
X X L 0 1
X X L 1 0
X X L 1 1
0 0 L 1 1
0 1 L 1 1
1 0 L 1 1
1 1 L 1 1
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PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
RESULT:
Thus the J-K Flip flop was designed and truth table is verified.
PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
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VIVA QUESTIONS
1. What do you mean by Logic Gates?
2. What are the applications of Logic Gates?
3. What is Truth Table?
4. Why we use basic logic gates?
5. Write down the truth table of all logic gates?
6. What do you mean by universal gate?
7. Write truth table for 2 I/P OR, NOR, AND and NAND gate?
8. Implement all logic gate by using Universal gate?
9. Why is they called Universal Gates?
10. Give the name of universal gate?
11. Draw circuit diagram of Half Adder circuit?
12. Draw circuit diagram of Full Adder circuit?
13. Draw Full Adder circuit by using Half Adder circuit and minimum no. of logic gate?
14. Write Boolean function for half adder? Q.5 Write Boolean function for Full adder?
15. Design the half Adder & Full Adder using NAND-NAND Logic.
16. Draw circuit diagram of Half Subtractor circuit?
17. Draw circuit diagram of Full Subtractor circuit?
18. Draw Full Subtractor circuit by using Half Subtractor circuit and minimum no. of logic gate?
19. Write Boolean function for half Subtractor?
20. Write Boolean function for Full Subtractor?
21. What is Excess-3 code? Why it is called Excess-3 code?
22. What is the application of Excess-3 Code?
23. What is ASCII code?
24. Excess-3 code is Weighted or Unweighted?
25. Out of the possible 16 code combination? How many numbers used in Excess-3 code?
26. What is Demorgan’s Law?
27. Show the truth table for Demorgan’s Theorem?
28. What is Minterm & Maxterm?
29. How Minterm can be converted in Max term?
30. What is Hybrid function?
31. What is Flip-Flop?
32. What is Latch circuit?
33. Draw a truth –tables of S-R, J-K, D and T?
34. What is the disadvantages of S-R Flip-Flop?
35. How can you remove the problem of S-R Flip –Flop?
36. Make circuit diagram of S-R, J-K, D and T Flip-Flop?
37. What do you understand by Race Aground condition? How it is over come in J-K Flip Flop?
38. Explain the principle of Multiplexer?
39. Draw a circuit diagram of 4: 1 Multiplexer?
40. What are the advantages of Multiplexer?
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41. What are the disadvantages of Multiplexer?
42. Make the Truth-table of Multiplexer?
43. Explain about Demultiplexer?
44. Draw a circuit diagram of 1: 4 Demultiplexer?
45. Make a logic diagram of 1: 4 Demultiplexer?
46. What is the application of Demultiplexer?
47. What is the difference between Multiplexer and Demultiplexer?
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