Fetch–Decode–Execute for Instruction: ADD R1, R2
Goal
This document constructs the complete fetch–decode–execute (FDE) sequence for the
instruction ADD R1, R2 on a generic multi-cycle CPU. We list the micro-operations per cycle and
the control signals.
Assumptions & Notation
• Word-addressed memory; PC increments by 1 word.
• Register-transfer notation: X ← Y is a one-cycle transfer.
• Example signals: PCout, MARin, MemRead, MDRin, IRin, RegWrite, ALUop.
Block Purpose / Role
PC Holds the address of the next instruction to fetch.
MAR Carries the memory address for the current access.
MDR Holds data coming from or going to memory.
IR Holds the current instruction for decoding.
RegFile General-purpose registers; two read ports and one write port.
A, B Operand latches to hold register outputs for ALU.
ALU Performs arithmetic/logic; outputs to ALUOut.
ALUOut Latch for ALU result used in later cycles.
Big Picture: Cycle Breakdown
We use a 4-cycle breakdown for an R-type ALU instruction: Fetch → Decode/Register Read →
Execute → Write-Back.
Cycle 1 — Instruction Fetch
1) MAR ← PC
2) MemRead=1; MDR ← Mem[MAR]
3) IR ← MDR
4) PC ← PC + 1
Signal Meaning Asserted?
PCout Drive PC onto bus for addressing. 1
MARin Latch bus into MAR. 1
MemRead Start instruction memory read. 1
MDRin Latch memory data into MDR. 1
IRin Latch MDR into IR. 1
ALUSrcA=PC Select PC as ALU A input. 1
ALUSrcB=+1 Constant 1 (word step) to ALU B. 1
ALUop=ADD ALU performs addition for PC+1. 1
PCWrite Write back ALU result into PC. 1
Cycle 2 — Decode & Register Read
1) Decode IR fields (opcode, rs, rt, rd)
2) A ← Reg[rs]
3) B ← Reg[rt]
Signal Meaning Asserted?
RegSrc=rs/rt Select read ports for rs and rt. 1
RegRead Enable register file read. 1
Ain Latch Rs value into A. 1
Bin Latch Rt value into B. 1
Cycle 3 — Execute (ALU Operation)
ALUOut ← A + B
Signal Meaning Asserted?
ALUSrcA=A Select A latch as ALU input A. 1
ALUSrcB=B Select B latch as ALU input B. 1
ALUop=ADD Perform addition. 1
ALUOutIn Latch ALU result into ALUOut. 1
Cycle 4 — Write-Back
Reg[rd] ← ALUOut (rd = R1)
Signal Meaning Asserted?
RegDst=rd Select rd field as the destination register. 1
MemToReg=0 Select ALUOut (not memory) for write-back. 1
RegWrite Enable register file write port. 1
Timing Summary
Clock Key Signals High
T1 PCout, MARin, MemRead, MDRin, IRin, ALUSrcA=PC, ALUSrcB=+1, ALUop=ADD, PCWrite
T2 RegRead, Ain, Bin
T3 ALUSrcA=A, ALUSrcB=B, ALUop=ADD, ALUOutIn
T4 RegDst=rd, MemToReg=0, RegWrite
Variations & Notes
• Byte-addressed machines with 32-bit instructions use PC ← PC + 4 instead of +1.
• Single-cycle vs multi-cycle vs 5-stage pipeline (IF, ID, EX, MEM, WB): ADD completes WB
without MEM read.
• Example ISA mapping (MIPS-like): opcode=0, funct=0x20; rs=R1, rt=R2, rd=R1.
Signal Effect / Destination
PCout / PCWrite Places PC on bus / writes new PC value.
MARin / MDRin Address into MAR / data into MDR.
MemRead / MemWrite Initiate read or write to memory.
IRin Loads current instruction into IR.
RegRead / RegWrite Enable register file read or write.
RegDst Selects destination register (rd vs rt).
MemToReg Selects WB source (memory vs ALU).
ALUSrcA / ALUSrcB Chooses ALU inputs (PC, A, B, constants).
ALUop Selects ALU operation (ADD, SUB, AND, OR, etc.).
Ain / Bin / ALUOutIn Latch enables for operand and result latches.
Worked Example: PC=100, R1=5, R2=3; after execution, R1=8 and PC=101 (word addressed).