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Flip-Flops and Their Applications in Digital Logic

Module 3 covers flip-flops and their applications, detailing basic bistable elements, latches, and various types of counters. It explains the operation of SR latches, gated D latches, and the importance of setup and hold times to prevent metastability. Additionally, it discusses the characteristics and applications of different registers and counters, including synchronous and asynchronous types.

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s9charan.2006
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37 views32 pages

Flip-Flops and Their Applications in Digital Logic

Module 3 covers flip-flops and their applications, detailing basic bistable elements, latches, and various types of counters. It explains the operation of SR latches, gated D latches, and the importance of setup and hold times to prevent metastability. Additionally, it discusses the characteristics and applications of different registers and counters, including synchronous and asynchronous types.

Uploaded by

s9charan.2006
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Module 3:

FLIP-FLOPS AND ITS APPLICATIONS


Basic Bistable elements:

• It has two cross-coupled inverters, 2 outputs Q and Q’.


• It is called “Bistable” as the basic bistable element circuit has two
stable states logic 0 and logic 1.
• The following diagram shows the Basic Bistable element.
• The 2 outputs are always complementary.
• The circuit has 2 stable states. when Q=1, it is Set state. when Q=0,
it is Reset state.
• The circuit can store 1-bit of digital information and so it is called
one-bit memory cell.
• The one-bit information stored in the circuit is locked or latched in
the circuit. This circuit is also called Latch.
• Third stable state is metastable state.
Latches:
Application of SR latch:
S’R’ Latch:
Gated SR Latch
Timing Diagram of SR latch
Gated D Latch:
Timing diagram of Gated D latch:
Propagation Delay:
Setup Time and Hold Time:
Setup Time:
The time before the required control signal edge, during which the input must be ready and
held constant is called the set up time.

Hold Time:
The time after the required control signal edge has passed, during which the input has to be
held constant is called the Hold time.

Note : if setup and hold time requirements are not met the output might enter a metastable
state, until next set of inputs enforce one of the stable states.
Minimum Pulse width:
MS JK Flip Flop:
Characteristics Equation:
Characteristics Equation:
Flip Flop Applications:

•Registers : Mostly Memory, like devices which can remember bits


of data along with capability of rotating, shifting and rearranging
bits specified number of times.
•Counters/Timers: Also are memory like devices, but it is used to
count an event, or it can be used as timer, where it signals(sends
out a signal) after an amount of time has lapsed, to begin an event.
It can up count , down count or generate random counts(Finite).
SISO Register:
SIPO Register:
SISO,SIPO,PIPO, PISO Register:
Universal Shift Register(USR):
Counter:
• Generic Counter- state diagram of counter(Finite states):
• Up counting
• Down counting
• Random counting

There are 2 types of Counters based on application of clock:


• Asynchronous Counters
• Synchronous Counter
Asynchronous Binary counter/ Ripple Counter:
Binary Synchronous Counter:
Better version of Synchronous
Counter or variation of
Synchronous counter:
4-bit Binary synchronous
Counter with parallel load
capability:
4-bit Synchronous
counter implemented
as Mod -10 counter:
8-bit Synchronous
counter using two 4-
bit synchronous
counter:
Counters using shift Register/Non Binary
Counter:
i) Ring Counter(Mod-4):
ii)Twisted / Johnson Ring counter:
Twisted ring counter with Odd –
Sequence:

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