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Verilog Syntax and Hierarchical Identifiers

The document outlines lexical conventions in Verilog, including examples of white space, comments, unique names, legal identifiers, and escape identifiers. It also provides a hierarchical identifier example with a simple adder program, detailing input and output port declarations, internal variables, and a testbench for driving inputs and displaying results. The code demonstrates how to structure a Verilog module and utilize hierarchical paths.

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nguyentuankiet20cm
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8 views4 pages

Verilog Syntax and Hierarchical Identifiers

The document outlines lexical conventions in Verilog, including examples of white space, comments, unique names, legal identifiers, and escape identifiers. It also provides a hierarchical identifier example with a simple adder program, detailing input and output port declarations, internal variables, and a testbench for driving inputs and displaying results. The code demonstrates how to structure a Verilog module and utilize hierarchical paths.

Uploaded by

nguyentuankiet20cm
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

1.

Lexical Conventions
- Example of White Space:
module addbit (
input wire a, b, cin,
output wire sum, co,
);
endmodule

- Example of Comments:
module addbit (
// Input ports
input wire a, b, cin,

// Output ports
output wire sum, co
);
endmodule

- Example of Unique names:


 input // a verilog keyword
 wire // a verilog keyword
 Wire // a unique name (not a keyword)
 WIRE // a unique name (not a keyword)

- Example of legal identifiers:


data_input mu
clk_input my$clk
i386 A

- Example of escape identifiers:


// There must be white space after the
// string which uses escape character
module \1dff (
q, // Q output
\q~ , // Q_out output
d, // D input
cl$k, // CLOCK input
\reset* // Reset input
);
input d, cl$k, \reset* ;
output q, \q~ ;

endmodule

2. Hierarchical Identifiers
- Code:
//-----------------------------------------------------
// This is simple adder Program
// Design Name : adder_hier
// File Name : adder_hier.v
// Function : This program shows verilog hier path works
// Coder : Deepak
//-----------------------------------------------------
`include "addbit.v"
module adder_hier (
result , // Output of the adder
carry , // Carry output of adder
r1 , // first input
r2 , // second input
ci // carry input
);

// Input Port Declarations


input [3:0] r1 ;
input [3:0] r2 ;
input ci ;

// Output Port Declarations


output [3:0] result ;
output carry ;

// Port Wires
wire [3:0] r1 ;
wire [3:0] r2 ;
wire ci ;
wire [3:0] result ;
wire carry ;

// Internal variables
wire c1 ;
wire c2 ;
wire c3 ;
// Code Starts Here
addbit u0 (r1[0],r2[0],ci,result[0],c1);
addbit u1 (r1[1],r2[1],c1,result[1],c2);
addbit u2 (r1[2],r2[2],c2,result[2],c3);
addbit u3 (r1[3],r2[3],c3,result[3],carry);

endmodule // End Of Module adder

module tb();

reg [3:0] r1,r2;


reg ci;
wire [3:0] result;
wire carry;

// Drive the inputs


initial begin
r1 = 0;
r2 = 0;
ci = 0;
#10 r1 = 10;
#10 r2 = 2;
#10 ci = 1;
#10 $display("+--------------------------------------------------------+");
$finish;
end

// Connect the lower module


adder_hier U (result,carry,r1,r2,ci);

// Hier demo here


initial begin
$display("+--------------------------------------------------------+");
$display("| r1 | r2 | ci | [Link] | [Link] | [Link] | [Link] |");
$display("+--------------------------------------------------------+");
$monitor("| %h | %h | %h | %h | %h | %h | %h |",
r1,r2,ci, [Link], [Link], [Link], [Link]);
end
endmodule

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