Microprocessor Question Paper Solutions (Marks: 3, 4, 7)
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Q.1
(a) List the key parts of a microprocessor and give a short explanation of their functions. (3 marks)
1. ALU (Arithmetic Logic Unit) - performs arithmetic (ADD, SUB) and logic (AND, OR, XOR) operations.
2. Registers - small fast storage inside CPU (accumulator, general purpose, program counter, stack pointer, flag register)
used for temporary data and control.
3. Control Unit - generates timing/control signals (RD, WR, ALE, INTA) to coordinate operations.
Example: In 8085 the accumulator (A) holds operand/result for ALU operations.
(b) Explain memory and I/O operations in a microprocessor. (4 marks)
Memory operations: The CPU places a memory address on the address bus, asserts MEMR/RD to read (memory drives
data onto data bus) or MEMW/WR to write (CPU places data on data bus). Timing is governed by machine cycles and
T-states.
Example: LDA 2050H - places address 2050H on bus, memory supplies byte to accumulator.
I/O operations: For separate I/O space (like 8085), CPU uses IO/M control to indicate I/O cycle; IN reads from an I/O
port, OUT writes. Address lines select the peripheral, RD/WR signals control data transfer.
Example: OUT 01H writes accumulator contents to I/O port 01H.
(c) Describe the architecture of the 8085 microprocessor with a neat diagram. (7 marks)
Architecture summary:
1. Registers: A (Accumulator), B,C,D,E,H,L (general purpose pair registers), Program Counter (PC), Stack Pointer (SP),
Flag register (S,Z,AC,P,C).
2. ALU: Performs arithmetic/logic on accumulator and other registers; sets flags.
3. Control Unit: Generates timing and control signals (ALE, RD, WR, IO/M, INTA).
4. Instruction Register & Decoder: Accepts opcode fetched from memory and decodes the instruction.
5. Timing and Control: Generates T-states and control sequences for each machine cycle.
6. Address Bus (16-bit) and Data Bus (8-bit): For addressing and data transfer.
7. Serial I/O and Interrupts: Serial in/out pins, five interrupt lines (TRAP, RST7.5, RST6.5, RST5.5, INTR).
8. Machine Cycle Flow: Opcode fetch -> decode -> operand fetch / memory read-write / I/O / execution.
Working: On reset PC=0000H, control unit issues memory read (opcode fetch) using address bus; the instruction is
decoded and executed via ALU/register transfers, possibly involving memory/I/O cycles.
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Q.2
(a) Explain Assembler, Debugger and Linker with an example. (3 marks)
- Assembler: Translates assembly language source into machine code (object file). Example: MVI A, 45H becomes
opcode 3E 45.
- Debugger: Tool to run/step through program, inspect registers/memory, set breakpoints.
- Linker: Combines object modules and resolves addresses/symbols to create final executable image (for multi-module
programs).
(b) Explain Read/Write control signals for memory and I/O. (4 marks)
- RD / MEMR: Read signal - asserted by CPU when it wants to read data from memory or I/O.
- WR / MEMW: Write signal - asserted when CPU writes data.
- IO/M: Distinguishes between memory and I/O cycles. IO/M = 0 => memory operation; IO/M = 1 => I/O operation.
- ALE (Address Latch Enable): Indicates that the low-order AD0-AD7 lines contain address info (for multiplexed
address/data bus). ALE goes high in T1 to latch the low address into an external latch, then AD0-AD7 become data
lines.
(c) Draw and Explain Timing Diagram of MVI A, 45H. (7 marks)
Instruction: MVI A, 45H (2 bytes: opcode 3E then immediate data 45H).
Machine cycles:
1. Opcode Fetch (M1): 3 T-states (T1, T2, T3)
- T1: Address on address bus, ALE high, IO/M=0, RD asserted.
- T2: Memory drives opcode onto data bus.
- T3: Increment PC.
2. Memory Read (M2): 3 T-states.
- T1: Next address on bus, ALE pulses, RD asserted.
- T2: Memory places immediate byte (45H) on data bus.
- T3: Execution: data loaded into accumulator A.
Signals: ALE, IO/M, RD used for control.
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Q.3
(a) Explain Program Counter and Stack Pointer in 8085. (3 marks)
- Program Counter (PC): 16-bit register holding address of next instruction to fetch.
- Stack Pointer (SP): 16-bit register pointing to current top of stack in memory. Stack grows downward.
Example: CALL 2050H pushes PC onto stack, then PC set to 2050H.
(b) Describe the instruction cycle and machine cycles. (4 marks)
Instruction cycle: Sequence from fetching an instruction to completing its execution. It consists of machine cycles like
Opcode Fetch, Memory Read/Write, I/O Read/Write, etc.
Machine cycle: Basic bus operation such as opcode fetch (M1), memory read/write. Each machine cycle has several
T-states (T1, T2, T3...).
Example: LXI H,2050H has 3 machine cycles.
(c) Assembly program for demultiplexing address/data bus. (7 marks)
Program:
ORG 0000H
START: MVI A,55H
LXI H,2050H
MOV M,A
LXI H,2050H
MOV A,M
HLT
Explanation:
ALE is used to latch lower address (AD0-AD7) using external latch (74LS373). After ALE goes low, bus lines carry
data. During MOV M,A, memory write occurs; during MOV A,M, memory read occurs.
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Q.4
(a) Define I/O ports and describe their role. (3 marks)
I/O ports are hardware addresses/registers used to interface CPU with peripherals. Allow communication with external
devices.
Example: IN 00H reads keyboard input, OUT 01H sends data to display.
(b) Explain the working of the 8255 PPI. (4 marks)
- 8255 provides 24 programmable I/O lines grouped as Port A, Port B, Port C.
- Modes of operation:
Mode 0: Simple input/output.
Mode 1: Handshake I/O.
Mode 2: Bidirectional bus.
- Control Word configures ports as input/output.
Example: Control word 10011011B makes Port A output, Port B input, Port C used for control.
(c) Discuss interrupt architecture of 8085. (7 marks)
Types:
- Hardware: TRAP, RST7.5, RST6.5, RST5.5, INTR.
- Software: RST instructions.
Priority: TRAP > RST7.5 > RST6.5 > RST5.5 > INTR.
TRAP non-maskable; others maskable.
Interrupt process: Peripheral requests -> CPU completes current instruction -> Acknowledges interrupt -> Pushes PC ->
Jumps to ISR.
Example: RST6.5 jumps to address 0030H.
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Q.5
(a) Concept of segmentation in 8086. (3 marks)
Segmentation divides memory into 64KB segments. Four segment registers: CS, DS, SS, ES. Physical address =
Segment*16 + Offset.
Example: CS=2000H, IP=0004H => Physical address=20004H.
(b) Compare minimum and maximum mode of 8086. (4 marks)
Minimum Mode (MN/M=1): Single processor system. CPU generates control signals directly.
Maximum Mode (MN/M=0): Multiprocessor system. 8288 bus controller generates signals. Supports coprocessor
(8087).
Example: Minimum mode for standalone system, maximum for multiprocessor setup.
(c) Architecture and programming model of 80386. (7 marks)
Architecture:
- 32-bit CISC processor with 32-bit address/data bus (4GB memory).
- Registers: EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP.
- Segment Registers: CS, DS, SS, ES, FS, GS.
- Control Registers: CR0-CR4 for enabling protected mode, paging.
- Protected Mode: Supports multitasking, memory protection, virtual memory.
- Paging: 4KB pages with 2-level translation (page directory + table).
- Descriptor Tables: GDT, LDT, IDT.
Programming Model:
EAX, EBX, ECX, EDX (data), ESI, EDI (index), EBP, ESP (stack). Flags in EFLAGS register. EIP as instruction
pointer.
Example: MOV EAX,12345678H loads 32-bit value into EAX.