Architecture Microprocessor

Contents Page

1 Introduction 4 Pin diagram

CONTENTS
2 Programming Model 5 Functional Block diagram

3 Bus Organization 6 Memory Interfacing

1

PART ONE

Introduction-
8085
 Introduction

It works on 5-Volt DC power supply. 8085 is pronounced as "eighty-eighty-five" microprocessor.

It is a single chip N MOS device with 40 pins. 8085 It is an 8-bit microprocessor designed by Intel in 1977

It has multiplexed address and data bus.(AD0 - AD7). 8 bit General purpose microprocessor (i.e. 8 bit data bus).
 Introduction

It provides accumulator, 5 flag register, 6 general purpose The maximum clock frequency is 3MHz while minimum
registers and 2 special purpose registers (SP,PC). frequency is 500kHz.

It generates 8 bit I/O address so

it can access 28 = 256 input ports 8085 It supports external interrupt request.

It has two 16 bit registers named program counters

(PC) and stack pointer (SP). It provides 16 address lines, therefore capable of addressing
216 = 64K of memory.
2

PART TWO

Programing model
 Accumulator A (8) Flag Register

General Purpose Registers

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Address Bus 16
8 Data Bus

Bidirectional Unidirectional
 Accumulator A (8) Flag Register

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

• 8 - bit register, identified as A 16 Address Bus

Data Bus 8 • Part of ALU
• Used to store 8-bit data to perform arithmetic &
logical operations.
Bidirectional • Result of operation is stored in Accumulator. Unidirectional
 Accumulator A (8) Flag Register

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

• 6 general purpose registers to store 8-bit data B, C, D, E, H & 16 Address Bus

Data Bus 8 L.
• Can be combined as fixed register pairs – BC, DE, HL to
perform 16 bit operations.
Bidirectional • Used to store or copy data using data copy instructions. Unidirectional
 Accumulator A (8) Flag Register

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

16 Address Bus
Data Bus 8 • Used as memory pointer.
• Points to the memory location in R/W memory, called Stack.
• Beginning of stack is defined by loading a 16-bit address in
the stack pointer.
Bidirectional Unidirectional
 Accumulator A (8) Flag Register

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

• Microprocessor uses PC register to sequence the execution of

instructions. 16 Address Bus
Data Bus 8
• Its function is to point to memory address from which next byte is to
be fetched.
• When a byte is being fetched, PC is incremented by 1 to point next
Bidirectional memory location. Unidirectional
 Accumulator A (8) Flag Register

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

• ALU has 5 Flag Register that set/reset after an operation

16 Address Bus
Data Bus 8 according to data conditions of the result in accumulator & other
registers.
• Helpful in decision making process of microprocessor.
• Conditions are tested through software instructions.
Bidirectional Unidirectional
 Flag Register
D7 D6 D5 D4 D3 D2 D1 D0

S Z  AC  P  CY

1 0 1 1 1 1 1 0
1 1 1
S=1
0 0 1 0 1 0 1 0
+ 0 1 1 0 1 0 0 1
Z -Zero Flag P -Parity Flag 1 0 0 1 0 0 1 1
S -Sign Flag
Set (1) when result is zero; Set (1) if result has
evenACno.
= 1of 1’s & Reset(0) if
(1) if 7th bit
Setotherwise of result is 1;
reset(0) result has odd no. ofCY1’s-Carry Flag
otherwise resetAC (0)-Auxiliary Carry Flag Set (1) if arithmetic operation results in carry;
:Undefined otherwise Reset(0)
Set (1) when carry bit is
generated by 3rd bit & passed
1 0 1 0 0 0 1 1 1 1 1
1 0 1 0 to bit 4th bit. otherwise
P=1 1 0 1 0 1 1 1 1
-1 0 1 0 Reset(0) + 0 1 1 0 1 0 0 0
0 0 0 0
1 0 0 0 1 0 1 1 1
Z=1
CY = 1
 Accumulator A (8) Flag Register

General Purpose Registers

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Address Bus 16
8 Data Bus

Bidirectional Unidirectional
3

PART THREE

Bus Organization
CPU Memory Input/output

Control Bus

System Bus
Address Bus

Data Bus
 A15
Address Bus
A0

Memory Input Output

8085 MPU Real

World

D7
Data Bus
D0

Control Bus
 A15
Address Bus
A0

Memory Input Output

8085 MPU Real

World
• The bus over which the CPU sends out the address of the memory location is
called as the address bus.
• Group of 16 unidirectional lines generally identified as A0 to A15,
D7 i.e. bits flow from microprocessor to peripheral devices.
• If there are N address lines thenData address 2N memory location.
it canBus
D0 • 16 address lines are capable of addressing 65536 memory locations. So, 8085
has 64K memory locations.

Control Bus
 A15 • Group of 8 lines identified as D0 to D7.
• They are bidirectional i.e. data Address Bus directions between microprocessor,
flow in both
A0
memory & peripheral.
• The data bus connects the I/O ports & CPU. So that CPU can write data to or read
data from the memory or I/O ports.

Memory Input Output

8085 MPU Real

World

D7
Data Bus
D0
• 8 data lines enable microprocessor to manipulate data ranging from 00H to FFH
(28=256 numbers).
Control Bus
• As Data bus is of 8-bit, 8085 is known as 8-bit Microprocessor.
 A15 • It comprises of various single lines that carry synchronization, timing & control
Address Bus
A0 signals.
• These signals are used to identify a device type with which MPU intends to
communicate.
• Some control signals are Read, Write and Opcode fetch etc.

Memory Input Output

8085 MPU Real

World

D7
Data Bus
D0

Control Bus
 A15
Address Bus
A0

Memory Input Output

8085 MPU Real

World

D7
Data Bus
D0

Control Bus
4

PART FOUR

Pin Diagram
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
IT HAS 40 PINS
TRAP 6 35 READY
RST7.5 7 34 IO/M
RST6.5 8 33 S1
RST5.5 9 32 RD
INTR 10 31 WR
1. Address bus
INTA 11 8085A 30 ALE
2. Multiplexed address/data bus
3. Control & status signals AD0 12 29 S0
4. Power supply & frequency signals AD1 13 28 A15
5. Externally initiated signals AD2 14 27 A14
6. Serial I/O ports AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
Address bus
SOD 4 37 CLK (OUT)

• 16 signal lines are used as address bus. SID 5 36 RESET IN

TRAP 6 35 READY
• However these lines are split into two segments: RST7.5 7 34 IO/M
A15 - A8 and AD7 - AD0 RST6.5 8 33 S1
RST5.5 9 32 RD
• A15 - A8 are unidirectional and used to carry high- INTR 10 31 WR
order address of 16-bit address.
INTA 11 8085A 30 ALE

• AD7 - AD0 are used for dual purpose. AD0 12 29 S0

AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA

Multiplexed address/data bus SOD 4 37 CLK (OUT)

SID 5 36 RESET IN
TRAP 6 35 READY
• Signal lines AD7-AD0 are bidirectional and serve dual RST7.5 7 34 IO/M
purpose.
RST6.5 8 33 S1
RST5.5 9 32 RD
• They are used as low-order address bus as well as
data bus. INTR 10 31 WR
INTA 11 8085A 30 ALE
• The low-order address bus can be separate from AD0 12 29 S0
these signals by using a latch (ALE).
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
Control & status signals
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
To identify nature of operation
TRAP 6 35 READY

Two Control Signals RST7.5 7 34 IO/M

1. RD(Read) RST6.5 8 33 S1
2. WR(Write) RST5.5 9 32 RD
Three Status Signals INTR 10 31 WR
1. S1 INTA 11 8085A 30 ALE
2. S0
AD0 12 29 S0
3. IO/M
To indicate beginning of operation AD1 13 28 A15
ALE(Address Latch Enable) AD2 14 27 A14
ALE 1, then Address bus AD3 15 26 A13
ALE 0, then Data bus
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA

RD: Read SOD 4 37 CLK (OUT)

SID 5 36 RESET IN
• This is a read control signal (active low) TRAP 6 35 READY
• This signal indicates that the selected I/O or Memory RST7.5 7 34 IO/M
device is to be READ & data is available on data bus. RST6.5 8 33 S1
RST5.5 9 32 RD
INTR 10 31 WR
WR : Write
INTA 11 8085A 30 ALE
• This is a write control signal (active low) AD0 12 29 S0
• This signal indicates that the selected I/O or Memory AD1 13 28 A15
device is to be WRITE & data is available on data bus.
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
IO/M: Input/Output & Memory SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
TRAP 6 35 READY
• This is a status signal used to differentiate I/O & Memory
operation. RST7.5 7 34 IO/M
RST6.5 8 33 S1
When signal is RST5.5 9 32 RD
High I/O operation INTR 10 31 WR
Low Memory operation INTA 11 8085A 30 ALE
AD 12 29 S0
• This signal is combined with RD and WR to generate I/O &0
memory control signals. AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
Status Signals
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
To identify nature of operation
TRAP 6 35 READY

S1 S0 RST7.5
Operation 7 34 IO/M
RST6.5 8 33 S1
0 0 HLT
RST5.5 9 32 RD
INTR 10 31 WR
0 1 WRITE 8085A
INTA 11 30 ALE

1 0 READ
AD0 12 29 S0
AD1 13 28 A15
1 1 OPCODE FATCH
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
ALE: Address Latch Enable
SOD 4 37 CLK (OUT)
ALE 1 SID 5 36 RESET IN
TRAP 6 35 READY
• This is positive going pulse generated every time the 8085RST7.5 7 34 IO/M
begins an operation (machine cycle).
RST6.5 8 33 S1
• It indicates that the bits on AD7-AD0 are address bits.
RST5.5 9 32 RD
• This signal is used primarily to latch the low-address from
multiplexed bus & generate a separate set of address lines INTR 10 31 WR

A7-A0. INTA 11 8085A 30 ALE

AD0 12 29 S0
ALE 0
AD1 13 28 A15

• Negative going pulse will indicate that bits on multiplexedAD2 14 27 A14

bus are data D7-D0. AD3 15 26 A13

AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
8085 PIN DIAGRAM

I0/M RD WR Operation

0 0 0 HLT

0 0 1 MEMR
0 1 0 MEMW

0 1 1 Opcode
Fetch

1 0 0 HLT

1 0 1 IOR

1 1 0 IOW
1 1 1 NA
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
Power supply & frequency signals
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
Vcc → +5V Supply.
Vss → Ground Reference TRAP 6 35 READY
RST7.5 7 34 IO/M
CLK (OUT) → Clock output RST6.5 8 33 S1
RST5.5 9 32 RD
• This signal is used as system clock for other I/O devices for
INTR 10 31 WR
synchronization with Microprocessor. 8085A
INTA 11 30 ALE

X1, X2 → Crystal Oscillator is connected at these two pins. AD0 12 29 S0

AD1 13 28 A15
• The frequency is internally divided by two; AD2 14 27 A14
• To operate a system at 3MHz, the crystal should have a frequency
AD3 15 26 A13
of 6MHz.
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA

Externally initiated signal SOD 4 37 CLK (OUT)

SID 5 36 RESET IN
One interrupt Acknowledgement
TRAP 6 35 READY
1. INTA
Three type of interrupt Signals RST7.5 7 34 IO/M
RST6.5 8 33 S1
1. INTR RST5.5 9 32 RD
2. RST 5.5, RST 6.5, RST 7.5
INTR 10 31 WR
3. TRAP
INTA 11 8085A 30 ALE
Five hand shake signals
1. HOLD AD0 12 29 S0
2. HLDA AD1 13 28 A15
3. RESET IN AD2 14 27 A14
4. RESET OUT
AD3 15 26 A13
5. READY
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
INTA → Output SOD 4 37 CLK (OUT)
• Interrupt Acknowledge. SID 5 36 RESET IN
TRAP 6 35 READY
RST7.5 7 34 IO/M
INTR → Input
RST6.5 8 33 S1
• Interrupt Request
• It is used for general purpose interrupt. RST5.5 9 32 RD
INTR 10 31 WR
INTA 11 8085A 30 ALE
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
RST 7.5, RST 6.5, RST 5.5 → Input
SOD 4 37 CLK (OUT)
• Restart Interrupts. SID 5 36 RESET IN
TRAP 6 35 READY
• These are vector interrupts that transfer the program RST 7.5 7 34 IO/M
control to specific memory locations. RST 6.5 8 33 S1
RST 5.5 9 32 RD
• RST7.5, RST6.5, RST5.5 have higher priorities than INTR
INTR 10 31 WR
interrupt.
INTA 11 8085A 30 ALE
• Among these 3 interrupts, the priority order is AD0 12 29 S0
AD1 13 28 A15
1. RST 7.5
AD2 14 27 A14
2. RST 6.5
3. RST 5.5 AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
TRAP → Input
SOD 4 37 CLK (OUT)
• This is a non maskable interrupt SID 5 36 RESET IN
• It has the highest priority. TRAP 6 35 READY
RST 7.5 7 34 IO/M
RST 6.5 8 33 S1
RST 5.5 9 32 RD
INTR 10 31 WR
INTA 11 8085A 30 ALE
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
HOLD → Input SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
• This signal indicates that a peripheral such as DMA
TRAP 6 35 READY
Controller is requesting the use of address & data buses.
RST7.5 7 34 IO/M
RST6.5 8 33 S1
HLDA → Output
RST5.5 9 32 RD
• Hold Acknowledge. INTR 10 31 WR
• This signal acknowledges the HOLD request INTA 11 8085A 30 ALE
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
RESET IN → Input
TRAP 6 35 READY

• RST7.5 is
When the signal on this pin goes low, the Program Counter 7 34 IO/M
set to zero, the buses are tri-stated & microprocessorRST6.5
is 8 33 S1
reset. RST5.5 9 32 RD
INTR 10 31 WR
INTA 11 8085A 30 ALE
RESET OUT → Output
AD0 12 29 S0

• This signal indicates that microprocessor is being reset.AD1 13 28 A15

• The signal is also used to reset other devices. AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
READY → Input
TRAP 6 35 READY

• This signal is used to delay the microprocessor read orRST7.5

write 7 34 IO/M
RST6.5
cycles until low-responding peripheral is ready to send or 8 33 S1
accept data. RST5.5 9 32 RD
INTR 10 31 WR
• When the signal goes low, the microprocessor waits for an
INTA 11 8085A 30 ALE
integral no. of clock cycles until READY signal goes high.
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC

8085 PIN DIAGRAM X2 2 39 HOLD

RESET OUT 3 38 HLDA
Serial I/O ports
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
Two pins for serial transmission
TRAP 6 35 READY

1. SOD (Serial Output Data) RST7.5 7 34 IO/M

2. SID (Serial Input Data) RST6.5 8 33 S1
RST5.5 9 32 RD
INTR 10 31 WR
• In serial transmission, data bits are sent over a single line,
INTA 11 8085A 30 ALE
one bit at a time.
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 X1 1 40 VCC
X2 2 39 HOLD
RESET OUT 3 38 HLDA
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
TRAP 6 35 READY
RST7.5 7 34 IO/M
RST6.5 8 33 S1
RST5.5 9 32 RD
INTR 10 31 WR
INTA 11 8085A 30 ALE
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
 +5 V
1 2 40 20 GND
5
Serial I/O Ports SID 4 28
SOD
High-Order Address Bus Address bus
6 21
TRAP 7
RST 7.5 8
RST 6.5 9
RST 5.5 10
INTR 19
Multiplexed Multiplexed
Externally Initiated
35 8085A Address/Data Bus address/data bus
Signals READY 39 12
HOLD
36
RESET IN 30 ALE
11 29
INTA 38
HLDA 33 Control and
34 IO/M Status Signals
32 RD
31 WR

Power & Frequency 3 37

Signal RESET OUT CLK OUT
5

PART FIVE

Functional Block
Diagram
 INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

Instructio
Accumulator (8) Temp. Reg. (8) Multiplexer
n Reg. (8)
W (8) Z (8)
Temp. Reg. Temp. Reg.
Instruction B (8) C (8)
Decoder Reg. Reg.
Flag (5) and

Register Select
D (8) E (8)
Flip-Flops Machine Reg. Reg.
Cycle H (8) L (8)
Encoding Reg. Reg.
Arithmetic Stack Pointer (16)
Logic Unit
Power +5 V (ALU) (8) Program Counter (16)
Supply GND
Increment/Decrement
Address Latch (16)
X1 CLK Reset
X2 GEN
Timing and Control
Control Status DMA Address Buffer Data/Address Buffer
(8) (8)

CLK RD WR S0 S1 IO/M HLDA RESET OUT

OUTREADY ALE HOLD RESET IN
• Used to store 8-bit data to perform arithmetic & logical operations. Used to hold data (i.e. temporary data)
• Result of operation is stored in Accumulator. during ALU operation.

8-Bit Internal Data Bus

Instructio
Accumulator (8) Temp. Reg. (8) When Instruction is fetched from memory,
n Reg. (8)
it is loaded in the Instruction Register (IR).

Instruction
Decoder
Flag (5) and
Flip-Flops Machine
Cycle
S Z AC P CY
Encoding

Arithmetic
Instruction decoder decodes the
Logic Unit
Power +5 V information present in the Instruction
(ALU) (8)
Supply GND register.

• Performs Computing Functions.

• Accumulator, Temporary Register and Flag
Registers are part of ALU.
 A multiplexer pulls out the right group of bits, depending on the
instruction.

8-Bit Internal Data Bus

• Each register can hold 8-bit data.
• These registers can work in pair to hold 16-bit data and their Multiplexer
pairing combination is like B-C, D-E & H-L.
W (8) Z (8)
Temp. Reg. Temp. Reg.
• Two additional 8-bit register, which holds the temporary data B (8) C (8)
during execution of some instructions. Reg. Reg.

Register Select
• They are used internally, so they are not available to the D (8) E (8)
programmer. Reg. Reg.
H (8) L (8)
Reg. Reg.
16-bit register used to store the memory address location of the next
instruction to be executed. Stack Pointer (16)

Program Counter (16)

• It increments the program counter as instructions execute, Increment/Decrement
increments and decrements the stack pointer as needed, and Address Latch (16)
supports the 16-bit increment and decrement instructions.

Address Buffer Data/Address Buffer

It is a 16-bit register works like stack, which is always
(8) (8)
• incremented/decremented
The content stored in thebySP
2 during
and PCpush & popinto
is loaded operations.
the Address Buffer and
Data/Address Buffer.
• The memory and I/O chips are connected to these buses that can exchange the
data.
 DMA control signal
Input signal to synchronize microprocessor with peripheral
device.

Perform synchronization with peripheral device. Shows read/write status to/from memory or I/O.

This unit synchronizes all the microprocessor operations with the clock and generates control signal necessary for
communication between microprocessor & peripheral.

Frequency Control Signals Read/write either to/from memory or peripherals.

Address Latch Enable control signal

Signal to RESET microprocessor and other
devices connected to it.
X1 CLK Reset
X2 GEN
Timing and Control
Control Status DMA

CLK RD WR S0 S1 IO/M HLDA RESET OUT

OUTREADY ALE HOLD RESET IN
 INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

• It controls the interrupts during a process.

• There are 5 interrupt signals in 8085 It controls the serial data communication by using two
microprocessor: instructions:
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR. i. SID (Serial input data)
ii. SOD (Serial output data)
 INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

Instructio
Accumulator (8) Temp. Reg. (8) Multiplexer
n Reg. (8)
W (8) Z (8)
Temp. Reg. Temp. Reg.
Instruction B (8) C (8)
Decoder Reg. Reg.
Flag (5) and

Register Select
D (8) E (8)
Flip-Flops Machine Reg. Reg.
Cycle H (8) L (8)
Encoding Reg. Reg.
Arithmetic Stack Pointer (16)
Logic Unit
Power +5 V (ALU) (8) Program Counter (16)
Supply GND
Increment/Decrement
Address Latch (16)
X1 CLK Reset
X2 GEN
Timing and Control
Control Status DMA Address Buffer Data/Address Buffer
(8) (8)

CLK RD WR S0 S1 IO/M HLDA RESET OUT

OUTREADY ALE HOLD RESET IN
6

PART SIX

Memory Interfacing
 T - States

T-States are defined as operation performed in one clock period.

T-State-1 T-State-2 T-State-3 T-State-4

CLK

These sub divisions are internal states synchronized with system clock & each T-state is precisely equal
to one clock period.
 Machine Cycle

Machine Cycle is defined as time required by the microprocessor to complete an operation.

Machine Cycle-1

T-State-1 T-State-2 T-State-3 T-State-4

CLK

Opcode Fetch

This cycle may consist 3 to 6 T-states.

 Machine Cycle

The basic microprocessor operation such as reading a byte from Memory & I/O port or writing
a byte to memory & I/O port.

Opcode Fetch Read Write

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

CLK

Machine Cycle-1 Machine Cycle-2 Machine Cycle-3

CLK

A15
High order Memory address Unspecified
A8
AD7
Low order
Memory address Opcode
AD0
Timing Diagram
Opcode
ALE Fatch

IO/M

RD
CLK

A15
High order Memory address Unspecified
A8
AD7
Low order
Memory address Data from processor
AD0
Timing Diagram
Memory
ALE Write

IO/M
IO/M=0, S1=0 , S0=1
S0

WR
CLK

A15
High order Memory address Unspecified
A8
AD7
Low order
Memory address Data from Memory
AD0
Timing Diagram
Memory
ALE Read

IO/M
IO/M=0, S1=1 , S0=0
S1

RD
 CLK

A15
High order Memory address Unspecified
A8
AD7
Low order
Memory address Data from I/O
AD0
Timing Diagram
I/O
ALE Read

S0
IO/M=1, S1=1 , S0=0
IO/M S1

RD
Memory Structure
Data Inputs
N= No of Memory location
WR
M=Word Length Input Buffer
CS
E.g. If a memory is having address lines=10 AN-1

Internal Decoder
data lines=8
then
NXM
1. number of registers / memory locations =
Memory
N= 210 = 1024
2. word length M= 8 bit
Therefore, N X M= 1024 X 8 A0
Output Buffer
RD

Data Output
Memory Structure
Memory size(bytes)(2n) No. of Lines (n)

2 1
4 2
8 3
16 4
32 5
64 6
128 7
256 8
512 9
1024 (1k) 10
2048 (2k) 11
4096 (4k) 12
8192 (8k) 13
16348 (16k) 14
32768 (32k) 15
65536 (64k) 16
Memory Structure

• 8085 can access 64K of memory, thus address bus is of 16-bit.

• It is not always necessary to use full 64K address space.
• Generally EPROM is used as a program memory and RAM is used as data memory.
• When both are used then total 64K address will be shared by both.
• The capacity of program memory and data memory depends on the application.
• program memory (EPROM) should be located from address 0000H, since reset address of
8085 microprocessor is 0000H.
• It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and
multiple RAMs as per the requirement.
 Example-1

Interface 4kB of EPROM with starting address from 0000H and 2kB of RAM with starting
address followed by EPROM

EPROM
Chip Size = 4kB (i.e. address Line=12, m/m = 212 = 4096B = 4k)

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Starting
Address = 0000H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ending 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Address = 0FFFH
 Example-1

Interface 4kB of EPROM with starting address from 0000H and 2kB of RAM with starting
address followed by EPROM

RAM
Starting address = Ending address of EPROM +1
= 0FFFH+1
= 1000H
Chip Size = 2kB (i.e. address Line=11, m/m = 211 = 2048B = 2k)

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Starting
Address = 1000H 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Ending 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
Address = 07FFH
EPROM A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Starting
Address = 0000H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ending
Address = 0FFFH 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM
Starting 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Address = 1000H
Ending 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
Address = 07FFH
00000
EPROM Y0
A15
• Required Address Lines: A11 to A15. To EPROM
• Now, EPROM has two Possibilities, either 00000 b or A14 Y1
00001 b.
• Therefore, it requires Y0 and Y1 outputs of decoder. 5:32 00001
A13
• RAM has 00010 b, hence it requires Y2 output of Decoder
decoder. A12 Y2
To RAM
A11 00010
 Example-2
Interface 16kB of EPROM with chip size of 8kB and starting address from 0000H and 8kB of
RAM with starting address followed by EPROM.

EPROM EPROM-1
Chip Size = 8kB Starting address = 0000 H
Total EPROM required = 16kB Chip Size = 8 kB (i.e. address Line=13, m/m = 213 = 8192B = 8k)
Chip required = 16kB/8kB = 2 Ending address = 1FFF H

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Starting
Address = 0000H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ending 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Address = 1FFFH
 Example-2
Interface 16kB of EPROM with chip size of 8kB and starting address from 0000H and 8kB of
RAM with starting address followed by EPROM.

EPROM-2
Starting address = 1FFF H +1 = 2000 H
Chip Size = 8 kB (i.e. address Line=13, m/m = 213 = 8192B = 8k) = 1FFF H
Ending address = 2000 H + 1FFF H = 3FFF H

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Starting
Address = 2000H 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Ending 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address = 3FFFH
 Example-2
Interface 16kB of EPROM with chip size of 8kB and starting address from 0000H and 8kB of
RAM with starting address followed by EPROM.

RAM
Starting address = EPROM End Address +1 = 3FFF H +1 = 4000 H
Chip Size = 8 kB (i.e. address Line=13, m/m = 213 = 8192B = 8k) = 1FFF H
Ending address = 4000 H + 1FFF H = 5FFF H

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Starting
Address = 4000H 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ending 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Address = 5FFFH
Example-2
Interface 16kB of EPROM with chip size of 8kB and starting address from 0000H and 8kB of
RAM with starting address followed by EPROM.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

EPROM-1 EPROM-2

0000H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1FFFH 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

2000H 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FFFH
4000H 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RAM

0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
5FFFH

EPROM chip size = RAM chip size = 8kB = 213

Therefore, neglect lower 13 address lines (i.e. A0 to A12) &
consider only A13 to A15 for decoding.
Example-2
Interface 16kB of EPROM with chip size of 8kB and starting address from 0000H and 8kB of
RAM with starting address followed by EPROM.

Y0 000
To EPROM CHIP-1
A15
Y1 001 To EPROM CHIP-2
A14 3:8
Decoder
A13 Y2 010 To RAM
Example-3
Interface 8kB of EPROM and 8kB of RAM using 4kB devices

Example-4

Draw the interfacing of a 4kB EPROM having a starting address 2000H and Two 2kB static RAMs
having starting addresses 6000H and 8000H, respectively, with 8085 microprocessor.
THANK YOU