VIPER26K

1050 V high voltage converter for ultra-wide input

Datasheet - production data

Description
The device is a high voltage converter smartly
integrating a 1050 V avalanche-rugged power
section, with a PWM current mode control. The
1050 V-BV power MOSFET allows to extend input
voltage range, and reduce the size of the DRAIN
snubber circuit. This IC meets the most stringent
energy-saving standards as it has very low
consumption and operates in burst mode under
Features light load.
The integrated HV startup, sense-FET, error
 1050 V avalanche-rugged power MOSFET
amplifier and oscillator with jitter allow a complete
 allowing ultra-wide VAC input range to be application to be designed with the minimum
covered number of components.
 Embedded HV startup and sense-FET The VIPer26K supports the most common SMPS
 Current mode PWM controller topologies such as: isolated flyback with
 Drain current limit protection: optocoupler, primary-side regulation, non-isolated
flyback with resistive feedback, buck, and buck
 -500 mA (VIPER265K) boost.
 -700 mA (VIPER267K)
 Jittered switching frequency reduces the EMI
filter cost: 60 kHz ± 4kHz
 Standby power < 30 mW at 230 VAC
 Embedded E/A with 3.3 V reference
 Safe auto-restart after a fault condition
 Hysteretic thermal shutdown
 Built-in soft-start for improved system reliability

Applications
 SMPS for energy metering
 Auxiliary power supplies for 3-phase input
industrial systems
 LED lighting
 Air conditioning

May 2019 DS12978 Rev 1 1/28

This is information on a product in full production. [Link]
 VIPER26K

Figure 1. Basic application schematic

2/28 DS12978 Rev 1

VIPer26K Contents

Contents

1 Pin setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical and thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Typical power capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Primary MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 High voltage startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 Current limit set point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8 FB pin and COMP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.9 Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10 Automatic auto restart after overload or short-circuit . . . . . . . . . . . . . . . . 18
4.11 Open loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.12 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Layout guidelines and design recommendations . . . . . . . . . . . . . . . . . . . 22

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 SO16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DS12978 Rev 1 3/28

28
Pin setting VIPER26K

1 Pin setting

Figure 2. Connection diagram

Table 1. Pin description

SO16
Name Function
N

Ground. Connected to the source of the internal power MOSFET and

1 GND
controller ground reference.

Not internally connected. It can be connected to GND (pin 1) or left

2, 3 N.C
floating.

Not available for user. This pin is mechanically connected to the controller
4 N.A.
die pad of the frame. It is highly recommended to connect it to GND (pin 1).

Supply voltage of the control section. This pin provides the charging
5 VDD
current of the external capacitor.

Not available for user. It is highly recommended to connect it to GND (pin

6 N.C.
1).

Inverting input of the internal trans-conductance error amplifier.

Connecting the converter output to this pin through a single resistor results
7 FB
in an output voltage equal to the error amplifier reference voltage. An
external resistors divider is required for higher output voltages.

Output of the internal trans conductance error amplifier. The

compensation network has to be placed between this pin and GND to
8 COMP achieve stability and good dynamic performance of the voltage control loop.
The pin is used also to directly control the PWM with an optocoupler. The
linear voltage range extends from VCOMPL to VCOMPH.

9-12 N.C. Not internally connected. It has to be left floating.

High voltage drain pin. The built-in high voltage switched start-up bias
13-16 DRAIN current is drawn from this pin too. Pins connected to the metal frame to
facilitate heat dissipation.

4/28 DS12978 Rev 1

VIPer26K Electrical and thermal ratings

2 Electrical and thermal ratings

Table 2. Absolute maximum ratings

Value
Symbol Pin Parameter(1),(2) Unit
Min. Max.

VDRAIN 13-16 Drain-to-source (ground) voltage 1.05 KV

Pulse drain current (limited by
IDRAIN 3 A
TJ = 150 °C)

Internally
VDD 5 Supply voltage -0.3 V
limited
IDD 5 Input current 20 mA

VFB 7 Feedback pin voltage -0.3 4.8 V

VCOMP 8 Input pin voltage -0.3 3.5 V

PTOT Power dissipation at TA < 60 °C 1.05(3) W

TJ Operating junction temperature range -40 150 °C

TSTG Storage temperature -55 150 °C

1. Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
2. Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability.
3. When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 μm thick).

Table 3. Thermal data

Symbol Parameter Max. value Unit

Thermal resistance junction to case (1)

RTH-JC 10 °C/W
(Dissipated power = 1 W)

Thermal resistance junction to case (2)

RTH-JC 5 °C/W
(Dissipated power = 1 W)

Thermal resistance junction ambient (1)

RTH-JA 120 °C/W
(Dissipated power = 1 W)

Thermal resistance junction ambient (2)

RTH-JA 85 °C/W
(Dissipated power = 1 W)
1. When mounted on a standard, single side FR4 board with minimum copper area.
2. When mounted on a standard, single side FR4 board with 100 mm2 of Cu (35 μm thick).

DS12978 Rev 1 5/28

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Electrical and thermal ratings VIPER26K

Figure 3. RthJA

Table 4. Avalanche characteristics

Value
Symbol Pin Parameter Unit
Min. Max.

IAR Repetitive avalanche current (limited by TJ = 150 °C) 1 A

EAV Repetitive avalanche energy (limited by TJ = 150 °C) 3 mJ

6/28 DS12978 Rev 1

VIPer26K Electrical characteristics

3 Electrical characteristics

(TJ = -40 to 125°C, VDD = 14V; unless otherwise specified.)

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit.
ID = 1 mA,
VBVDSS Breakdown voltage VCOMP = GND, 1.05 kV
TJ = 25°C

VDRAIN = 1050V,
Drain-source leakage
IDSS VCOMP = GND, 29 μA
current
TJ = 25°C

IDRAIN = 0.2 A;
7
TJ = 25 °C
Drain-Source ON state
RDS(on) 
resistance IDRAIN = 0.2 A;
14
TJ = 125 °C

Table 6. Supply section

Symbol Parameter Test conditions Min. Typ. Max. Unit

High voltage start-up current source

ID = 1 mA,
Startup breakdown drain-
VVDSS_SU VCOMP = GND, 1.05 kV
source voltage
TJ = 25°C

VHV_START Drain-source start voltage 38 60 V

VDRAIN = 50 V to
Charging current during
IDDch1 1.05 kV, -0.6 -1.8 mA
startup
VDD = 4 V

VDRAIN = 50 V to
Charging current in self-
IDDch2 1.05 kV, -7 -13 mA
supply
VDD = 9 V falling edge

IC supply and consumptions

VDD Operating voltage range 11.5 23.5 V

VDDclamp VDD clamp voltage IDD = 15 mA 23.5 V

VDDon VDD start up threshold 12 13 14 V

DS12978 Rev 1 7/28

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Electrical characteristics VIPER26K

Table 6. Supply section (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VDDon internal high voltage

VDDCSon 9.5 10.5 11.5 V
current generator threshold

VDD under voltage shutdown

VDDoff 7 8 9 V
threshold

Operating supply current, FOSC = 0 kHz,

IDD0 0.6 mA
not switching VCOMP = GND

Operating supply current, VDRAIN = 120 V,

IDD1 2 mA
switching FOSC = 60 kHz

Operating supply current

IDDoff VDD < VDDoff 0.35 mA
with VDD < VDDoff

Open loop failure current VDD = VDDclamp

IDDol 4 mA
threshold VCOMP = 3.3 V

Table 7. Controller section

Symbol Parameter Test conditions Min. Typ. Max. Unit

E/A

VREF_FB Input voltage 3.2 3.3 3.4 V

IFB_PULL UP Pull-up current -1 μA

GM Transconductance 2 mA/V

Compensation pin (Comp)

VCOMPH Upper saturation limit TJ = 25°C 3 V

VCOMPL Burst mode threshold TJ = 25°C 1 1.1 1.2 V

VHYS Burst mode hysteresis 40 mV

HCOMP ΔVCOMP/ΔIDRAIN TJ = 25°C 1.9 2.35 2.8 V/A

RCOMP(DYN) Dynamic resistance VFB = GND 15 kΩ

Source / sink Current VFB > 100mV 150 μA

ICOMP VCOMP = GND,
Max. source current 220 μA
VFB = GND

8/28 DS12978 Rev 1

VIPer26K Electrical characteristics

Table 7. Controller section (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Current limitation

VIPER267K
VCOMP = 3.3V, 0.66 0.7 0.74
TJ = 25°C
IDLIM Drain current limitation A
VIPER265K
VCOMP = 3.3V, 0.47 0.5 0.53
TJ = 25°C

tSS Soft-start time 8.5 ms

TON-MIN Minimum turn ON time 480 ns

IDLIM-BM Burst mode current limitation VCOMP = VCOMPL 127 mA

Overload

tOVL Overload time 50 ms

tRESTART Restart time after fault 1 s

Oscillator

TJ = -25 to 125°C 54 60 66
FOSC Switching frequency kHz
TJ = -40 to 125°C 44 60 66

FD Modulation depth ±4 kHz

FM Modulating frequency 240 Hz

DMAX Maximum duty cycle 70 80 %

Thermal shutdown

TSD Thermal shutdown temperature 150 160 °C

THYST Thermal shutdown hysteresis 30 °C

DS12978 Rev 1 9/28

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Electrical characteristics VIPER26K

3.1 Typical electrical characteristics

Figure 4. IDLIM vs. Tj Figure 5. FOSC vs. Tj

Figure 6. VHV_START vs. Tj Figure 7. VREF_FB vs. Tj

Figure 8. IDD0 vs. Tj Figure 9. IDD1 vs. Tj

10/28 DS12978 Rev 1

VIPer26K Electrical characteristics

Figure 10. GM vs. Tj Figure 11. HCOMP vs. Tj

Figure 12. ICOMP(source/sink) vs. Tj Figure 13. ICOMP(max source) vs. Tj

Figure 14. Power MOSFET capacitances Figure 15. VBVDSS vs. TJ

variation vs. VDS @ VGS=0, f=1MHz ....................................................

DS12978 Rev 1 11/28

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Electrical characteristics VIPER26K

Figure 16. RDS(on) vs. Tj Figure 17. Maximum avalanche energy vs. Tj

Figure 18. SOA SSOP10 package

12/28 DS12978 Rev 1

VIPer26K General description

4 General description

4.1 Block diagram

Figure 19. Block diagram

4.2 Typical power capability

Table 8. Typical power

Vin: 230 Vac Vin: 85-265Vac Vin: 85-440Vac

Adapter(1) Open frame(2) Adapter(1) Open frame(2) Adapter(1) Open frame(2)

16W 20W 10W 12W 10W 12W

1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heatsinking.

4.3 Primary MOSFET

The power section is implemented with an N-channel power MOSFET with a breakdown
voltage of 1050 V min. and a maximum RDS(ON) of 7 Ω. It includes a sense-FET structure to
allow a virtually lossless current sensing and the thermal sensor.
The gate driver of the power MOSFET is designed to supply a controlled gate current during
both turn-ON and turn-OFF in order to minimize common mode EMI. During UVLO
conditions, an internal pull-down circuit holds the gate low in order to ensure that the power
MOSFET cannot be turned ON accidentally.

DS12978 Rev 1 13/28

28
General description VIPER26K

4.4 High voltage startup

The high voltage current generator is supplied by the DRAIN pin. At the first startup of the
converter, it is enabled when the voltage across the input bulk capacitor reaches the
VDRAIN_START threshold, sourcing the IDDch1 current; as the VDD voltage reaches the VDDon
start-up threshold, the power section starts switching and the high voltage current generator
is turned OFF. The VIPer26K is powered by the external source. After the startup, the
auxiliary winding or the diode connected to the output voltage have to power the VDD
capacitor with voltage higher than the VDDCSon threshold. During the switching, the internal
current source is disabled and the consumptions are minimized.
In case of fault, the switching is stopped and the device is self-biased by the internal high
voltage current source; it is activated between the levels VDDCSon and VDDon, delivering the
current IDDch2 to the VDD capacitor during the MOSFET OFF time.
If a very low main input voltage is applied to the converter, it is strongly recommended to
choose the VDD capacitor value by the following formula:

Equation 1

I DDCH 1  t OVL
C VDD = ---------------------------------
-
V DD - V DDoff

At converter power-down, the VDD voltage drops and the converter activity stops as it falls
below the VDDoff threshold.

Figure 20. Timing diagram: normal power-up and power-down sequences

14/28 DS12978 Rev 1

VIPer26K General description

4.5 Oscillator
The switching frequency is internally fixed at 60 kHz.
The switching frequency is modulated by approximately ±4 kHz at 230 Hz (typical) rate, so
that the resulting spread spectrum action distributes the energy of each harmonic of the
switching frequency over a number of sideband harmonics having the same energy on the
whole but smaller amplitudes.

4.6 Soft-start
During the converters' start-up phase, the soft-start function progressively increases the
cycle-by-cycle drain current limit, up to the default value IDLIM. In this way, the drain current
is further limited and the output voltage is progressively increased reducing the stress on the
secondary diode. The soft-start time is internally fixed to tSS, and the function is activated for
any attempt of converter startup and after a fault event.
This function helps prevent transformer saturation during startup and short-circuit.

4.7 Current limit set point

The VIPer26K includes a current mode PWM controller: cycle by cycle the drain current is
sensed through the integrated resistor RSENSE and the voltage is applied to the non-
inverting input of the PWM comparator. As soon as the sensed voltage is equal to the
voltage derived from the COMP pin, the power MOSFET is switched OFF.
In parallel with the PWM operations, the comparator OCP checks the level of the drain
current and switches OFF the power MOSFET in case the current is higher than the
threshold IDlim.
The IC is available with two different drain current limitations: the VIPer267K has a 700 mA
(typical value), whereas the VIPer265K is available with 500 mA current limitation.
Both values are ensured with tolerance reported in Table 3.

4.8 FB pin and COMP pin

The device can be used both in non-isolated and in isolated topology. In the case of non-
isolated topology, the feedback signal from the output voltage is applied directly to the FB
pin as inverting input of the internal error amplifier having the reference voltage, VREF_FB.
The output of the error amplifier sources and sinks the current, ICOMP, respectively to and
from the compensation network connected on the COMP pin. This signal is then compared,
in the PWM comparator, with the signal coming from the sense-FET; the power MOSFET is
switched off when the two values are the same on a cycle-by-cycle basis.
When the power supply output voltage is equal to the error amplifier reference voltage,
VREF_FB, a single resistor has to be connected from the output to the FB pin. For higher
output voltages the external resistor divider is needed. If the voltage on the FB pin is
accidentally left floating, an internal pull-up protects the controller.
The output of the error amplifier is externally accessible through the COMP pin and it's used
for the loop compensation: usually an RC network.

DS12978 Rev 1 15/28

28
General description VIPER26K

In the case of isolated power supply, the internal error amplifier has to be disabled (FB pin
shorted to GND). In this case an internal resistor is connected between an internal reference
voltage and the COMP pin.
The current loop has to be closed on the COMP pin through the optocoupler in parallel with
the compensation network. The VCOMP dynamics range is between VCOMPL and VCOMPH.
When the voltage VCOMP drops below the voltage threshold VCOMPL, the converter enters
burst mode.
When the voltage VCOMP rises above the VCOMPH threshold, the peak drain current will
reach its limit, as well as the deliverable output power.

Figure 21. Feedback circuit

Figure 22. COMP pin vs. IDLIM

16/28 DS12978 Rev 1

VIPer26K General description

4.9 Burst mode

When the voltage VCOMP drops below the threshold, VCOMPL, the power MOSFET is kept in
the OFF state and the consumption is reduced to IDD0 current. As a reaction at the energy
delivery stop, the VCOMP voltage increases and as soon as it exceeds the threshold VCOMPL
+ VCOMPL_HYS, the converter starts switching again with consumption level equal to IDD1
current. This ON-OFF operation mode, referred to as “burst mode” and reported in Figure 4,
reduces the average frequency, which can go down even to a few hundred hertz, thus
minimizing all frequency-related losses and making it easier to comply with energy saving
regulations. During burst mode, the drain current limit is reduced to the value IDLIM_bm in
order to avoid the audible noise issue.

Figure 23. Load-dependent operating modes: timing diagram

4.10 Automatic auto restart after overload or short-circuit

The overload protection is implemented in an automatic way using the integrated up-down
counter. Every cycle, it is incremented or decremented depending on whether the current
logic detects the limit condition or not. The limit condition is the peak drain current, IDLIM.
After the reset of the counter, if the peak drain current is continuously equal to the level IDlim,
the counter will be incremented till the fixed time, tOVL, after that the power MOSFET switch
ON is disabled. It is activated again, through the soft-start, after the tRESTART time.
In the case of overload or a short-circuit event, the power MOSFET switching is stopped
after a time that depends from the counter and that can be as maximum equal to tOVL. The
protection occurs in the same way until the overload condition is removed.
This protection ensures restart attempts of the converter with low repetition rate, so that it
works safely with extremely low power throughput and avoiding the IC overheating in case
of repeated overload events.
If the overload is removed before the protection tripping, the counter is decremented cycle-
by-cycle down to zero and the IC is not stopped.

DS12978 Rev 1 17/28

28
General description VIPER26K

Figure 24. Timing diagram: OLP sequence

4.11 Open loop failure protection

In case the power supply is built in flyback topology and the VIPer26K is supplied by an
auxiliary winding, the converter is protected against feedback loop failure or accidental
disconnections of the winding.
If RH is opened or RL is shorted, the VIPer26K works at its drain current limitation. The
output voltage, VOUT, increases and also the auxiliary voltage, VAUX, which is coupled with
the output through the secondary-to-auxiliary turns ratio.
As the auxiliary voltage increases up to the internal VDD active clamp, VDDclamp and the
clamp current injected on the VDD pin exceeds the latch threshold, IDDol, a fault signal is
internally generated.
In order to distinguish an actual malfunction from a bad auxiliary winding design, both the
above conditions (drain current equal to the drain current limitation and current higher than
IDDol through VDD clamp) have to be verified to reveal the fault.
If RL is opened or RH is shorted, the output voltage, VOUT, is clamped to the reference
voltage VREF_FB (in case of non-isolated flyback) or to the external TL voltage reference (in
case of isolated flyback).

4.12 Thermal shutdown

When the controller temperature exceeds the shutdown threshold, TSD, the device is shut
down to prevent any dangerous overheating for the system and the VDD pin is continuously
recycled between VDDon and VDDoff to keep the controller alive.
Once the tRESTART time is elapsed, when temperature falls THYST below the OTP threshold,
the IC starts once it has reached again the VDDon.
The OTP timing diagram is shown in Figure 25.

18/28 DS12978 Rev 1

VIPer26K General description

Figure 25. Timing diagram: OLP sequence

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DS12978 Rev 1 19/28

28
Application information VIPER26K

5 Application information

Figure 26. Typical isolated flyback configuration with secondary regulation

Figure 27. Typical isolated flyback configuration with primary regulation

20/28 DS12978 Rev 1

VIPer26K Application information

Figure 28. Typical non isolated flyback configuration

Figure 29. Ultra wide range Buck configuration

DS12978 Rev 1 21/28

28
Application information VIPER26K

5.1 Layout guidelines and design recommendations

A proper printed circuit board layout ensures the correct operation of any switch-mode
converter and this is also true for the VIPer. The main reasons to have a proper PCB layout
are:
 Provides clean signals to the IC, ensuring good immunity against external and switching
noises.
 Reduces the electromagnetic interferences, both radiated and conducted, to pass the
EMC tests more easily.
If the VIPer is used to design an SMPS, the following basic rules should be considered:
 Separate signal from power tracks. Generally, traces carrying signal currents should
run far from others carrying pulsed currents or with fast swinging voltages. Signal ground
traces should be connected to the IC signal ground, GND, using a single “star point”,
placed close to the IC. Power ground traces should be connected to the IC power ground,
GND. The compensation network should be connected to the COMP, maintaining the
trace to GND as short as possible. In the case of two-layer PCB, it is good practice to route
signal traces on one PCB side and power traces on the other side.
 Filter sensitive pins. Some crucial points of the circuit need or may need filtering. A small
high-frequency bypass capacitor to GND might be useful to get a clean bias voltage for
the signal part of the IC and protect the IC itself during EFT/ESD tests. A low ESL ceramic
capacitor (a few hundreds pF up to 0.1 μF) should be connected across VCC and GND,
placed as close as possible to the IC. With flyback topologies, when the auxiliary winding
is used, it is suggested to connect the VCC capacitor on the auxiliary return and then to
the main GND using a single track.
 Keep power loops as confined as possible. The area circumscribed by current loops
where high pulsed current flow should be minimized to reduce its parasitic self-inductance
and the radiated electromagnetic field. As a consequence, the electromagnetic
interferences produced by the power supply during the switching are highly reduced. In a
flyback converter the most critical loops are: the one including the input bulk capacitor, the
power switch, the power transformer, the one including the snubber, the one including the
secondary winding, the output rectifier and the output capacitor. In a buck converter the
most critical loop is the one including the input bulk capacitor, the power switch, the power
inductor, the output capacitor and the freewheeling diode.
 Reduce line lengths. Any wire acts as an antenna. With the very short rise times
exhibited by EFT pulses, any antenna can receive high voltage spikes. By reducing line
lengths, the level of received radiated energy is reduced, and the resulting spikes from
electrostatic discharges are lower. This also keeps both resistive and inductive effects to
a minimum. In particular, all traces carrying high currents, especially if pulsed (tracks of
the power loops) should be as short and wide as possible.
 Optimize track routing. As levels of pickup from static discharges are likely greater near
the edges of the board, it is wise to keep any sensitive lines away from these areas. Input
and output lines often need to reach the PCB edge at some stage, but they can be routed
away from the edge as soon as possible where applicable. Since vias are to be
considered inductive elements, it is recommended to minimize their number in the signal
path and avoid them in the power path.
 Improve thermal dissipation. An adequate copper area has to be provided under the
DRAIN pins as heatsink, while it is not recommended to place large copper areas on the
GND.

22/28 DS12978 Rev 1

VIPer26K Application information

Figure 30. Recommended routing for flyback converter

Figure 31. Recommended routing for Buck converter

DS12978 Rev 1 23/28

28
Package information VIPER26K

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: [Link].
ECOPACK® is an ST trademark.

6.1 SO16N package information

Figure 32. SO16N package outline

24/28 DS12978 Rev 1

VIPer26K Package information

Table 9. SO16N mechanical data

mm
Dim.
Min. Typ. Max.

A 1.75
A1 0.1 0.25
A2 1.25
b .31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.8 6 6.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 1.1

DS12978 Rev 1 25/28

28
Order code VIPER26K

7 Order code

Table 10. Order codes

Order Code Package IDLIM Packaging
VIPER265KDTR 500 mA
SO16N Tape & Reel
VIPER267KDTR 700 mA

26/28 DS12978 Rev 1

VIPer26K Revision history

8 Revision history

Table 11. Document history

Date Revision Changes

23-Apr-2019 1 Initial release.

DS12978 Rev 1 27/28

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 VIPER26K

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