DIGITAL IC

APPLICATIONS
LABORATORY MANUAL (R16)

Prepared by
Mr. Sundara K ChakravarthyM, Assistant Professor

Department of Electronics & Communication Engineering

VIGNAN’S NIRULA INSTITUTE OF
TECHNOLOGY & SCIENCE FOR WOMEN
Affiliated to JNT University, Kakinada
An ISO 9001:2008 Certified Institution
Vadlamudi, Guntur (Dist.,), A.P. - 522213

DIGITAL IC APPLICATIONS
III YEAR – I SEMESETER

The students are required to design and draw the internal structure of the following Digital
Integrated Circuits and to develop VHDL source code, perform simulation using relevant simulator and
analyze the obtained simulation results using necessary synthesizer. Further, it is required to verify the
logic with necessary hardware.

DICA Lab Manual -1- Department of ECE, VNITSW

 LIST OF EXPERIMENTS

1. Realization of Logic Gates

2. Design of Full Adder using 3 modeling systems
3. 3 to 8 Decoder- 74138
4. 8 to 3 Encoder (with and without priority)
5. 8*1 Multiplexer-74151 and 2*1 De-multiplexer-74155
6. 4-Bit Comparator-7485.
7. D Flip-Flop- 7474
8. Decade Counter- 7490
9. Shift Register-7495
10. 8 bit serial in –parallel out and Parallel in –serial out
11. First in &first out (FIFO)
12. MAC (Multiplier & Accumulator)
13. ALU

DICA Lab Manual -2- Department of ECE, VNITSW

 Useful Integrated Circuit (IC)’s List
[Link]. IC Number Description of IC

1 4072 Dual 4-input OR Gate

2 7400 Quad 2-input NAND GATE

3 7402 Quad 2-input NOR Gate

4 7404 Hex Inverts

5 7408 Quad 2-input AND Gate

6 7411 Dual 3-input AND Gate

7 7421 Dual 4-input AND Gate

8 7432 Quad 2-input OR Gate

9 7473 Dual Master-Slave J-K Flip-Flop

10 7474 Dual D Flip-Flop

11 7476 Dual J-K Flip-Flop with Preset and Clear

12 7485 4 bit Comparator

13 7486 Quad 2-input EX-OR Gate

14 7490 Decade Counter

15 7493 4-bit Binary Counter

16 7495 4-bit Shift Register

17 74151 8X1 Multiplexer

18 74155 1X4 Demultiplexer

19 74189 SRAM

20 74173 Quad D Flip-Flops

21 74174 Hex D Flip-Flops

22 74273 Octal D Flip-Flops

DICA Lab Manual -3- Department of ECE, VNITSW

 Introduction of VIVADOIDE Quick StartTutorial
1. Open VIVADO 2014.2 Software from the help tool
2. Check for licence activation status
3. Select create new project in Quick Start
4. Check on next and define project name with project location. Make sure that create project subdirectory is
selected.
5. Select RTL Project and click next and Check that target and simulator languages are in VHDL
6. Select Create File and Give filename. Select file type as VHDL and CLICK OK
7. Mostly the architecture name user defined and click next
8. Select type of board from the list
9. Select 'ARTIX7 FPGA' in display name
10. Define inputs &outputs both and click finish
11. Select the file from source pane and write program code
12. Save the file
13. For creating the test bench from the flow navigator (or) create simulation sources, and add sources
14. Give test bench file name as filename_tb and click next
15. Click CANCEL and then YES
16. Write Simulation code and save it
17. Go to the sources and check for any errors
18. Select run simulation and then behavioral simulation
19. Analyze the waveforms

DICA Lab Manual -4- Department of ECE, VNITSW

 Experiment No: 01 Date:
STUDY OF LOGIC GATES

AIM: To simulate and verify the truth tables of OR, AND, NOT, NAND, NOR and X-OR gates.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

THEORY:
A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and one output. At any given moment, every terminal is in one of the two
binary conditions low (0) or high (1), represented by different voltage levels. The logic state of a
terminal can, and generally does, change often, as the circuit processes data. In most logic gates,
the low state is approximately zero volts (0 V), while the high state is approximately five volts
positive (+5V).
AND:
The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in the
same way as the logical "and"operator.
OR:
The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive
"or." The output is "true" if either or both of the inputs are "true." If both inputs are "false," then
the output is "false."
NOR:
The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both inputs
are "false." Otherwise, the output is "false."
PROCEDURE:
 Click on the Xilinxicon.
 Go to file and click on newproject.
 Enter your project name and project setting select automotive Spartan 3E in family.
 Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your
file name. But do not give keywords as filename.
 Now define module will be opened. Fill input, output details inport.
 In design window your file will appear, make sure it isdetected.
 Write architectural part and saveit.
 Go to process window, click on synthesizer and checksyntax.
 If any syntax errors occur they will appear on console window whilecompiling.
 Go to simulation and select yourfile.
 In process window click ISM simulator, now click on behavioral check syntax, simulate behavioralmodel.
 Select your input & click on force constant. Enter value in ‘force clock’ tovalue.
 By repeating above step for all input’s click on‘RUN’.
To view output for all combinations of inputs click on zoomview.

ALGORITHM FOR ALL GATES:

Step 1: Use the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Step 2: Declare the Entities

DICA Lab Manual -5- Department of ECE, VNITSW

Define the Ports with 2 Inputs and 8 output for all gate’s operation
Step 3: Declare the architecture for each gate
If i/p=1 then p=0 else o/p=1 [for NOTgate]
If two i/p’s are 1 then o/p=1; else o/p=0 [for ANDgate]
If one i/p is 1 then o/p=1; else o/p=0 [for ORgate]
If one i/p is 0 then o/p=1; else o/p=0 [for NANDgate]
If two i/p’s are 0 then o/p=1; else o/p=0 [for NORgate]
If two i/p’s are different then o/p=1; else o/p=0 [for XORgate]
If two i/p’s are same then o/p=1; else o/p=0 [for XNORgate]
Step 4: End
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity exp1prb is
Port ( a,b : in STD_LOGIC;
y1,y2,y3,y4,y5,y6,y7,y8 : out STD_LOGIC);
end exp1prb;
architecture exp1prb of exp1prb is
begin
y1<=a and b;
y2<=a or b;
y3<=a nand b;
y4<=a nor b;
y5<=a xor b;
y6<=a xnor b;
y7<=not a;
y8<=not b;
end exp1prb;
TESTBENCH:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity exp1prb_tb is
end;
architecture exp1prb_tb of exp1prb_tb is
component exp1prb is
port(a,b:in std_logic; y1,y2,y3,y4,y5,y6,y7,y8:out std_logic);
end component;
signal a,b:std_logic;
signal y1,y2,y3,y4,y5,y6,y7,y8:std_logic;
begin
uut:exp1prb port map(a=>a,b=>b,y1=>y1,y2=>y2,y3=>y3,y4=>y4,y5=>y5,y6=>y6,y7=>y7,y8=>y8);
process
begin
a<='0'; b<='0'; wait for 10ns;
a<='0'; b<='1'; wait for 10ns;
a<='1'; b<='0'; wait for 10ns;
a<='1'; b<='1'; wait for 10ns;
wait;
end process;
end;

DICA Lab Manual -6- Department of ECE, VNITSW

 SIMULATION OUTPUTS:

RESULT: NOT gate is simulated and verified.

RESULT: XOR gate is simulated and verified.

VIVA QUESTIONS:
1. Implement the following function using VHDL coding. (Try to minimize if youcan). F(A,B,C,D)=(A′
+B+C) . (A+B′+D′). (B+C′+D′) .(A+B+C+D)
2. What will be the no. of rows in the truth table of Nvariables?
3. What are the advantages ofVHDL?
4. Design Ex-OR gate using behavioralmodel?
5. Implement the following function using VHDL codef=AB+CD.
6. What are the differences between half adder and fulladder?
7. What are the advantages of minimizing the logicalexpressions?
8. What does a combinational circuitmean?
9. Implement the half adder using VHDLcode?
10. Implement the full adder using two half adders and write VHDL program instructural model?

DICA Lab Manual -7- Department of ECE, VNITSW

Experiment No: 02 Date:

1. Design of Full Adder using 3 modeling systems

AIM: To write VHDL code for a full adder in 3 modeling styles and simulate using Xilinx ISE simulator
and verify truth tables.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

THEORY:
The VHDL Code for full-adder circuit adds three one-bit binary numbers (A B Cin) and outputs
two one-bit binary numbers, a sum (S) and a carry (Cout). Truth Table describes the functionality
of full adder. sum(S) output is High when odd number of inputs are High. Cout is High, when two
or more inputs are High. VHDL Code for full adder can also be constructed with 2 half adder Port
mapping in to full adder.

Fig: Block diagram and Logic circuit of Full Adder

VHDL Code for Full adder in Behavioral style
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity exp2prb is
Port ( a,b,c : in STD_LOGIC; sum,carry : out STD_LOGIC);
end exp2prb;
architecture exp2prb of exp2prb is
begin
process(a,b,c)
begin
if a='0' and b='0' and c='0' then sum<='0';carry<='0';
elsif a='0'and b='0'and c='1' then sum<='1';carry<='0';
elsif a='0' and b='1' and c='0' then sum<='1';carry<='0';
elsif a='0' and b='1' and c='1' then sum<='0';carry<='1';
elsif a='1' and b='0' and c='0' then sum<='1';carry<='0';
elsif a='1' and b='0' and c='1' then sum<='0';carry<='1';
elsif a='1' and b='1' and c='0' then sum<='0';carry<='1';
else sum<='1';carry<='1';
end if;
end process;
end exp2prb;

VHDL Code for Full adder in Structural style

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

DICA Lab Manual -8- Department of ECE, VNITSW

use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
Port ( a,b,cin : in STD_LOGIC;
sum,cout : out STD_LOGIC);
end full_adder;
architecture fa_str of full_adder is
component xor2
port(d1,d2:in std_logic;
dz:out std_logic);
end component;
component or2
port(n1,n2:std_logic;
z:out std_logic);
end component;
component and2
port(a1,a2:in std_logic;
u:out std_logic);
end component;
signal s1,s2,s3,s4,s5:std_logic;
begin
x1:xor2 port map(a,b,s1);
x2:xor2 port map(s1,cin,sum);
r1:and2 port map(a,b,s2);
r2:and2 port map(b,cin,s3);
r3:and2 port map(a,cin,s4);
o1:or2 port map(s2,s3,s5);
o2:or2 port map(s4,s5,cout);
end fa_str;

VHDL Code for Full adder in Dataflow style

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity exp2pra is
Port ( a,b,c : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end exp2pra;
architecture exp2pra of exp2pra is
begin
sum<=a xor b xor c;
carry<=(a and b) or (b and c) or (c and a);
end exp2pra;

TESTBENCH Code for Full adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity exp2pra_tb is
end;
architecture exp2pra_tb of exp2pra_tb is
component exp2pra is
port(a,b,c:in std_logic; sum,carry:out std_logic);
end component;
signal a,b,c:std_logic;
signal sum,carry:std_logic;
begin
uut:exp2pra port map(a=>a,b=>b,c=>c,sum=>sum, carry=>carry);
process
begin
a<='0'; b<='0'; c<='0'; wait for 10ns;
a<='0'; b<='0'; c<='1'; wait for 10ns;
a<='0'; b<='1'; c<='0'; wait for 10ns;
a<='0'; b<='1'; c<='1'; wait for 10ns;

DICA Lab Manual -9- Department of ECE, VNITSW

 a<='1'; b<='0'; c<='0'; wait for 10ns;
a<='1'; b<='0'; c<='1'; wait for 10ns;
a<='1'; b<='1'; c<='0'; wait for 10ns;
a<='1'; b<='1'; c<='1'; wait for 10ns;
wait;
end process;
end;

SIMULATION OUTPUTS:

RESULT: Full adder is simulated and verified.

DICA Lab Manual -10- Department of ECE, VNITSW

 Experiment No: 03 Date:
3. 3 to 8 DECODER

AIM: Simulation and verification of 3-8 DECODERS using IC-74183.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator
PIN DIAGRAM:

LOGIC DIAGRAM:

DICA Lab Manual -11- Department of ECE, VNITSW

INTERNAL ARCHITECTURE OF 74138

OBSERVATIONS:

THEORY:
Decoder is the combinational circuit which contains ‘n’ input lines to 2 n output lines. The decoder is
used for converting the binary code into the octal code. The IC74138 is the 3*8 decoder which contains
three inputs and eight outputs and also three enables out of them two are active low and one is active high.
Decoders are used in the circuit where required to get more outputs than that of the inputs which also used
in the chip designing process for reducing the IC chip area.

DICA Lab Manual -12- Department of ECE, VNITSW

PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp3pr is
Port ( g1,ng2a,ng2b : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end exp3pr;
architecture exp3pr of exp3pr is
begin
process(g1,ng2a,ng2b,a)
begin
if g1='0' or ng2a='1' or ng2b='1'
then y<="11111111";
else
if a="000" then y<="11111110";
elsif a="001" then y<="11111101";
elsif a="010" then y<="11111011";
elsif a="011" then y<="11110111";
elsif a="100" then y<="11101111";
elsif a="101" then y<="11011111";
elsif a="110" then y<="10111111";
else y<="01111111";
end if;
end if;
end process;
end exp3pr;
TESTBENCH PROGRAM FOR DECODER:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity exp3pr_tb is
end;
architecture exp3pr_tb of exp3pr_tb is
component exp3pr is
port(g1,ng2a,ng2b:in std_logic;
a:in std_logic_vector(2 downto 0);
y:out std_logic_vector(7 downto 0));
end component;
signal g1,ng2a,ng2b:std_logic;
signal a:std_logic_vector(2 downto 0);
signal y:std_logic_vector(7 downto 0);
begin
uut:exp3pr port map(g1=>g1,ng2a=>ng2a,ng2b=>ng2b,a=>a,y=>y);
process
begin
g1<='0';ng2a<='0';ng2b<='0';wait for 10ns;
g1<='1';ng2a<='1';ng2b<='0';wait for 10ns;
g1<='1';ng2a<='0';ng2b<='1';wait for 10ns;
g1<='1';ng2a<='0';ng2b<='0';a<="000";wait for 10ns;
a<="001";wait for 10ns;
a<="010";wait for 10ns;
a<="011";wait for 10ns;
a<="100";wait for 10ns;
a<="101";wait for 10ns;
a<="110";wait for 10ns;
a<="111";wait for 10ns;
wait;
end process;

DICA Lab Manual -13- Department of ECE, VNITSW

end;

SIMULATION OUTPUTS :

VIVA QUESTIONS:
1. What is decoder?
2. What is a encoder?
3. For a 2- I/P decoder how many O/P’s are produced
4. A decoder with ‘n’ input produces max. of __ [Link].
5. The general representation of an encoder is
6. Draw the 2 to 4 line decoder with only nor gates.
7. Difference b/w de multiplexer and decoder

RESULT: 3-8 DECODERS using IC-74183is simulated and verified.

DICA Lab Manual -14- Department of ECE, VNITSW

 Experiment No: 04 Date:

4. 8 to 3 ENCODER WITH AND WITHOUT PRIORITY

AIM: To write VHDL code for 8 to 3 encoder with and without priority.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

BLOCK DIAGRAM:

Truth Table:

Theory:
Unlike a multiplexer that selects one individual data input line and then sends that data to a single output
line or switch, Digital Encoder more commonly called a Binary Encoder takes ALL its data inputs one at
a time and then converts them into a single encoded output. So we can say that a binary encoder, is a multi-
input combinational logic circuit that converts the logic level “1” data at its inputs into an equivalent binary
code at its output.
Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of
data input lines. An “n-bit” binary encoder has 2 n input lines and n-bit output lines with common types that
include 4-to-2, 8-to-3 and 16-to-4 line configurations.

DICA Lab Manual -15- Department of ECE, VNITSW

The output lines of a digital encoder generate the binary equivalent of the input line whose value is equal to
“1” and are available to encode either a decimal or hexadecimal input pattern to typically a binary or
“B.C.D” (binary coded decimal) output code.
The Priority Encoder solves the problems mentioned above by allocating a priority level to each input.
The priority encoders output corresponds to the currently active input which has the highest priority. So
when an input with a higher priority is present, all other inputs with a lower priority will be ignored.
Priority encoders are available in standard IC form and the TTL 74LS148 is an 8-to-3 bit priority encoder
which has eight active LOW (logic “0”) inputs and provides a 3-bit code of the highest ranked input at its
output.
Priority encoders output the highest order input first for example, if input lines “D2“, “D3” and “D5” are
applied simultaneously the output code would be for input “D5” (“101”) as this has the highest order out of
the 3 inputs. Once input “D5” had been removed the next highest output code would be for input “D3”
(“011”), and so on.
PROCEDURE:
 Click on the Xilinxicon.
 Go to file and click on newproject.
 Enter your project name and project setting select automotive Spartan 3E in family.
 Go to project, click on new source. A new source wizard will open. Select VHDL module and enter
your file name. But do not give keywords as filename.
 Now define module will be opened. Fill input, output details inport.
 In design window your file will appear, make sure it isdetected.
 Write architectural part and saveit.
 Go to process window, click on synthesizer and checksyntax.
 If any syntax errors occur they will appear on console window whilecompiling.
 Go to simulation and select yourfile.
 In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioralmodel.
 Select your input & click on force constant. Enter value in ‘force clock’ tovalue.
 By repeating above step for all input’s click on‘RUN’.

VHDL Code:( Encoder with priority)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp5pra is
Port ( e : in STD_LOGIC;
y : in STD_LOGIC_VECTOR (7 downto 0);
a : out STD_LOGIC_VECTOR (2 downto 0);
Gs,Eo : out STD_LOGIC);
end exp5pra;
architecture exp5pra of exp5pra is
begin
process(e,y)
begin
if e='1' then a<="111";Gs<='1';EO<='1';
elsif y="xxxxxxx0" then a<="000";Gs<='0';EO<='1';
elsif y="xxxxxx01"then a<="001";Gs<='0';EO<='1';
elsif y="xxxxx011" then a<="010";Gs<='0';Eo<='1';
elsif y="xxxx0111" then a<="011";Gs<='0';EO<='1';
elsif y="xxx01111" then a<="100";Gs<='0';EO<='1';
elsif y="xx011111" then a<="101";Gs<='0';EO<='1';
elsif y="x0111111" then a<="110";Gs<='0';EO<='1';
elsif y="01111111" then a<="111";Gs<='0';EO<='1';
elsif y="11111111" then a<="111";Gs<='1';EO<='0';

DICA Lab Manual -16- Department of ECE, VNITSW

end if;
end process;
end exp5pra;

TEST BENCH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp5pra_tb is
end exp5pra_tb;
architecture exp5pra_tb of exp5pra_tb is
component exp5pra is
port(e:in std_logic;
y:in std_logic_vector(7 downto 0);
a:out std_logic_vector(2 downto 0);
Gs,EO:OUT STD_LOGIC);
end component;
signal e:std_logic;
signal y:std_logic_vector(7 downto 0);
signal a:std_logic_vector(2 downto 0);
signal Gs,EO:std_logic;
begin
uut:exp5pra port map(e=>e,y=>y,a=>a,Gs=>Gs,Eo=>EO);
process
begin
e<='1';y<="xxxxxxx0";wait for 10ns;
e<='0';y<="xxxxxxx0";wait for 10ns;
y<="xxxxxx01";wait for 10ns;
y<="xxxxx011";wait for 10ns;
y<="xxxx0111";wait for 10ns;
y<="xxx01111";wait for 10ns;
y<="xx011111";wait for 10ns;
y<="x0111111";wait for 10ns;
y<="01111111";wait for 10ns;
y<="11111111";wait for 10ns;
wait;
end process;
end exp5pra_tb;

VHDL Code:( Encoder with priority)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp5prb is
Port ( e : in STD_LOGIC;
y : in STD_LOGIC_VECTOR (7 downto 0);
a : out STD_LOGIC_VECTOR (2 downto 0);
Gs,Eo : out STD_LOGIC);
end exp5prb;
architecture exp5prb of exp5prb is
begin
process(e,y)
begin
if e='1' then a<="111";Gs<='1';EO<='1';
elsif y="11111110" then a<="000";gs<='0';e0<='1';
elsif y="11111101" then a<="001";gs<='0';e0<='1';
elsif y="11111011" then a<="010";gs<='0';e0<='1';
elsif y="11110111" then a<="011";gs<='0';e0<='1';

DICA Lab Manual -17- Department of ECE, VNITSW

elsif y="11101111" then a<="100";gs<='0';e0<='1';
elsif y="11011111" then a<="101";gs<='0';e0<='1';
elsif y="10111111" then a<="110";gs<='0';e0<='1';
elsif y="01111111" then a<="111";gs<='0';e0<='1';
else a<="111";Gs<='1';EO<='0';
end if;
end process;
end exp5prb;

TEST BENCH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp5prb_tb is
end exp5prb_tb;
architecture exp5prb_tb of exp5prb_tb is
component exp5prb is
port(e:in std_logic;
y:in std_logic_vector(7 downto 0);
a:out std_logic_vector(2 downto 0);
Gs,EO:OUT STD_LOGIC);
end component;
signal e:std_logic;
signal y:std_logic_vector(7 downto 0);
signal a:std_logic_vector(2 downto 0);
signal Gs,EO:std_logic;
begin
uut:exp5prb port map(e=>e,y=>y,a=>a,Gs=>Gs,Eo=>EO);
process
begin
e<='1';y<="11111110";wait for 10ns;
e<='0';y<="11111110";wait for 10ns;
y<="11111101";wait for 10ns;
y<="11111011";wait for 10ns;
y<="11110111";wait for 10ns;
y<="11101111";wait for 10ns;
y<="11011111";wait for 10ns;
y<="10111111";wait for 10ns;
y<="01111111";wait for 10ns;
y<="11111111";wait for 10ns;
wait;
end process;
end exp5prb_tb;

Simulation Results:

RESULT: 8 to 3 Encoder is simulated and verified.

DICA Lab Manual -18- Department of ECE, VNITSW

DICA Lab Manual -19- Department of ECE, VNITSW
 Experiment No: 05 Date:

5. 8 x 1MULTIPLEXER

AIM: Simulation and verification of 8*1 MULTIPLEXER using IC-74150.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

PIN DIAGRAM: LOGIC DIAGRAM:

TRUTH TABLE:

DICA Lab Manual -20- Department of ECE, VNITSW

THEORY:

A multiplexer is a digital switch- it connects data from one of n sources to its output. An 8*1 is
multiplexer consists of 3 input lines as select lines and 8 input lines and 1 output line. A multiplexer is a
unidirectional device which follows the data from input lines to output lines. Multiplexers are obviously
useful device in any application in which data must be multiple source to destination. A common
application in computers is the mux between the processors registers and its ALU.

VHDL CODE FOR MULTIPLEXER (8:1) :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp4pr is
Port ( ne : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (2 downto 0);
i0,i1,i2,i3,i4,i5,i6,i7 : in STD_LOGIC;
y,ny : out STD_LOGIC);
end exp4pr;
architecture exp4pr of exp4pr is
signal y1:std_logic;
begin
process(ne,s,i0,i1,i2,i3,i4,i5,i6,i7)
begin
if ne='1' then y1<='0';
else
case s is
when "000"=> y1<=i0;
when "001"=> y1<=i1;
when "010"=> y1<=i2;
when "011"=> y1<=i3;
when "100"=> y1<=i4;
when "101"=> y1<=i5;
when "110"=> y1<=i6;
when others =>y1<=i7;
end case;
end if;
end process;
y<=y1;
ny<=not y1;
end exp4pr;
TEST BENCH FOR MULTIPLEXER:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity exp4pr_tb is
end;
architecture exp4pr_tb of exp4pr_tb is
component exp4pr is
port(ne:in std_logic;
s:in std_logic_vector(2 downto 0);
i0,i1,i2,i3,i4,i5,i6,i7:in std_logic;
y,ny:out std_logic);
end component;
signal ne:std_logic;
signal s:std_logic_vector(2 downto 0);
signal i0,i1,i2,i3,i4,i5,i6,i7:std_logic;
signal y,ny:std_logic;
begin

DICA Lab Manual -21- Department of ECE, VNITSW

uut:exp4pr port map(ne=>ne,s=>s,i0=>i0,i1=>i1,i2=>i2,i3=>i3,i4=>i4,i5=>i5,i6=>i6,i7=>i7,y=>y,ny=>ny);
process
begin
ne<='1';wait for 10ns;
ne<='0';wait for 10ns;
s<="000";i0<='1';i1<='0';i2<='0';i3<='0';i4<='0';i5<='0';i6<='0';i7<='0';wait for 10ns;
s<="001";i0<='0';i1<='1';i2<='0';i3<='0';i4<='0';i5<='0';i6<='0';i7<='0';wait for 10ns;
s<="010";i0<='0';i1<='0';i2<='1';i3<='0';i4<='0';i5<='0';i6<='0';i7<='0';wait for 10ns;
s<="011";i0<='0';i1<='0';i2<='0';i3<='1';i4<='0';i5<='0';i6<='0';i7<='0';wait for 10ns;
s<="100";i0<='0';i1<='0';i2<='0';i3<='0';i4<='1';i5<='0';i6<='0';i7<='0';wait for 10ns;
s<="101";i0<='0';i1<='0';i2<='0';i3<='0';i4<='0';i5<='1';i6<='0';i7<='0';wait for 10ns;
s<="110";i0<='0';i1<='0';i2<='0';i3<='0';i4<='0';i5<='0';i6<='1';i7<='0';wait for 10ns;
s<="111";i0<='0';i1<='0';i2<='0';i3<='0';i4<='0';i5<='0';i6<='0';i7<='1';wait for 10ns;
wait;
end process;
end;

VHDL CODE FOR DEMULTIPLEXER (1:4):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity exp4prb is
Port (ei:in STD_LOGIC;
s:in STD_LOGIC_VECTOR(1 downto 0);
y:out STD_LOGIC_VECTOR(3 downto 0) );
end exp4prb;

architecture exp4prb of exp4prb is

signal y1: std_logic_vector(3 downto 0);
begin
process(ei,s)
begin
if ei='1' then y1<="1111";
else
case s is
when "00"=>y1<="1110";
when "01"=>y1<="1101";
when "10"=>y1<="1011";
when "11"=>y1<="0111";
when others=>y1<="0000";
end case;
end if;
end process;
y<=y1;
end exp4prb;
TEST BENCH FOR DEMULTIPLEXER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity exp4prb_tb is
end exp4prb_tb;
architecture exp4prb_tb of exp4prb_tb is
component exp4prb is
port(ei:in std_logic;
s:in std_logic_vector(1 downto 0);
y:out std_logic_vector(3 downto 0));
end component;
signal ei:std_logic;
signal s:std_logic_vector(1 downto 0);
signal y:std_logic_vector(3 downto 0);
begin
uut:exp4prb port map(ei=>ei,s=>s,y=>y);

DICA Lab Manual -22- Department of ECE, VNITSW

process
begin
ei<='1';wait for 10ns;
ei<='0';wait for 10ns;
s<="00";wait for 10ns;
s<="01";wait for 10ns;
s<="10";wait for 10ns;
s<="11";wait for 10ns;
wait;
end process;
end exp4prb_tb;

SIMULATION OUTPUTS for MUX:

SIMULATION OUTPUTS for DEMUX:

VIVA QUESTIONS:

1. Mux is an implementation of –
2. Multiplexer is represented by –
3. De multiplexer is represented by –

RESULT: 8*1 Multiplexerand 2*4 demultiplexeris simulated and verified.

DICA Lab Manual -23- Department of ECE, VNITSW

 Experiment No: 06 Date:
8. BIT COMPARATOR

AIM: Simulation and verification of 4 BIT COMPARATOR using IC-7485.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

PIN DIAGRAM:

FUNCTION TABLE:

DICA Lab Manual -24- Department of ECE, VNITSW

LOGIC DIAGRAM:

THEORY:

Comparing two binary words for equality is a commonly used operation in computer systems and
device interfaces. A circuit that compares two binary words and indicates whether they are equal is called a
comparator. Some comparators interpret their input words as signed or unsigned numbers and also
indicate an arithmetic relationship (greater or less than) between the words. These devices are often called
magnitude comparators. A 1-bit Comparator is designed using Ex-OR and Ex-NOR gates. The outputs of
4 XOR gates are ORed to create a 4-bit comparator. The IC 7485 is 4-bit magnitude comparator. With
respect to the 8 inputs 3 inputs are cascaded inputs. After the 8 input operations are performed further the
outputs are based on the cascaded inputs.

PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp6pr is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
iagb,ialb,iaeb : in STD_LOGIC;
agb,alb,aeb : out STD_LOGIC);
end exp6pr;
architecture exp6pr of exp6pr is
begin
process(a,b,iagb,ialb,iaeb)
begin
if a>b then agb<='1';alb<='0';aeb<='0';

DICA Lab Manual -25- Department of ECE, VNITSW

elsif a<b then agb<='0'; alb<='1';aeb<='0';
else
if iagb='1' and ialb='0' and iaeb='0' then agb<='1'; alb<='0';aeb<='0';
elsif iagb='0' and ialb='1' and iaeb='0' then agb<='0'; alb<='1';aeb<='0';
elsif iagb='0' and ialb='0' and iaeb='1' then agb<='0'; alb<='0';aeb<='1';
else
agb<='1';alb<='1';aeb<='1';
end if;
end if;
end process;
end exp6pr;
TESTBENCH:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp6pr_tb is
end exp6pr_tb;
architecture exp6pr_tb of exp6pr_tb is
component exp6pr is
port(a,b:in std_logic_vector(3 downto 0);
iagb,ialb,iaeb:in std_logic;
agb,alb,aeb:out std_logic);
end component;
signal a,b:std_logic_vector(3 downto 0);
signal iagb,ialb,iaeb:std_logic;
signal agb,alb,aeb:std_logic;
begin
uut:exp6pr port map(a=>a,b=>b,iagb=>iagb,ialb=>ialb,iaeb=>iaeb,agb=>agb,alb=>alb,aeb=>aeb);
process
begin
a<="1111";b<="0111";wait for 10ns;
a<="0001";b<="1000";wait for 10ns;
a<="1111";b<="1111";wait for 10ns;
iagb<='1';ialb<='0';iaeb<='0';wait for 10ns;
iagb<='0';ialb<='1';iaeb<='0';wait for 10ns;
iagb<='0';ialb<='0';iaeb<='1';wait for 10ns;
iagb<='1';ialb<='1';iaeb<='1';wait for 10ns;
wait;
end process;
end exp6pr_tb;

SIMULATION OUTPUTS :

VIVA QUESTIONS:
1. What is Magnitude Comparator?
2. To form a 12 – bit comparator how many 4-bit comparators are connected in cascaded form.
3. The IC 7485 is a package and is a ____ comparator.
4. How many cascaded input are there for a 4-bit comparator

RESULT: 4 BIT COMPARATOR using IC-7485is simulated and verified.

DICA Lab Manual -26- Department of ECE, VNITSW

 Experiment No: 07 Date:

7. D-FLIP-FLOP

AIM: Simulation and verification of D-FLIP FLOP(IC-74LS74A) using Xilinx ISE Simulator

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

PIN DIAGRAM:

LOGIC DIAGRAM:

DICA Lab Manual -27- Department of ECE, VNITSW

FUNCTIONAL TABLE:

THEORY:
TheD flip-flop is also known as the Data flip-flop or the Delay flip-flop. It is used to either store the
data or introduce a delay. If a ‘0’ is given at D in ,then S is ‘0’ and R will be ‘1’. This resets the flip-flop. If a
‘1’ is given at Din, then S is ‘1’ and R ‘0’. This sets the flip-flop. Thus we find that D out is always equal to Din.
Hence this flip-flop can be used to store a binary digit. So it is known as the Data flip-flop. The D flip-flop
can also be clocked similar to the RS flip-flop. In the clocked D flip-flop Dout will be made equal to Din
only when the clock arrives. Thus the data bit is sent to the output after a delay. Therefore, the D flip-flop
is also known as the Delay flip-flop.

PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp8pr is
Port ( pre,clk,clr,d : in STD_LOGIC;
q,qn : out STD_LOGIC);
end exp8pr;
architecture exp8pr of exp8pr is
signal q1:std_logic:='0';
begin
process(pre,clk,clr,d)
begin
if clr='1' and pre='0' then q1<='1';
elsif clr='0' and pre='1' then q1<='0';
elsif clr='0' and pre='0' then q1<='U';
elsif clr='0' and pre='0' then q1<='U';
else
if clk'event and clk='1' then q1<=d;
else q1<=q1;
end if;
end if;
end process;
q<=q1;qn<=not q1;
end exp8pr;

TEST BENCH:
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp8pr_tb is
end exp8pr_tb;
architecture exp8pr_tb of exp8pr_tb is
component exp8pr is
port(pre,clk,clr,d:in std_logic;
q,qn:out std_logic);

DICA Lab Manual -28- Department of ECE, VNITSW

end component;
signal pre,clr,clk,d:std_logic;
signal q,qn:std_logic;
begin
uut:exp8pr port map(pre=>pre,clr=>clr,clk=>clk,d=>d,q=>q,qn=>qn);
process
begin
pre<='0';clr<='1';wait for 10ns;
pre<='1';clr<='0';wait for 10ns;
pre<='0';clr<='0';wait for 10ns;
pre<='1';clr<='1';d<='0';wait for 10ns;
pre<='1';clr<='1';d<='1';wait for 10ns;
wait;
end process;
process
begin
clk<='0';wait for 5ns;
clk<='1';wait for 5ns;
end process;
end exp8pr_tb;

DICA Lab Manual -29- Department of ECE, VNITSW

 SIMULATION OUTPUTS:

VIVA QUESTIONS:
1. What is D-FF?
2. Define a latch?
3. Define a FF?
4. What is the difference b/w latch & FF?
5. In flip-flop how many stable states are there?
6. What is edge triggering
7. What is level triggering
8. I/P of D-F/F =’1’, then what is the O/P value Q=

RESULT: D flip-flop is simulated and verified.

DICA Lab Manual -30- Department of ECE, VNITSW

 Experiment No: 08 Date:

[Link] COUNTER

AIM: Simulation and verification of DECADE COUNTER(IC-7490) using Xilinx ISE Simulator.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

PIN DIAGRAM:

LOGIC SYMBOL:

DICA Lab Manual -31- Department of ECE, VNITSW

TRUTH TABLE:

Decimal
QD QC QB QA Equivalent
output

0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9

THEORY:

The decade counter (mod-10 counter) is used most often. In order to count from 0 through 9, a
counter with 3 flip-flops is not sufficient. With 4 flip-flops one can count from 0 to15 (16 states). Out of
these 16 states, we should skip any 6 states. In the decade counter, when the output is 1010 (for the
10thclock pulse), all the flip-flops should be reset. Thus the outputs Q 3 and Q1 are given directly to the
inputs of the AND gate and the outputs Q 2 and Q0 are given through inverters. Therefore, for the 10 th clock
pulse, the counter output would be 1010 for a moment. This sends the output of the AND gate to HIGH
clearing all the flip-flops. Thus a decade counter has been developed.

PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dec is
port(clk,rst,st:instd_logic;cout:out std_logic_vector(3 downto 0));
end dec;
architecture dec of dec is
signal ci:std_logic_vector(3 downto 0):="0000";
begin
process (clk)
begin
if rst='1' then ci<="0000";
elsif st='1' then ci<="1001";
elsif(clk'event and clk='1') then
ci<=ci+'1';
if(ci="1001")then ci<="0000";
end if;
end if;
end process;
cout<=ci;
end dec;

SIMULATION OUTPUTS:

DICA Lab Manual -32- Department of ECE, VNITSW

 VIVA QUESTIONS:
1. What is a counter?
2. what are the asynchronous inputs
3. To restrict the count value of a counter, if takes the help of inputs.
4. To restrict the count value of a counter, if takes the help of inputs.
5. Define mod –up counter.
6. Define mod –down counter.
7. Difference b/w mod-up counter and mod-down counter.

RESULT: Decade counter is simulated and verified.

DICA Lab Manual -33- Department of ECE, VNITSW

 Experiment No: 09 Date:
[Link] REGISTER

AIM: Simulation and verification of SHIFT REGISTER(IC-7495A) using Xilinx ISE Simulator.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

PIN DIAGRAM:

CIRCUIT DIAGRAM:

DICA Lab Manual -34- Department of ECE, VNITSW

THEORY:

A shift register is an n-bit register with a provision for shifting its stored data by one bit position at
each tick of the clock. The serial input, SERIN, specifies a new bit to be shifted into one end at each clock
tick. This bit appears at the serial output, SEROUT, after ‘n’ clock ticks, and is lost one tick later. Thus, an
n-bit serial-in, serial-out shift register can be used to delay a signal by n clock ticks.
A serial-in, parallel-out shift register has outputs for all of its stored bits, making them available to
other circuits. Such a shift register can be used to perform serial-to-parallel conversion.
Conversely, it is possible to build a parallel-in, serial-out shift register. At each clock tick the
register either loads new data from inputs 1D-ND or it shifts its current contents, depending on the value of
the LOAD/SHIFT control input. The device uses a 2-input multiplexer on each flip-flop’s D input to select
between the two cases. A parallel-in, serial-out shift register can be used to perform parallel-to-serial
conversion.
By providing outputs for all of the stored bits in a parallel-in shift register, we obtain the parallel-
in, parallel-out shift register. Such a device is general enough to be used in any of the applications of the
previous shift registers.

PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
entity shiftregister is
port(clk,sein,mode:in std_logic;
pllin:in std_logic_vector(3 downto 0);
cout:out std_logic_vector(3 downto 0));
end shiftregister;
architecture sr of shiftregister is
signal cout1:std_logic_vector(3 downto 0);
begin
process (clk)
begin
if (mode='1' and sein='0')then cout1<=pllin;
elsif (mode='0' and sein='1')then
cout1(0)<='1';
cout1(1)<='0';
cout1(2)<='0';
cout1(3)<='0';
else
cout1<="0000" ;
end if;
end process;
cout<=cout1;
end sr;

DICA Lab Manual -35- Department of ECE, VNITSW

 SIMULATION OUTPUTS:

VIVA QUESTIONS:
1. What is a register?
2. What is a shift register?
3. What are the operations performed by a shift register?
4. Applications of SISO shift register.
5. Applications of PISO shift register.
6. Applications of SIPO shift register.
7. Applications of PIPO shift register.
8. What is the IC package?
9. What is a universal shift register?
10. What are the operations performed by a universal shift register?
11. Applications of SISO universal shift register.
12. Applications of PISO universal shift register.
13. Applications of SIPO universal shift register.
14. Applications of PIPO universal shift register.
15. What is the IC package?
16. Difference b/w shift register and universal shift register.

RESULT: Shift register is simulated and verified

Experiment No: 10 Date:

10.8 bit Serial in –parallel out and Parallel in serial-out

DICA Lab Manual -36- Department of ECE, VNITSW

AIM :Simulation and verification of 8 bit Serial in –parallelout and Parallel in serial -out using Xilinx ISE
Simulator.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

Block Diagram for Serial in –parallelout

Block Diagram for Parallell in –Serial out

VHDL Code for Serial in –parallel out

library ieee;
use ieee.std_logic_1164.all;

DICA Lab Manual -37- Department of ECE, VNITSW

entity sipo is
port(
clk, clear : in std_logic;
Input_Data: in std_logic;
Q: out std_logic_vector(3 downto 0) );
end sipo;

architecture arch of sipo is

begin

process (clk)
begin
if clear = '1' then
Q <= "0000";
elsif (CLK'event and CLK='1') then
Q(3 downto 1) <= Q(2 downto 0);
Q(0) <= Input_Data;
end if;
end process;
end arch;

VHDL Code for Parallel in serial-out

library ieee;
use ieee.std_logic_1164.all;

entity piso is
port(mode,clk1,clk2,serial:in std_logic;
a;in std_logic_vector(7 downto 0);
q: buffer std_logic_vector(7 downto 0);
end piso;
architecture behavioral of piso is
begin
process(mode,clk1,clk2,serial,a)
begin
if mode=’1’ and (clk2=’1’ and clk2’event) then q<=a;
elsif mode=’0’ and (clk1=’1’ and clk1’event) then q<= serial&q(3)&q(2)&q(1);
end if;
end process;

MODEL
SIMULATION
OUTPUTS
(SIPO)

DICA Lab Manual -38- Department of ECE, VNITSW

MODEL SIMULATION OUTPUTS (PISO)

RESULT: 8 bit Serial in –parallelout and Parallel in serial-out waveforms are verified.

Experiment No: 11 Date:

11. First in & First out (FIFO) Register

AIM :Simulation and verification of First in & First out (FIFO) register using Xilinx ISE Simulator.

APPARATUS:
1. Personal computer -1 no.

DICA Lab Manual -39- Department of ECE, VNITSW

 2. Xilinx ISE Simulator

VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FIFO is
port(
en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end FIFO;

architecture FIFO_arc of FIFO is

begin

fifo_design : process (en,clk,din) is

variable mem : std_logic_vector (3 downto 0) := (others => '0');
begin
if (en='1') then
if (rising_edge (clk)) then
dout<= mem(0);
mem := (din & mem(3 downto 1));
end if ;
end if;
end process fifo_design;

end FIFO_arc;

SIMULATED WAVEFORMS:

RESULT: First in & First out (FIFO) register waveforms are verified.

DICA Lab Manual -40- Department of ECE, VNITSW

 Experiment No: 12 Date:

12. MAC(Multiplier& Accumulator)

AIM:Simulation and verification of Multiplier& Accumulator using Xilinx ISE Simulator.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

VHDL code:

entity macunit is
Port ( x,y : in STD_LOGIC_VECTOR (2 downto 0);
clk1,rst1 : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (5 downto 0));
end macunit;
architecture Behavioral of macunit is
component pipo

DICA Lab Manual -41- Department of ECE, VNITSW

Port ( u : in STD_LOGIC_VECTOR (5 downto 0);
clock : in STD_LOGIC;
rst : in STD_LOGIC;
w : out STD_LOGIC_VECTOR (5 downto 0));
end component;
component multiplier
Port ( l,m : in STD_LOGIC_VECTOR (2 downto 0);
n : out STD_LOGIC_VECTOR (5 downto 0));
end component;
signal t:std_logic_vector(5 downto 0);
begin
g0: multiplier port map(x,y,t);
g1: pipo port map(t,clk1,rst1,z);
end Behavioral;
entity multiplier is
Port ( l,m : in STD_LOGIC_VECTOR (2 downto 0);
n : out STD_LOGIC_VECTOR (5 downto 0));
end multiplier;
architecture Behavioral of multiplier is
component and1
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
component hadder
port( i,j : in STD_LOGIC;
su,ca : out STD_LOGIC);
end component;
component fulladd
Port ( d,e,f : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end component;
component or1
Port ( a1,b1 : in STD_LOGIC;
c1 : out STD_LOGIC);
end component;
signal p,q: std_logic;
signal r : std_logic_vector( 8 downto 0);
signal s : std_logic_vector ( 3 downto 0);
signal si: std_logic_vector(3 downto 1);
signal sic: std_logic_vector(3 downto 1);
signal sumor: std_logic;
begin
l0: and1 port map ( l(0),m(0),r(0));
l1: and1 port map ( l(1),m(0),r(1));
l2: and1 port map ( l(0),m(1),r(2));
l3: and1 port map ( l(2),m(0),r(3));
l4: and1 port map ( l(1),m(1),r(4));
l5: and1 port map ( l(0),m(2),r(5));
l6: and1 port map ( l(2),m(1),r(6));
l7: and1 port map ( l(1),m(2),r(7));
l8: and1 port map ( l(2),m(2),r(8));
n(0)<= r(0);

DICA Lab Manual -42- Department of ECE, VNITSW

m1: hadder port map (r(1),r(2),n(1),s(1));
m2: hadder port map (s(1),r(3),si(1),sic(1));
m3: hadder port map (r(4),r(5),si(2),sic(2));
m4: hadder port map (si(1),si(2),n(2),s(2));
m5: hadder port map (sic(1),sic(2),si(3),sic(3));
m8: or1 port map (s(2),si(3),sumor);
m6: fulladd port map (sumor,r(6),r(7),n(3),s(3));
m7: fulladd port map (s(3),sic(3),r(8),n(4),n(5));
end Behavioral;
entity and1 is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end and1;
architecture Behavioral of and1 is
begin
c<= a and b;
end Behavioral;
entity or1 is
Port ( a1,b1 : in STD_LOGIC;
c1 : out STD_LOGIC);
end or1;
architecture Behavioral of or1 is
begin
c1<= a1 or b1;
end Behavioral;

entity hadder is
Port ( i,j : in STD_LOGIC;
su,ca : out STD_LOGIC);
end hadder;
architecture Behavioral of hadder is
begin
su<= ixor j;
ca<= i and j;
end Behavioral;

entity fulladd is
Port ( d,e,f : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end fulladd;
architecture Behavioral of fulladd is
component and1
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
begin
sum <= d xor e xor f;
carry <= ((d and e) or ( e and f ) or ( f and d));
end Behavioral;
entity pipo is
Port ( u : in STD_LOGIC_VECTOR (5 downto 0);
clock : in STD_LOGIC;

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rst : in STD_LOGIC;
w : out STD_LOGIC_VECTOR (5 downto 0));
end pipo;
architecture Behavioral of pipo is
component dff
port(data,clk,reset : in STD_LOGIC;
output : out STD_LOGIC);
end component;
begin
d0: dff port map ( u(0),clock,rst,w(0));
d1: dff port map ( u(1),clock,rst,w(1));
d2: dff port map ( u(2),clock,rst,w(2));
d3: dff port map ( u(3),clock,rst,w(3));
d4: dff port map ( u(4),clock,rst,w(4));
d5: dff port map ( u(5),clock,rst,w(5));
end Behavioral;

entity dff is
Port ( data,clk,reset : in STD_LOGIC;
output : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(clk)
begin
if(reset='1') then output<= '0';
elsif( clk'event and clk='1') then output<= data;
end if;
end process;
end Behavioral;

Schematic diagram of MAC Unit:

SIMULATED OUTPUTS:

DICA Lab Manual -44- Department of ECE, VNITSW

RESULT: MAC unit waveforms are verified.

Experiment No: 13 Date:

[Link] ( Arithmetic Logical Unit)

AIM:Simulation and verification of ALU ( Arithmetic Logical Unit) using Xilinx ISE Simulator.

APPARATUS:
1. Personal computer -1 no.
2. Xilinx ISE Simulator

BLOCK DIAGRAM:

FUNCTION TABLE:

DICA Lab Manual -45- Department of ECE, VNITSW

VHDL CODE:

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.NUMERIC_STD.ALL;

entityalu is
Port ( inp_a : insigned(3 downto0);
inp_b : insigned(3 downto0);
sel : inSTD_LOGIC_VECTOR(2 downto0);
out_alu : outsigned(3 downto0));
endalu;

architectureBehavioral ofalu is
begin
process(inp_a, inp_b, sel)
begin
casesel is
when"000"=>
out_alu<= inp_a + inp_b; --addition
when"001"=>
out_alu<= inp_a - inp_b; --subtraction
when"010"=>
out_alu<= inp_a - 1; --sub 1
when"011"=>
out_alu<= inp_a + 1; --add 1
when"100"=>
out_alu<= inp_a andinp_b; --AND gate
when"101"=>
out_alu<= inp_a orinp_b; --OR gate
when"110"=>
out_alu<= notinp_a ; --NOT gate

DICA Lab Manual -46- Department of ECE, VNITSW

 when"111"=>
out_alu<= inp_axorinp_b; --XOR gate
whenothers=>
NULL;
endcase;

endprocess;
endBehavioral;

SIMULATED OUTPUTS:

RESULT: ALU unit waveforms are verified.

DICA Lab Manual -47- Department of ECE, VNITSW