Anusha Meneni
Mail id: anukit.07@[Link]
Ph no: 9951115076
Technical Experience Summary:
4.5 years experience in block level, the APR flow in Physical Design, Floorplan, Custom Analog
routing, PNR, Timing (STA-DMSA) using FC, Innovus.
Responsible for Physical implementation-starting from RTL to GDS2.
Excellent understanding of the complete ASIC flow.
Handled Block level Physical Design which involves Floor-planning, Power-planning,
Placement,CTS and Routing.
Good knowledge about creating a good floorplan based upon the architecture
Handled Timing critical, Congestion critical (Global Congestion & Local Congestion ) , PhyV
critical ( DRC FEOL & BEOL ) , EMIR critical blocks.
Hands-on wrt PT-STA (with and without SI , DMSA ) & PT-ECOs , LEC ( Gate2Gate , RTL2Gate) ,
EMIR analysis and fixes , PhyV ( DRC,LVS,ANT,DFM etc )
Worked for Manual DRC BEOL fixes.
Hands-on wrt UPF implementation and doing Static-checks using VCLP and Multi-Voltage
checks.
EDA Tools:
Innovus, ICC2, FC, Prime Time, StarRC, IC Validator, Calibre.
Scripting:
TCL/AWK/Shell
Languages: Verilog, Basic C
Professional Work Experience:
August 2024 to till date: Radiant Semiconductors
November 2023 to August 2024: Krisemi Design Technologies [Link]
May 2022 to November 2023: Mirafra Technologies [Link].
Dec 2020 to May 2022: Avast Technologies
Clients worked for: Broadcom, AMD, Intel
Education: [Link] (VLSI System Design),JNTUH
[Link] (EIE), JNTU, Hyderabad
Projects Details:
Project :1
Block-1
Technology: 5 nm, Instance count: 3.5million, Frequency: 1 GHz, Metal layers:17
Tool: Cadence Innovus, PrimeTime,calibre
Role and Responsibilities
Role: Block-Level PnR Implementation from Netlist-GDSII
Responsibilities:
Involved in complete physical design flow.
Applied placement techniques to fix congestion and to meet the timing margins
Tried multiple experiments like bounds, path grouping to converge the timing.
Analyzed the large latency value and tried fixing them
To converge interface timing, applied path groups for the violating paths at place stage.
Done Timing analysis and Timing closure with the top level team.
Fixing of DRVs, max tran and cap violations, clock coupling, noise and signalEM violations.
Performed Ecos to meet the timing
Fixed DRC shorts manually
Block-2
Technology: 5 nm, Macros:3, Instance count: 0.73 million, Frequency: 1 GHz, Metal layers:17
Tool: Cadence Innovus, PrimeTime, calibre
Role and Responsibilities
Role: Block-Level PnR Implementation from Netlist-GDSII
Responsibilities:
Done different Floorplan experiments to meet timing margins.
Solved DRC issues, by applying some blockages over the macros.
Analyzed shorts/opens and fixes done.
Fixed no clock cells and tran issue.
Analyzed timing and fixes done.
Worked on signoff flow to close timing and DRVs
Project:2
Block-1
Technology: 6 nm, Macros:33, Instance count: 2.4 million, Frequency: 0.9 GHz, Metal layers:13
Tool: Cadence Innovus, PrimeTime,calibre
Role and Responsibilities
Role: Block-Level PnR Implementation from RTL-GDSII
Responsibilities
Involved in complete physical design flow.
Performed multiple iterations of floorplan to get better placement and timing.
Tried multiple experiments like bounds, path grouping to converge the timing.
Done Timing analysis and Timing closure.
Fixing of DRVs, max tran and cap violations.
Performed Ecos to meet the timing
Block-2
Technology: 6 nm, Macros:19, Instance count: 2.1 million, Frequency: 0.9 GHz, Metal layers:13
Tool : Cadence Innovus, PrimeTime,calibre
Role and Responsibilities
Role: Block-Level PnR Implementation from RTL-GDSII
Responsibilities
Done different Floorplan experiment and lot of path groups to meet the timing issues
Block was routing critical and removed NDRs for a few clock nets carefully without
impacting timingand clock tree quality metrics
Had to do different Floorplan exp and lot of path groups to meet the timing issues.
Worked on signoff flow to close timing and DRVs.
Project:3
Block-1
Technology: 22nm, Macros:56, Instance count: 890k, Frequency: 0.9 GHz, Metal layers:10
Tool : FC,Star-Rc PrimeTime,calibre
Role and Responsibilities
Role: Block-Level PnR Implementation from RTL-GDSII
Challenge: Congestion, Timing critical
Responsibilities
Synthesis and PnR implementation for a block.
Done multiple Floorplan iterations to balance between Congestion and Timing issues.
Done ECO generation and Implementation
Done Timing Analysis and Timing closure using Primetime.
Successfully participated in both Base and Metal Tape-out
Block-2
Technology: 22nm, Macros:42, Instance count: 750k, Frequency: 0.9 GHz, Metal layers:10
Tool : FC,Star-Rc PrimeTime,calibre
Role and Responsibilities
Role: Block-Level PnR Implementation from RTL-GDSII
Challenge: Congestion, Timing critical
Responsibilities:
Synthesis and PnR implementation for a block.
Resolved para issues reported by FCT so rename the terminal name with the port name. Some
terminals are missed so, created manually.
Fixing the DRVs (max. Tran and max. Cap violations) was critical.
Used clock pull and push to meet timing.
Done ECO generation and Implementation
Successfully participated in both Base and Metal Tape-out.
Project:4
Block-1
Technology: 7nm, Macros:24, Instance count: 600k, Frequency: 1.2GHz, Metal layers:11
Tool: ICC II, PrimeTime, calibre
Role and Responsibilities
Role: Block-Level PnR Implementation from Netlist-GDSII
Challenge: Congestion, Timing critical
Responsibilities:
Synthesis and PnR implementation for a block.
Work involved Physical Aware Synthesis and in PnR hadFloorplan, Placement, CTS,
Routing, EMIR, ECO, DRC/LVS.
Worked on different timing optimization techniques to meet timing requirements and
taped out within deadlines
Block-2
Technology: 7nm, Macros:24, Instance count: 913k, Frequency: 1.2GHz, Metal layers:11
Tool: ICC II, PrimeTime
Role and Responsibilities
Role: Block-Level PnR Implementation from Netlist-GDSII
Challenge: Routing and Timing critical
Responsibilities:
Worked on different timing optimization techniques to meet timing requirement and
done area recoveryin eco stage taped out within deadlines.
The logic levels are high (>40) and the modules are splitting due to port connectivity.
Controlled the Module placement using bounds, and path groups for better timing.
Project:5
Block-1
Technology: 10nm, Macros:4, Instance count: 756k, Frequency: 1.8GHz, Metal layers:11
Tool: ICC II, PrimeTime,calibre
Role and Responsibilities
Role: Block-Level PnR Implementation from Netlist-GDSII
Challenge: Timing critical
Responsibilities:
PnR implementation for a Low power block by creating Voltage-Areas. Work involved in
Floorplan, Placement, CTS, Routing, ECO. Worked on different timing optimization
techniques to meet timing requirements and taped out within deadlines.