BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI K K BIRLA GOA CAMPUS

Microelectronics Circuits (ECE/EEE/INSTR F244) Tutorial on MOSFET Cascode amplifiers

Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design the circuit with the condition that the current flowing through the circuit is 100 μA and an output
resistance of 500 kΩ. Can we fabricate it with 0.18-μm CMOS technology for which VDD =1.8 V; Vtp =−0.5 V,
′
μp Cox =90 μA/V2 , and VA =−5 V/μm. Assuming two transistors are identical and |VOV |=0.3 V, determine
L and W/L for each transistor, and the values of the bias voltages VG3 and VG4 .

VDD

VG4 Q4

ro4

VG3 Q3

(gm3 ro3 )ro4

Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The cascode current source shown in figure, must be designed for a bias current of 0.5 mA. Assume μn Cox =
100 μA/V2 and Vtn =0.4 V.

(a) Neglecting channel-length modulation, compute the required value of Vb2 . What is the minimum tolerable
value of Vb1 if M2 must remain in saturation?

(b) Assuming λ=0.1 V−1 , calculate the output impedance of the circuit.

W 30
Vb1 M1 =
L 0.18

Vb2 W 20
M2 =
L 0.18

Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ECE/EEE/INSTR F244 Page 1 of 2

Show that the output resistance of the circuits depicted in Figure, can be written as Rout = g 1
m2

Rout

Vb1 M1

M2

Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The common-gate stage of figure below employs the current source M3 as theload to achieve a high voltage
W 40 μm
gain. For simplicity, neglect channel-length modulation in M1 . Assuming = , λn =0.1 V−1 , and
L 3 0.18 μm
λp =0.2 V−1 , design the circuit for a voltage gain of 20, an input impedance of 50 Ω, and a power budget of
13 mW. Given VDD =1.8 V, μn Cox =100 μA/V2 , μp Cox =50 μA/V2 , Vth,n =0.4 V, |Vth,p |=0.5 V,IREF =ID5 ,
VGS5 =0.5 V.

VDD

M4 M3
Vout

M1 Vb
IREF
Vin

MREF M5 M2

ECE/EEE/INSTR F244 Page 2 of 2