Power Aware Static Verification

Agenda

• Design Trends Impacting Static Verification

• Why is Power Management Critical?
• Impact of Power Management on CDC
• Typical Power Aware CDC Bugs
• Power Aware Static Verification Using VC SpyGlass
• Verdi Debug
Synopsys Confidential Information © 2022 Synopsys, Inc. 2
 Design Trends Impacting Static Verification

Number of power/voltage domains

100% 4% 4% 5%
5% 5% 6%

13% 14%
14%
• Number of power/voltage domains
80% >20
continue to grow
11-20
28% 28%
60% 29% 6-10

4-5
• Low power, multi-voltage verification
3
40% 20% 20%
19% increasingly critical at every step of
2 design flow
20% 16% 18% 1
17%

13% 12% 11%

0%
2019 2020 2021
Synopsys Global User Survey, 2021

Synopsys Confidential Information © 2022 Synopsys, Inc. 3

 Design Trends Impacting Static Verification
Synopsys Global User Survey, 2018

Voltage Domains Shutdown Domains

100% 2% 3% 100%
3% 3% 4% 5%
4% 4% 5% >20 3%
8% 4% >20
11% 9%
10% 13% 7%

80% 80% 12%

11-20 11-20
15%
18%
23% 26%
26% 6-10 6-10
60% 60% 28%

4-5 4-5

40% 40% 48%

42% 1-3* 70% 1-3*
40%
59% 35%

20% 2-3 20% 2-3

15% 1 18% 1
13% 13%
0% 0%
2016 2017 2018 2016 2017 2018

Low Power, Multi-voltage Verification Must be Performed at Every Step of Design Flow

Synopsys Confidential Information © 2022 Synopsys, Inc. 4

Why is Power Management Critical?
• Power Management enables reduced power
consumption with desired functionality
– Reduce static leakage and dynamic power
consumption Subsystem 1
– Smaller area with more functionality with Sub system 2
power gating with
– Enhanced battery backup power gating &
– Lighter products retention

• Low power techniques introduce power intent

logic Macros with
Multiple voltages
– Isolation cell
Power Management Unit
– Retention cell
– DVFS (Dynamic Voltage and Frequency Scaling)…

Synopsys Confidential Information © 2022 Synopsys, Inc. 5

 Impact of Power Management on CDC Analysis

• Power intent logic provided by designer in Unified Power Format (UPF)

• Power cells introduced during gate level translation

• Power intent logic not implemented in RTL

– Conventional CDC signoff tool not able to catch CDC issues

• Need to ensure low power technique is not breaking any qualified CDC paths
– Designers must verify zero introduction of new bugs in design

With Introduction of Power Intent Logic, Design is no Longer CDC Clean

Power aware CDC Verification Must for RTL with UPF instrumentation
Synopsys Confidential Information © 2022 Synopsys, Inc. 6
Typical Power Aware CDC Bugs

Synopsys Confidential Information © 2022 Synopsys, Inc. 7

Isolation Cell Causes Metastability

• Isolation cells are power cells

inserted during synthesis to PDA PDA
isolate buses/wires crossing from
FF1 FF2
power-gated domain to its ISO

always-on domain CLK_A CLK_A

PDB Unsafe Structure

• Isolation cell may introduce extra
FF3
unsynchronized CDC crossings
at netlist level which is active at CLK_B

RTL level
Additional CDC crossing from FF3 to FF2
introduced due to UPF instrumentation

Synopsys Confidential Information © 2022 Synopsys, Inc. 8

Isolation Cell Results in Potential Glitch

PDA PDB PDB

FF1 FF2 FF2

ISO

CLK_A CLK_B CLK_B

PDA Unsafe Structure

FF3

CLK_A

• Isolation cell introducing combo logic between a valid synchronizer causing

glitch at output of at AND gate
Synopsys Confidential Information © 2022 Synopsys, Inc. 9
Isolation Cell Introduces Clock Glitch

• After synthesis, isolation cell PDA

introduced on clock path CLK_A FF2
crossing power domains ISO

– Isolation signal generated from

different clock domain CLK_B.
• This corrupts clock at destination PDB Introducing clock glitch in clock path

and causes glitches on clock FF3

path
CLK_B
• Designer should ensure that only
a few signals sequences are
possible making the design
operation safe

Synopsys Confidential Information © 2022 Synopsys, Inc. 10

Isolation Cell Leads to Reset Domain Crossing
• No RDC between FF1 and FF2
– FFs running on same resets
PDA PDA
• Additional RDC crossing from FF1 FF2
CLK_A CLK_A
FF3 to FF2 introduced due to ISO

UPF instrumentation RST_A RST_A

– FF3 and FF2 running on different

domain resets PDB Unsafe Structure

CLK_A FF3
• ISO policy precedence analysis
must be consistent with DC/ICC RST_B

– If not, potential bugs will be

missed in RTL or false negative
violation flagged

Synopsys Confidential Information © 2022 Synopsys, Inc. 11

Voltage Domain Crossing
• Voltage domain crossing introduce
asynchronous clock domains PDA VDD, 1.2 V VDD, 2 V PDB

FF1 FF2
• Data path FF1 to FF2 running on
different voltage domains
– Level shifter used in clock path to provide
required voltage
LS, 3 V  1.2 V LS, 3 V  2 V
• If both flops running on different clock
domain, path reported as
unsynchronized Voltage Domain Crossing due to LS

• Challenge: identification of voltage

domain crossings on synchronous path
to avoid failure

Synopsys Confidential Information © 2022 Synopsys, Inc. 12

Retention Cell Causes Unsynchronized Crossings

• Special flops with multiple

power supply
– Typically used as register to retain Save
its value when block in which it FF1
resides is shutdown PDB
CLK_A
Retention

• Retention cell can introduce CLK_C

unsynchronized paths FF2 Restore
– Save and Restore pins can be CLK_B
driven with different domain signals
Power
– Two unsynchronized CDC Control
crossings from FF1->Retention and
FF2->Retention introduced

Synopsys Confidential Information © 2022 Synopsys, Inc. 13

Power Aware Static Verification Using VC SpyGlass

Synopsys Confidential Information © 2022 Synopsys, Inc. 14

 VC SpyGlass Platform Overview
Industry leading static verification platform for RTL signoff

Lint CDC RDC DFT Constraints

10x noise reduction with AI vs.

AI/ML Enabled
competition
Hierarchical Formal
Power Aware
3x performance and ½ the memory vs. Signoff Enabled
competition Proven SpyGlass Engines

Multi-billion Gate Word-level Data Model

Synopsys Design Compiler,
PrimeTime, VCS, Verdi compatibility Highly accelerated multi-threading analysis

Verilog, VHDL, SystemVerilog, Lib,

UPF, SDC

Synopsys Confidential Information © 2022 Synopsys, Inc. 15

Power Aware Static Verification Methodology

UPF UPF RTL Real-Isolation Insertion

Parser Data Model Data Model

UPF Annotated Design

Instrumentation
through Netlist Edits set_app_var enable_lp_instrument true
….
read_upf [Link]
Instrumented UPF Annotated
Design

Lint CDC RDC .. Verdi

Leverage Industry-Proven VC LP Engines for Detection of Low-Power Static Bugs

Synopsys Confidential Information © 2022 Synopsys, Inc. 16
 Native UPF Instrumentation Supported in VC SpyGlass
Consistent interpretation across other Synopsys Implementation tools

• UPF 2.1/3.0/3.1 support available

UPF Logic Native instrumentation

• Native UPF instrumentation Isolation Cells Yes

supported
Retention Flops Yes
– All Synopsys implementation tool
constructs supported Power-switch Yes

Level-shifters Yes
• Powerful debug available
– Highlights UPF instrumented logic in
different colors

Synopsys Confidential Information © 2022 Synopsys, Inc. 17

Native UPF Aware Instrumentation
Pre-Isolation Insertion Virtual-Isolation Insertion Real-Isolation Insertion

Pre-Retention Insertion Virtual-Retention Insertion Real-Retention Insertion

Signoff Signoff Signoff

No Instrumentation Virtual Instrumentation Real Instrumentation
Synopsys Confidential Information © 2022 Synopsys, Inc. 18
Incremental Analysis Using Differential Report
Faster comparisons between non-UPF and UPF instrumented runs

RTL RTL+UPF
Manually identifying differences between runs is difficult
and time consuming
• Difference due to UPF instrumentation SDC Read SDC Read
CDC Analysis CDC Analysis

Run1 (Without UPF):

Severity Stage Tag Count

-------- ----- ---------------------- ----- CDC DB1 CDC DB2
error SYNC SYNCCDC_UNSYNC_NOSCHEME 10 2 extra CDC
-------- ----- ---------------------- ----- violations got
introduced due to
Run2 (With UPF):
UPF DB Diff
Severity Stage Tag Count instrumentation
-------- ----- ---------------------- ----- compare_violations
error SYNC SYNCCDC_UNSYNC_NOSCHEME 12
-------- ----- ---------------------- -----

Differential CDC Violations

Synopsys Confidential Information © 2022 Synopsys, Inc. 19

Ease of Setup

• vc_static_shell>set_app_var
vc_static_shell> set_app_var enable_lp_instrument
enable_lp_instrument true
true
• c_static_shell> read_upf
vc_static_shell> read_upf [Link]
[Link]
Existing customers

vc_static_shell>
vc_static_shell> set_app_var
set_app_var enable_cdc|enable_rdc
enable_cdc|enable_rdc true true

vc_static_shell>
vc_static_shell> set_app_var enable_lp_instrument
set_app_var true
enable_lp_instrument true
vc_static_shell> set search_path “<space separated list of directories >”
vc_static_shell> set search_path “<space separated list of directories >” Design Setup & Read
vc_static_shell> set link_library “<space separated list of libs>”
vc_static_shell> set link_library “<space separated list of libs>” Section
vc_static_shell> analyze –format vhdl –work lib_name file_name.vhd
vc_static_shell> analyze –format vhdl –work lib_name file_name.vhd
vc_static_shell> analyze –format verilog –work lib_name file_name.v
vc_static_shell> analyze –format verilog –work lib_name file_name.v
vc_static_shell> read_sdc cdc_setup.tcl Configuring Checks &
vc_static_shell>
vc_static_shell> read_sdc
read_sdc cdc_setup.tcl
[Link] Reading Constraints/UPG
vc_static_shell>
vc_static_shell> read_upf [Link]
read_sdc [Link]
vc_static_shell> check_cdc|check_rdc
vc_static_shell> read_upf [Link]
vc_static_shell> report_cdc|report_rdc
Running & Reporting CDC
vc_static_shell> check_cdc|check_rdc Checks
vc_static_shell> quit
vc_static_shell> report_cdc|report_rdc

vc_static_shell> quit
Synopsys Confidential Information © 2022 Synopsys, Inc. 20
Verdi Debug

Synopsys Confidential Information © 2022 Synopsys, Inc. 21

Results Analysis
Spreadsheet
Toolbar

Search bar

Invoke
schematic
view

Select a
particular tag for Links to
schematic or
more details source code
viewer
Automatic filter
creation

Synopsys Confidential Information © 2022 Synopsys, Inc. 22

CDC Violations due to UPF Instrumentation

Filtering based on reason-code

to review UPF instrumented
CDC Violations

Synopsys Confidential Information © 2022 Synopsys, Inc. 23

Schematic Legend “Show/hide Legend” icon

“Show Legends” option in New

Violation Schematic

Synopsys Confidential Information © 2022 Synopsys, Inc. 24

Missing Synchronizer due to UPF Instrumentation
Source Destination
Object Object

Isolation
Cell

Synopsys Confidential Information © 2022 Synopsys, Inc. 25

 Retention Cell Introduces Missing Synchronizer
Source Destination
Object Object

Retention
Cell

Power domain boundary

will get highlighted in
different color, moving
cursor will show that
information

Synopsys Confidential Information © 2022 Synopsys, Inc. 26

Power Switch Introduces Missing Synchronizer
Source Destination
Object Object

Power Switch,
Control is connected
to acknowledgement

Synopsys Confidential Information © 2022 Synopsys, Inc. 27

Connect_logic_net Introduces Missing Synchronizer
Source Destination
Object Object

Instrumented net with

connect_logic_net
command

Synopsys Confidential Information © 2022 Synopsys, Inc. 28

Glitch on Control Path due to UPF Instrumentation
Source Destination
Object Object

Isolation
Cell

Synopsys Confidential Information © 2022 Synopsys, Inc. 29

Powerful Schematic Trace Options
Tracing commands for different debug scenarios

Trace driver/load Trace fan-in/out cone

Trace connectivity Trace two points

Synopsys Confidential Information © 2022 Synopsys, Inc. 30

VC SpyGlass TCL Shell Interface
Terminology about different types of objects

Same as DC/ICC

Synopsys Confidential Information © 2022 Synopsys, Inc. 31

Thank You
What is Clock Domain Crossing (CDC)?
Synchronizer Required!

Metastability (non deterministic value) can cause chip failures!

Synopsys Confidential Information © 2022 Synopsys, Inc. 33
 What is Reset Domain Crossing (RDC)?

• Metastability (Non deterministic value) scenarios caused by Asynchronous Reset Assertion

• Race condition between reset and clock

Source Destination Setup + hold time window

Domain Domain
FF1 FF2
q1 d2 q2
D Q D Q

QB QB

RSTB RSTB
Metastable net
rst1 rst2

CLK

Metastable value

Metastability (non deterministic value) can cause chip failures!

Synopsys Confidential Information © 2022 Synopsys, Inc. 34

CDC Verification Scenarios on UPF Instrumented Logic
Isolation Cell Insertion Causing Metastability CDC on Save-restore pins of Retention Flops

Level-shifters causing New Clock-domain Power-switch introducing New CDC Path

Synopsys Confidential Information © 2022 Synopsys, Inc. 35