Journal of VLSI Circuits and Systems, ISSN: 2582-1458 Vol. 4, No. 1, 2022 (pp.

7-11)

RESEARCH ARTICLE [Link]

An Improved Design of Low-Power High-Speed

Accuracy Scalable Approximate Multiplier
Jagadeesh Bodapati1, Oggi Sudahkar2, Atava G V Karthik Raju3
1
Professor, Department of ECE, Godavari Institute of Engineering and Technology, Rajahmundry-5332961,
2
Assistant Professor, Department of ECE, Godavari Institute of Engineering and Technology
3
Assistant Professor, Department of ECE, GIET Engineering College

KEYWORDS:
Approximate multiplication, AbstrAct
Approximate Tree Compressor (ATC),
Carry Maskable Adder (CMA), Approximate multiplication is a technique that can be used to reduce energy con-
Partial Product tree, Accuracy scalability. sumption and improve accuracy. Multiplication is a fundamental function of many
error-tolerant applications. The proposed accuracy-controllable multiplier can be dy-
namically adjusted to meet the accuracy requirements. It can generate a carry-mas-
ARTICLE HISTORY:
Received: 11.11.2021
kable product with a defined length. The proposed algorithm can dynamically modify
the carry propagation length for optimal accuracy. The proposed tree compressor has
Accepted: 22.01.2022
Published: 23.02.2022
a partial product tree that is approximated by the carry maskable adder. The partial
product tree is computed by the proposed multiplier. The proposed approximate mul-
tiplier is proposed to consist of an ATC and a carry-maskable adder. The ATC and the
DOI: CMA are both power-efficient and feature a simple circuit structure.
[Link]
Author’s e-mail: bjagadeesh@[Link], oggisudhakar@[Link], karthik.raju01@
[Link]

How to cite this article: Bodapati J, Sudahkar O, Raju AGVK. An Improved Design of
Low-Power High-Speed Accuracy Scalable Approximate Multiplier Journal of Comple-
mentary Research, Vol. 4, No. 1, 2022 (pp. 7-11).

IntroductIon adder. The masking carry propagation of the CPA is

achieved by replacing it with theproposed CMA. A tree
Most commonly, image processing and recognition compressor is used to reduce the accumulation layer
applications are tolerant of small inaccuracies. This depthof a partial product tree. A term that simplifies the
function is typically used in high-complexity applications process of achieving power andaccuracy requirements
where computational accuracy is not an issue. However, is introduced. This concept simplifies the process
it can also be used to reduce power consumption. of implementing a partial product reduction (PPR)
Approximate computing is a technique that can reduce the component. An approximate multiplier is a combination
power consumption and increase the reliability of error of acompressor and adder. It is commonly used in the
tolerant applications. This procedure is commonly used in design of calculators. This multiplier was implemented in
error tolerant domains.[1] Different kinds of error-tolerant Verilog HDL. It is a combination of the conventional and
applications have varying requirements when it comes to approximate multipliers.
accuracy. If the accuracy of multiplication is set, power The remainder of this paper is organized as follows.
will be wasted if it is not required. If it is dynamically Section II reviews previous literature works. Section III
reconfigurable, then approximate multipliers should have introduces the accuracy scalable approximate multiplier
the same accuracy requirements for different program after explaining the tree compressor and the CMA. Section
phases. The paper aims to develop an approximate IV evaluates the multipliers experimentally and simulation
multiplier designthat can dynamically control the accuracy results were presented. Section V presents our conclusions.
of a given function. This design can be configured to
work seamlessly with various carry propagation adders. LIterAture Work
A carrymaskable adder is proposed to enable a programmer The adder is a basic component of most multipliers.
to dynamically modify the operation of a carry propagation Mahdiani et al.[2] proposed the lower-part-OR adder. It is

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 Jagadeesh Bodapati, et al. : An Improved Design of Low-Power High-Speed Accuracy Scalable Approximate Multiplier

commonly utilized for adding the lower bits and the precise a AND b, so (c + s) can be generated by a OR b. Based on
adders for the upper bits. It uses the same concept as our theabove, consider the basic logiccell shown in Fig. 1(b),
proposed CMA, but it uses a dynamically reconfigurable forwhich the following equations results
method. A carry propagation delay reduction technique
was proposed by Liu et al. In this study, Liu et aL.[3]
proposed an approximate adder to reduce the carry
propagation delay of partial product accumulation. They
proposed a recovery vector that can improve the accuracy
An incomplete adder cell or an iCAC is a cell that shows
of an operation. The recovery vector can be selected with
the truth about a given adder Table I. Ascan be seen, q
the help of a designer.
is equal to c. While p is not equal to s, the precisesum
In order to reduce the size of the multiplier, Hashemi
can be obtainedbyadding p and q, so the iCAC is not
et al.[4] propose a technique that uses the following
an approximate adder but an element of a precise
k bits for both inputs. Intricate techniques were proposed
adder. By extending the above equation to m bits, the
to reduce the size of a multiplier by detecting the leading
followingequation can be obtained:
bits of an input and selecting the following k bits for both
inputs. Both[3] and[4] allow a static trade-off between power
consumption and accuracy. The ability to maintain a static
trade off between power consumption and accuracy is where A, B, P, and Q are m-bit values, the bits of
very useful in terms of reducing system complexity. The whichcorrespond to a, b, p, and q, respectively. A row of
power consumption and accuracy limits are statically eight iCACs, used for 8-bit inputs, is shown in Fig. 2.
controlled. The recovery vectors and input operands are
defined during the design process and are not dynamically
controllable, unlike with our proposed multiplier.
A system-level technique that would disable a part of
the combinational logic was proposed by Moons et al [5].
It can also trade off accuracy for power. It can change the
number of pipeline stages and voltage scaling modes. Our
proposed multiplier disables a part of the logic in the CPA
that enables the reduction of power consumption. It does
not require a pipeline system or control circuits. Fig. 1: (a) Accurate half adder and (b) Incomplete
adder cell
Accuracy Controllable Multiplier
Table I: Truth Tables for Accurate Half Adder And
The design of the multiplier has 3 integral parts: (i) AND Incomplete Adder Cell
gate used for partial product generation; (ii) PPR using
an addertree; and (iii) addition to produce the finalresult
using a CPA. Powerconsumption and circuit complexity are
dominated bythe PPR [6], and the multiplier’s critical path
is dominated bythe propagated carry chain in the CPA [7].
This section is organized as follows. Section III-A
explainshow the partial product layer is simplified by the
approximatetree compressor. Section III-B introduces the
CMA. Finally, Section III-C presents the overall structure
of the accuracy scalable approximate multiplier, which
uses the proposedadder and treecompressor.

A. Approximate Tree Compressor

Figure 1(a) shows an accurate half adder, for which
thefollowing equation can be obtained:

where {,} and + denote concatenation and addition, Fig. 2: A row of incomplete adder cells with
respectively. a XOR b generates c and s is generated by two 8-bit inputs

8 Journal of VLSI circuits and systems, , ISSN 2582-1458

 Jagadeesh Bodapati, et al. : An Improved Design of Low-Power High-Speed Accuracy Scalable Approximate Multiplier

Fig. 4: (a) Carry-maskable half adder,

(b) Carry-maskable full adder
Fig. 3: Structure of an approximate tree compressor
with eight inputs

Lets us see the example of an 8-bit adder with the two

inputsA = 01011111 and B = 00110110. The accurate sum S
is10010101, while the row of iCACsproduces P = 01111111
andQ = 00010110. Resultant equation is

(1)
While S is obtained from P and Q, P can be used as
anapproximation for S, and Q can be used as anerror
recoveryvector for the approximate sum P.

Two 8-bit inputs:

A = {a7, a6, a5, a4, a3, a2, a1, a0}
B = {b7, b6, b5, b4, b3, b2, b1, b0}
Two 8-bit outputs:
Approximate sum: P = {p7, p6, p5, p4, p3, p2, p1, p0}
Error recovery vector: Q = {q7, q6, q5, q4, q3, q2, q1,
q0}
Converting the row of iCACs to n from two to three is an
efficient method to get the n/2 Qs. If the sum of the two
Qs is equal to one, the number of Qs becomes reducedto
one. Remember that P is greater than S and Q is equal to Fig. 5: Structure of 8-bit Multiplier
C. OR gates can be used to generate an approximate sum with 8x8 partial products
of the n/2 quints without losing accuracy.
In the proposed half adder, when mask_x is 0, S is equal
The approximate sum is the compensation vector that
to x OR y and Cout is equal to 0. If mask_x is 1, then the
relates to the accuracy of the tree. It is named after the
mask_x is equal to the xOR b and the xAOR y. When mask_x
approximate tree compressor. An ATC with eight inputs
is enabled, it does not function as an accurate half adder.
is called an ATC- n. The structure of its eight inputs is
It can also be turned on by default. The proposed adder
shown in Fig. 3. The rectangles represent the rows and
is similar to the Half adder in that it works as an accurate
the number of iCACS in each row. For example, if there
adder when mask_x is enabled. It outputs either Cout or
are four miCACs in D1, D2, etc., then four rows of m-bits
S, depending on the option.
are required to build an ATC-8. To construct the ATC-8, we
need to construct four approximate sums, four correctness C. Overall Structure
recovery vectors, and four error compensation gates. An n-bit multiplier consists of 2n rows, each of which has
B. Carry-Maskable Adder n partial products (PP), so there are nxn PPs in total.
Usingthe ATC-n introduced in the previous section, the
A carry-maskable CMA is proposed to enable precise
rows can be replaced by rows. Figure 5
control of the accuracy of the data. It is similar to a
shows an example of an8-bit multiplier with 8 x 8 PPs.
k-bit CPA in that it has a carry-maskable half-adder and
The PPR is performed in threestages (Stage 1, Stage 2,
a carry-maskable full adder. The structures of the carry-
and Stage 3) and the CPA is performedin Stage 4. The PP
maskable partial and fulladders are presented in Fig.4.

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 Jagadeesh Bodapati, et al. : An Improved Design of Low-Power High-Speed Accuracy Scalable Approximate Multiplier

generation step is not shown. Each dotrepresents a PP.

The least significant bit (right side) is bit 0, andthe most
significant bit (left side) is bit 14. The solid rectanglesin
Stage 1 represent ATCs and the dashed rectangles
represent rows of seven iCACs. Every row of iCACs includes
PPs that are not processed: for example, the PP at position
0 in the firstrow and the one at position 8 in the second
row of the first iCAC block in ATC-8 are not processed.
In Stage 1, eight rows of PPs are reduced to four rows
(P1,P2, P3, and P4) and one accuracy compensation vector
(V1) byan ATC-8. The four rows are further reduced to two Fig. 6: Simulation result for Incomplete adder cell
rows (P5and P6) and another accuracy compensation vector
(V2) by anATC-4. A final row of iCACs then processes P5
and P6 andgenerates P7 and Q7. In summary, Stage 1 uses
an ATC-8, anATC-4, and a row of seven iCACs to compress
the 8 x 8 PPsto four rows (P7, V1, V2, and Q7).
In Stage 2, there are four PPs for each of bits 4 to 10.
Inorder to achieve a lower path delay, OR gates are used
to sumV1 and V2 approximately. The empty circles for
V1 and V2represent the bits which are summed using OR
gates. Seven ORgates are required in total and the four
rows are compressedto three.
In Stage 3, full adders and half adders are used to
compressthe three rows to two. Two half adders are Fig. 7: Simulation result for Carry Maskable Half Adder
required for bits 1and 13, and eleven full adders are
required for bits 2 to 12.
Addition using a CPA is required after PPR to produce
thefinal result. For an 8-bit Wallace tree multiplier, the
length of CPA is 13. In Stage 4, the CPA is divided into
three parts inorder to reduce the length of the carry
propagation. Since thelower bits are not significant for
accuracy, bits 0 to 4 are definedas the truncated part and
three OR gates are used to generate thevalues for bits 2,
3, and 4 of the final result. Because there is nocarry out
from the truncated part, the length of the CPA isreduced
to 10. Since the upper bits are the most significant Fig. 8: Simulation result for Carry Maskable Full Adder
foraccuracy, bits 12 to 14 are defined as the accurate part,
and threeaccurate adders are used to generate the values
for these bits ofthe final result.
The precision-scalable part of the CPA is between the
accurate and truncated parts. This part is very important
for both pathdelay and accuracy. In Stage 4, bits 5 to 11
in the CPA arereplaced by a 7-bit CMA. Note that every
1-bit CMA has amask_x signal. The u-bit upper bits are
configured as a 2-input or 2-out CPA gate. The lower bits
are used as mask_x signals. When u =7, it operates as a
7-bit CPA, while u = 0, it operates as a 2-input OR gate.
This feature cuts the power consumption by reducing the
switching activity in some logic gates.

Simulation Results
The proposed scalable accuracy approximate multiplier
was implemented using the Verilog HDL language in version Fig. 9: RTL Schematic for 8x8 Accuracy
controllable Multiplier

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 Jagadeesh Bodapati, et al. : An Improved Design of Low-Power High-Speed Accuracy Scalable Approximate Multiplier

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