Module-2

Bipolar Junction Transistors (BJT): PNP and NPN Transistors, Basic Transistor
Action, Input and Output Characteristics of CB, CE and CC Configurations, dc
and ac load line analysis, operating point, Transistor biasing: Fixed bias,
emitter bias/self-bias, Low-frequency response of CE amplifier.

Field Effect Transistors: JFET, Idea of Channel Formation, Pinch-Off and

saturation Voltage, Current-Voltage Output Characteristics; MOSFET: Basic
structure, operation and characteristics.

References
[1] Millman J., Halkias C.C., Parikh Chetan, “Integrated Electronics: Analog and Digital
Circuits and Systems”, Tata McGraw-Hill, 2/e.

[2] Boylstead R.L., Nashelsky L., “Electronic Devices and Circuit Theory”, Pearson
Education, Inc, 10/e.

[3] Mehta V. K., Mehta Rohit “Principles of Electronics ”, S. Chand., 11e

 Bipolar Junction Transistor (BJT)
➢The transistor is a three-layer semiconductor device consisting of either two n -
and one p -type layers of material or two p - and one n -type layers of material. The
former is called an npn transistor , and the latter is called a pnp transistor.
➢The emitter layer is heavily doped, with the
base and collector only lightly doped.
➢The outer layers have widths much greater
than the sandwiched p - or n -type material.
➢For the biasing shown in Fig. the terminals
have been indicated by the capital letters
E for emitter , C for collector , and B for base.
pnp Transistor npn Transistor
➢The abbreviation BJT, from bipolar junction transistor, is often applied to this
three-terminal device. The term bipolar reflects the fact that holes and electrons
participate in the injection process into the oppositely polarized material.

➢If only one carrier is employed (electron or hole), it is considered a unipolar

device such as FET (Field effect transistor).

Ref. [2]
 pnp- Transistor Operation
➢The operation of the npn transistor is exactly the same
if the roles played by the electron and hole are
interchanged.
➢In Fig.a the pnp transistor has been redrawn without
the base-to-collector bias. Note the similarities between
this situation and that of the forward-biased diode. The
depletion region has been reduced in width due to the (a) forward-bias
applied bias, resulting in a heavy flow of majority
carriers from the p - to the n -type material.
➢Remove the base-to-emitter bias of the pnp
transistor of Fig.a as shown in Fig.b. Consider the
similarities between this situation and that of the
reverse-biased diode. Recall that the flow of majority
carriers is zero, resulting in only a minority-carrier
flow, as indicated in Fig. b. (b) reverse-bias.

➢In summary, therefore: One p-n junction of a transistor is reverse-biased,

whereas the other is forward-biased

Ref. [2]
➢In Fig. c both biasing potentials have been applied to a pnp transistor, with the resulting
majority- and minority-carrier flows indicated
➢As indicated in Fig. c , a large number of majority
carriers will diffuse across the forward biased p–n
junction into the n -type material
➢Since the sandwiched n -type material is very thin
and has a low conductivity, a very small number of
these carriers will take this path of high resistance to
the base terminal. The magnitude of the base
current is typically on the order of μA, as compared
Fig. c Majority and minority
to mA for the emitter and collector currents.
carrier flow of a pnp transistor.
➢The larger number of these majority carriers will diffuse across the reverse-biased
junction into the p -type material connected to the collector terminal as indicated
in Fig.c. since collector is connected to the negative side of the voltage.
➢In other words, there has been an injection of minority carriers into the n -type
base region material. Combining this with the fact that all the minority carriers
in the depletion region will cross the reverse-biased junction of a diode
accounts for the flow indicated in Fig. c

Ref. [2]
Applying Kirchhoff’s current law to the transistor of Fig. c as if it were a single node,
we obtain
Valid for both pnp and npn transistors

➢Hence the emitter current is the sum of the collector and base currents
➢The collector current, however, comprises two components—the majority and
the minority carriers as indicated in Fig. c.

➢The minority-current component is called the leakage current and is given

the symbol ICO ( IC current with emitter terminal Open). The collector current,
therefore, is determined in total by
Valid for both pnp and npn transistors

➢For general-purpose transistors, IC is measured in mA and ICO is measured in

μA or nA. ICO , like Is for a reverse-biased diode, is temperature sensitive and
must be examined carefully when applications of wide temperature ranges are
considered. It can severely affect the stability of a system at high temperature if
not considered properly.

Ref. [2]
 Transistor notation and symbols

pnp transistor npn transistor

or
or

➢Note that emitter is shown by an arrow which indicates the direction of

conventional current flow with forward bias. For npn connection, it is clear that
conventional current flows out of the emitter as indicated by the outgoing arrow.
Similarly, for pnp connection, the conventional current flows into the emitter as
indicated by inward arrow.

Ref. [2]
 Transistor Configurations
➢A transistor can be configured in a circuit in the following three ways:
(i) Common base (CB) configuration
(ii) Common emitter (CE) configuration
(iii) Common collector (CC) configuration
(i) Common base configuration
➢To fully describe the behavior of a three-terminal
device such as the common-base amplifiers of Fig.
requires two sets of characteristics—one for the
driving point or input parameters and the other for
the output side.
➢ Note the input and output characteristics of npn
and pnp transistors are same except the directions
of current
➢The input set for the common-base amplifier as CB configuration for CB configuration for
shown in Fig. relates an input current ( IE ) to an pnp trans. npn trans.
input voltage (VBE) for various levels of output
voltage ( VCB ).

Ref. [2]
 Input or driving point characteristics
➢ Characteristics between input current ( IE ) and input voltage (VBE )
for various levels of output voltage ( VCB ).
➢As VBE or VEE increases the depletion region between the forward
biased emitter and base junction decreases and hence for VBE below the
cut-in voltage the emitter current is almost zero. Butt as the voltage VBE
becomes more than the cut-in voltage depletion region vanishes and
hence there is an exponential increases in the emitter current because of
the movement of holes from p region to n region where the holes are
attracted by the negative terminal of VCC.
➢ With the constant VBE if VCB or VCC increases more and more
number of holes are attracted by the negative terminal of VCC, which
further increase the current as shown in Fig.
➢The input characteristics of Fig. reveal that for fixed values of
collector voltage ( VCB ), as the base-to-emitter voltage increases, the
emitter current increases in a manner that closely resembles the
diode characteristics. In fact, increasing levels of VCB have such a
small effect on the characteristics that as a first approximation the
change due to changes in VCB can be ignored
➢That is, once a transistor is in the “on” state, the base-to-emitter
voltage can be assumed to be

Ref. [2]
 Output or collector characteristics
➢The output set relates an output current (IC ) to an output voltage ( VCB ) for
various levels of input current (IE )

➢The output or collector set of characteristics has three basic regions of

interest, as indicated in Fig. the active , cutoff , and saturation regions. The
active region is the region normally employed for linear (undistorted)
amplifiers.
➢In the active region the base–emitter junction is forward-biased, Fig.a
whereas the collector–base junction is reverse-biased.
➢At the lower end of the active region the
emitter current ( IE ) is zero (Fig. b), and the
collector current is simply that due to the reverse
saturation current ICO , as indicated in Fig. c.
➢The current ICO is so small (μA) in magnitude
compared to the vertical scale of IC (mA) that it
appears on virtually the same horizontal line as
IC 0.
➢The circuit conditions
that exist when IE=0 for
the common-base
configuration are shown
in Fig. c. The notation
most frequently used for Fig.c
ICO on data and specification sheets is, as indicated in Fig.c, ICBO (the Fig.b
collector-to-base current with the emitter leg open).
Ref. [2]
➢Note in Fig. b that as the emitter current increases above zero, the collector current increases to
a magnitude essentially equal to that of the emitter current as determined by the basic transistor-
current relations. Note also the almost negligible effect of VCB on the collector current for the
active region.
➢The curves clearly indicate that a first approximation to the relationship between I E and IC in the
active region is given by

➢As inferred by its name, the cutoff region is defined as that region where the collector current is
0 A, as revealed on Fig. c .
➢In the cutoff region the base–emitter and collector–base junctions of a transistor are both
reverse-biased.
➢The saturation region is defined as that region of the characteristics to the left of VCB = 0 V. The
horizontal scale in this region was expanded to clearly show the dramatic change in
characteristics in this region. Note the exponential increase in collector current as the voltage VCB
increases toward 0 V.
➢In the saturation region the base–emitter and collector–base junctions are forward-biased.

➢Hence from input and output characteristics, we can conclude that if transistor is in ‘ON’
state VBE = 0.7 V and there is sharp increase in the IE and hence from output characteristics if
IE is greater than zero the transistor works in active region

Ref. [2]
 Current amplification factor (α)
DC Mode: In the dc mode the levels of IC and IE due to the majority carriers are related by a
quantity called alpha (α) and defined by the following equation:

➢where IC and IE are the levels of current at the point of operation. Even though the
characteristics of Fig. b would suggest that α=1, for practical devices alpha typically extends from
0.90 to 0.998, with most values approaching the high end of the range
Since

Hence

Form the characteristics of Fig. b when IE = 0 mA, IC is therefore equal to ICBO ,

AC Mode: For ac situations where the point of operation moves on the characteristic curve,
an ac alpha is defined by

The ac alpha is formally called the common-base , short-circuit , amplification factor ,

Ref. [2]
 (ii) Common emitter (CE) configuration
➢The most frequently encountered transistor configuration appears in Fig.
a and b for the pnp and npn transistors. It is called the common-emitter
configuration because the emitter is common to both the input and
output terminals.
Input or driving point characteristics
➢Even though the transistor configuration has changed, the current
relations developed earlier for the common-base configuration are still
applicable. That is, IE = IC + IB and IC = αIE.
➢The input characteristics are a plot of the input current ( IB ) versus the input
voltage ( VBE ) for a range of values of output voltage ( VCE ). (a) npn tra.
➢The characteristic resembles
that of a forward biased diode
curve. This is expected since the
base-emitter section of transistor
is a diode and it is forward biased.
➢As compared to CB
arrangement, IB increases less
rapidly with VBE. Therefore, input
resistance of a CE circuit is higher
than that of CB circuit.

(b) pnp tra.

Ref. [2]
 Output or collector characteristics
➢For the common-emitter configuration the output characteristics are a
plot of the output current (IC) versus output voltage (VCE ) for a range of
values of input current (IB).
➢The collector current IC varies with VCE for VCE between 0 and 1V only.
After this, collector current becomes almost constant and independent of
VCE. This value of VCE upto which collector current IC changes with VCE is
called the knee voltage (Vknee). The transistors are always operated in the
region above knee voltage.
➢Above knee voltage, IC is almost constant.
However, a small increase in IC with
increasing VCE is caused by the collector
depletion layer getting wider and capturing a
few more majority carriers before electron-
hole combinations occur in the base area.
➢The active region for the common-emitter
configuration is that portion of the upper-right
quadrant that has the greatest linearity, that is, that
region in which the curves for IB are nearly straight
and equally spaced. In Fig. c this region exists to the
right of the vertical dashed line at VCEsat and above the
curve for IB equal to zero. The region to the left of
VCEsat is called the saturation region.

Fig. c
Ref. [2]
➢In the active region of a CE amplifier, the base–emitter junction is forward-biased, whereas the
collector–base junction is reverse-biased.
➢The active region of the CE configuration can be employed for voltage, current, or power
amplification.
➢The cutoff region, defined by IB ≤ 0mA, as for the CB configuration. Note on the collector
characteristics of Fig. C that IC is not equal to zero when IB is zero. For the CB configuration, when the
input current IE was equal to zero, the collector current was equal only to the reverse saturation
current ICO , so that the curve IE = 0 and the voltage axis were, for all practical purposes, one.

➢The reason for this difference in collector characteristics can be derived through the proper
manipulation of Eqs.

or

Rearranging yields

➢If we consider the case discussed above, where IB = 0A, and substitute a typical value
of α such as 0.996, the resulting collector current is the following:

If ICBO were 1 mA, the resulting collector current with IB = 0A would be 250 (1 mA)= 0.25A, as reflected
in the characteristics of Fig. c .

Ref. [2]
➢For future reference, the collector current defined by the condition IB = 0mA will be assigned
the notation indicated by the following equation:

➢As shown in the Fig., ICEO is known as collector to emitter current with open
base
Base current amplification factor ( β)
DC Mode: In the dc mode the levels of IC and IB are related by a quantity called beta ( β) and
defined by the following equation:

For practical devices the level of β typically ranges from about 50 to over 400, with most in the
midrange.
AC Mode: For ac situations an ac beta is defined as follows:

The formal name for β ac is common-emitter, forward-current , amplification factor

Ref. [2]
 Relationship between α and β
Using

or

recall that

but

derived from the above, we find that

Hence

Ref. [2]
 Common Collector (CC) Configuration
➢The common-collector configuration is used primarily for impedance-
matching (for driving a low impedance load from a high impedance
source) purposes since it has a high input impedance and low output
impedance, opposite to that of the common-base and common emitter
configurations.
➢For the input circuit of the common-collector configuration the common-
emitter base characteristics are sufficient for obtaining the required
information.
(a) pnp tra.
➢For all practical purposes, the output characteristics of the CC configuration
are the same as for the CE configuration. For the CC configuration the output
characteristics are a plot of IE versus VCE for a range of values of IB . The input
current, therefore, is the same for both the CE and CC characteristics. The
horizontal voltage axis for the CC configuration is obtained by simply changing
the sign of the CE voltage of the CE characteristics
Current amplification factor γ
The ratio of emitter current (IE) to the base current (IB) is known as
current amplification factor in CC arrangement i.e.

This circuit provides about the same current gain as the common emitter (a) npn tra.
circuit as IE ≈ IC. However, its voltage gain is always less than 1, because The
common collector circuit has very high input resistance (about 750 kΩ) and
very low output resistance (about 25 Ω)
Ref. [2]
 Relation between γ and α

Comparison of Transistor Connections

Ref. [2,3]
 Commonly Used Transistor Configuration
➢Out of the three transistor connections, the common emitter circuit is the most
efficient. It is used in about 90 to 95 per cent of all transistor applications. The main
reasons for the widespread use of this circuit arrangement are
1. High current gain: As the value of β is very large, therefore, the output current IC is much
more than the input current IB. Hence, the current gain in CE arrangement is very high. It
may range from 20 to 500.
2. High voltage and power gain: Due to high current gain, the common emitter circuit has
the highest voltage and power gain of three transistor connections. This is the major reason
for using the transistor in this circuit arrangement.

3. Moderate output to input impedance ratio: In a common emitter circuit, the ratio of
output impedance to input impedance is small (about 50). This makes this circuit
arrangement an ideal one for coupling between various transistor stages. However, in
other connections, the ratio of output impedance to input impedance is very large and
hence coupling becomes highly inefficient due to gross mismatching.

Ref. [2,3]
Problem: For the common base circuit shown in Fig., determine IC
and VCB. Assume the transistor to be of silicon.

Ref. [3]
Since the transistor is of silicon, VBE = 0.7V. Applying Kirchhoff’s voltage law to the emitter-
side loop, we get,

Ref. [3]
Problem: Determine VCB in the transistor circuit shown in Fig. The
transistor is of silicon and has β= 150.

Ref. [3]
Fig. shows the various currents and voltages along with polarities.
Applying Kirchhoff’s voltage law to base-emitter loop, we have

Note: Since VE = 0, VB = 0.7 V, and since VC-VB=2.85, hence, VC = 2.85+0.7 = 3.55 V, means
collector is at more potential than the base terminal, hence for npn trnasistor collector base
junction is reverse bias. Similarly base (VB = 0.7 V) is at higher potential than the emitter (VE =
0) terminal hence emitter base junction is forward bias. Hence in this circuit the transistor is
operating in active region

Ref. [3]
Problem

EMITTER-FOLLOWER CONFIGURATION

VBE = VB-VE
0.7 = VB-VE
VB = 0.7+VE
-20 + IERE = VE
VE = -20 + (4.16X2) = -11.68V
VB = 0.7-11.68 = -10.98V
Hence,
VC = 0, VE= -11.68 and VB = -10.98V

Hence, E-B terminal is FB and C-B terminal is RB

Ref. [2]
 Operating Point (Q –point)
➢Any increase in ac voltage, current, or power is the result of a transfer of energy from the applied
dc supplies
➢ For transistor amplifiers the resulting dc current and voltage establish an operating point on
the characteristics that define the region that will be employed for amplification of the applied
signal. Because the operating point is a fixed point on the characteristics, it is also called the
quiescent point (abbreviated Q -point). By definition, quiescent means quiet, still, inactive
➢Fig. shows a general output device characteristic with four operating points indicated.
➢Biasing circuit can be designed to set the
device operation at any of these points or
others within the active region.
➢The BJT device could be biased to operate
outside the indicated maximum limits, but
the result of such operation would be either
a considerable shortening of the lifetime of
the device or destruction of the device.
➢If no bias were used, the device would
initially be completely off, resulting in a Q -
point at A-namely, zero current through the
device (and zero voltage across it). Because
it is necessary to bias a device so that it can
respond to the entire range of an input
signal, point A would not be suitable.

Ref. [2]
➢For point B, if a signal is applied to the circuit, the device will vary in current and voltage from
the operating point, allowing the device to react to (and possibly amplify) both the positive and
negative excursions of the input signal. If the input signal is properly chosen, the voltage and
current of the device will vary, but not enough to drive the device into cutoff or saturation.
➢Point C would allow some positive and negative variation of the output signal, but the peak-
to-peak value would be limited by the proximity of VCE = 0 V and IC = 0mA. Operating at point C
also raises some concern about the nonlinearities introduced by the fact that the spacing
between IB curves is rapidly changing in this region. In general, it is preferable to operate where
the gain of the device is fairly constant (or linear) to ensure that the amplification over the
entire swing of input signal is the same.
➢Point D sets the device operating point near the
maximum voltage and power level. The output
voltage swing in the positive direction is thus limited
if the maximum voltage is not to be exceeded. Point
B therefore seems the best operating point in terms
of linear gain and largest possible voltage and
current swing.
➢This is usually the desired condition for small-signal
amplifiers but not the case necessarily for power
amplifiers. In this discussion, we will be concentrating
primarily on biasing the transistor for small-signal
amplification operation.

Ref. [2]
 Transistor biasing
➢Transistor biasing is used so that the transistor can work in active region and can stabilize
the operating point (Q-point (IC, VCE))
➢In any amplifier employing a transistor the collector current I C is sensitive to β, |VBE|and
Ico as all these three parameters change with the change of temperature as the results the IC
changes and hence there is change in the Q-point. The transistor biasing provides the
stability to Q-point so that transistor can work in active region and it can not go to the cut-off
or saturation region
Four types of biasing are used
1. Fixed-bias Configuration
2. Emitter-bias Configuration
3. Voltage-divider Bias Configuration or Self bias configuration
4. Collector Feedback Configuration
Note: In all types of biasing configuration we will be trying to find out the operating point i.e Q
point (IC, VCE))
• To find out the operating point we use the KVL at input and output sides and use the
general relationship of transistor
➢Here the dc analysis will be performed and later on we will do the ac analysis of the
configurations. Fortunately superposition theorem exist of the overall response of the transistor
➢For dc analysis isolate the ac input signal and consider the capacitor as an open circuit because
the impedance of capacitor for dc signal is infinite. As the capacitor is considered to be open circuit
the input ac signal will automatically be separated out.
Use the following relations during analysis

Ref. [2]
 1. Fixed-bias Configuration
➢The fixed-bias circuit of Fig. is the simplest transistor dc bias
configuration
Forward Bias of Base–Emitter
Consider first the base–emitter circuit loop of Fig. a .
Writing Kirchhoff’s voltage equation in the clockwise
direction for the loop, we obtain

Hence Fig a. Fixed bias circuit

Collector–Emitter Loop

Hence operating point is

ICQ = βIB
and VCEQ = VCC - ICQRC
Also we have the following relations to find out the voltages at various points

dc equivalent of Fig a.
since

Ref. [2]
 Transistor Saturation
➢For a transistor operating in the saturation region, the current is
a maximum value for the particular design
➢Saturation conditions are normally avoided because the base–
collector junction is no longer reverse-biased and the output
amplified signal will be distorted.
➢An operating point in the saturation region is depicted in Fig. 4.8a
. Note that it is in a region where the characteristic curves join and
the collector-to-emitter voltage is at or below VCEsat. Saturation region: (a) actual
➢If we approximate the curves of Fig. a by those appearing in Fig. b
, a quick, direct method for determining the saturation level
becomes apparent. In Fig. b , the current is relatively high, and the
voltage VCE is assumed to be 0 V.
➢For the future, therefore, if there were an immediate need to
know the approximate maximum collector current (saturation
level) for a particular design, simply insert a short circuit
equivalent between collector and emitter of the transistor and
calculate the resulting collector current.
Calculation of ICsat for fixed bias circuit Saturation regions: (b)
approximate

Determining ICsat for the

fixed-bias configuration.
Ref. [2]
 Load-Line Analysis
➢The characteristics of the BJT are superimposed on a plot of the network equation defined by the
same axis parameters. The load resistor RC for the fixed-bias configuration will define the slope of the
network equation and the resulting intersection between the two plots. The smaller the load
resistance, the steeper the slope of the network load line.
➢An output equation that relates the variables I C and VCE is given as

➢We must now superimpose the straight line defined by above Eq. on the
characteristics

Load-line analysis: (a) the network

➢By joining the two points defined by above Eqs. , we can

draw the straight line. The resulting line on the graph of
Fig. b is called the load line because it is defined by the
load resistor RC. By solving for the resulting level of IB , we
can establish the actual Q -point as shown in Fig. b.

Fig. b Fixed-bias load line

Ref. [2]
➢If the level of IB is changed by varying the value of RB , the Q -
point moves up or down the load line as shown in Fig. c for
increasing values of IB .
➢If VCC is held fixed and RC increased, the load line will shift
as shown in Fig. d . If IB is held fixed, the Q -point will
move as shown in the same fig. d.
➢If RC is fixed and VCC decreased, the load line shifts
as shown in Fig. e.
Fig. c Movement of the Q-point
with increasing level of IB .

Fig. e Effect of lower values of VCC on the load line

and the Q-point.

Fig. d Effect of an increasing level of

RC on the load line and the Q-point.

Ref. [2]
 2. Emitter-bias Configuration
➢ The dc bias network of Fig. a contains an emitter resistor to improve the stability level over that
of the fixed-bias configuration. The more stable a configuration, the less its response will change
due to undesirable changes in temperature and parameter variations.
Base–Emitter Loop
Writing Kirchhoff’s voltage law around the indicated loop in the
clockwise direction results in the following equation

Since
Substituting for IE

or
or

and solving for IB gives --------------------------------- (i) Fig. a: BJT bias circuit
with emitter resistor.
➢ Note that the only difference between this equation for IB and that
obtained for the fixed bias configuration is the term (β + 1)RE.
➢ There is an interesting result that can be derived from Eq (i). if the
equation is used to sketch a series network that would result in the
same equation. Such is the case for the network of Fig. b . Solving
for the current IB results in the same equation as obtained above.
Note that aside from the base-to-emitter voltage VBE, the resistor
RE is reflected back to the input base circuit by a factor (β + 1). In
other words, the emitter resistor, which is part of the collector–
emitter loop, “appears as” (β + 1)RE in the base–emitter loop. Fig.b: Network derived
from Eq. (1).
In general, therefore, for the configuration of Fig. a
Ref. [2]
Collector–Emitter Loop
Writing Kirchhoff’s voltage law for the indicated loop in the clockwise
direction results in

------------------(ii)
Hence operating point is
ICQ = βIB Taking IB From Eq. (i)
VCEQ = VCC – ICQ (RC + RE ) From Eq. (ii)
The single-subscript voltages are determined by

or

or
Saturation Level
Apply a short circuit between the collector–emitter terminals as shown in Fig. and
calculate the resulting collector current.
𝑉𝑐𝑐 − 𝐼𝐶𝑠𝑎𝑡 𝑅𝑐 − 𝐼𝐸 𝑅𝐸 = 0
We have
The addition of the emitter resistor reduces the collector saturation level Determining ICsat for the
below that obtained with a fixed-bias configuration using the same emitter stabilized bias circuit
collector resistor Ref. [2]
 Load-Line Analysis
➢ The load-line analysis of the emitter-bias network is only slightly different from that encountered
for the fixed-bias configuration. The level of IB as determined by Eq. (i) defines the level of IB on
the characteristics of Fig. a (denoted IBQ).
➢ The collector–emitter loop equation that defines the load line is

Choosing IC = 0 mA gives

Choosing VCE = 0 V gives

As shown in Fig. a. Different levels of IBQ will, of course, move the Q -

point up or down the load line. Fig. a: Load line for the emitter-
bias configuration .

Ref. [2]
 3. Voltage-divider Bias Configuration or Self bias configuration
➢In the previous bias configurations the bias current ICQ and voltage V CEQ were a function of the
current gain β of the transistor. However, because β is temperature sensitive, especially for silicon
transistors, and the actual value of beta is usually not well defined, it would be desirable to develop a
bias circuit that is less dependent on, or in fact is independent of, the transistor beta.
➢The voltage-divider bias configuration of Fig. a is such a network. If analyzed on an exact
basis, the sensitivity to changes in beta is quite small. If the circuit parameters are
properly chosen, the resulting levels of ICQ and VCEQ can be almost totally independent of
beta.
➢There are two methods that can be applied to analyze the voltage-
divider configuration.
1. Exact method: This can be applied to any voltage-
divider configuration.
2. Approximate method: This can be applied only if specific
conditions are satisfied
Fig.a: Voltage-divider bias
The approximate approach permits a more direct analysis configuration
with a savings in time and energy.

Ref. [2]
 1. Exact method
➢For the dc analysis the network of Fig. a can be redrawn as shown in Fig. b
➢The input side of the network can then be redrawn as shown in Fig. c for
the dc analysis
➢The Thévenin equivalent network for the network to the left of the
base terminal can then be found in the following manner:
➢RTh The voltage source is replaced by a short-circuit equivalent
Fig. b: DC components of the
voltage divider configuration.

➢ETh The voltage source VCC is returned to the network and the open-
circuit Thévenin voltage of Fig. determined as follows:

➢The Thévenin network is then redrawn as shown in

Fig. d Fig. c: Redrawing the input
Substituting IE = (β + 1)IB and solving for IB yields side of the network of Fig. b

From the collector to emitter loop

Hence operating point is ICQ = βIB

VCEQ = VCC – ICQ (RC + RE ) Fig.d: Thévenin
The remaining equations for VE, VC, and VB are same as obtained for the emitter- Equivalent model
bias configuration Ref. [2]
 2. Approximate method:
➢The input section of the voltage-divider configuration can be represented by the network of Fig. a.
The reflected resistance Ri = (β + 1)RE is the equivalent resistance between base and ground for the
transistor with an emitter resistor RE (as discussed in emitter bias configuration) .
➢If Ri is much larger than the resistance R2 , the current IB will
be much smaller than I2 and I2 will be approximately equal to I1 .
➢If we accept the approximation that IB is essentially 0 A
compared to I1 or I2 , then I 1 = I2, and R 1 and R2 can be
considered series elements.
➢The voltage across R2 , which is actually the base voltage, can
be determined using the voltage-divider rule

Fig. circuit for calculating the

➢Because Ri = (β + 1)RE ≈ βRE the condition that will define whether approximate base voltage VB
the approximate approach can be applied is

Once VB is determined, the level of V E can be calculated from

and the emitter current can be determined from But because IE ≈ IC

and The Q -point (as determined by ICQ and

VCEQ) is independent of the value of β.
The collector-to-emitter voltage is determined by

Ref. [2]
 Transistor Saturation
➢The output collector–emitter circuit for the voltage-divider configuration has the
same appearance as the emitter-biased circuit analyzed in earlier
➢The resulting equation for the saturation current is therefore

Load-Line Analysis
➢The similarities with the output circuit of the emitter-biased configuration result in
the same intersections for the load line of the voltage-divider configuration.

and

Ref. [2]
 4. Collector Feedback Configuration
➢An improved level of stability can also be obtained by introducing a feedback path from
collector to base as shown in a. Although the Q -point is not totally independent of beta (even
under approximate conditions), the sensitivity to changes in beta or temperature variations is
normally less than encountered for the fixed-bias or emitter-biased configurations.
Base–Emitter Loop

IB is neglected

or

and solving for IB yields

Fig.a: DC bias circuit with
Collector–Emitter Loop voltage feedback.

Hence operating point is

ICQ = βIB
VCEQ = VCC – ICQ (RC + RE )

Fig.b: Base–emitter loop

for the network of Fig. a
Ref. [2]
 Saturation Conditions
Using the approximation ,we find that the equation for the saturation current
is the same as obtained for the voltage-divider and emitter-bias configurations

Load-Line Analysis

➢Continuing with the approximation results in the same load line defined for the voltage-
divider and emitter-biased configurations. The level of IBQ is defined by the chosen bias
configuration.

and

Ref. [2]
Problem: Determine the following for the fixed-bias configuration of Fig.

e. Determine the saturation level for the network

Ref. [2]
With the negative sign revealing that the junction is reversed-biased, as it
should be for linear amplification.

Ref. [2]
Problem: For the emitter-bias network of Fig. determine

Ref. [2]
Ref. [2]
Problem: (a) Draw the load line for the network of Fig. a on the characteristics for the
transistor appearing in Fig. b .
b. For a Q -point at the intersection of the load line with a base current of 15 µ A ,
find the values of ICQ and VCEQ.
c. Determine the dc beta at the Q -point.
d. Using the beta for the network determined in part c, calculate the required value
of RB.

Fig. a Fig. b

Ref. [2]
The resulting load line appears in Fig. c
From the characteristics of Fig. c we find

Fig. c

Ref. [2]
Problem: Determine the dc bias voltage VCE and the
current IC for the voltage divider configuration of Fig. a

1. Exact Analysis
2. Approximate analysis

Ref. [2]
1. Exact Analysis

2. Approximate analysis

Ref. [2]
Problem: Determine the quiescent levels of ICQ and VCEQ for the network of Fig.

Ref. [2]
Ref. [2]
 BJT AC Analysis
➢ Transistor can be employed as an amplifying device. That is, the output sinusoidal signal is greater
than the input sinusoidal signal, or, stated another way, the output ac power is greater than the input
➢ ac
Thepower.
question then arises as to how the ac power output can be greater than the input ac power.
Conservation of energy dictates that over time the total power output, Po , of a system cannot be
𝑃
greater than its power input, Pi, and that the efficiency defined by 𝜂 = 0 cannot be greater than 1.
𝑝𝑖
The factor missing from the discussion above that permits an ac power output greater than the input
ac power is the applied dc power. It is the principal contributor to the total output power even
though part of it is dissipated by the device and resistive elements.
➢ In other words, there is an “exchange”BJT AC power
of dc Analysisto the ac domain that permits establishing a
𝑃0(𝑎𝑐)
higher output ac power. In fact, a conversion efficiency is defined by 𝜂 = , where 𝑃0(𝑎𝑐) is the
𝑝𝑖 (𝑑𝑐)
ac power to the load and 𝑝𝑖 (𝑑𝑐) is the dc power supplied. So, conversion efficiency is the measure of
how much dc supplied power is converted to the ac power and hence its value will always be less
The
thansuperposition
unity. theorem is applicable for the analysis and design of the dc and ac
components of a BJT network, permitting the separation of the analysis of the dc
and ac responses of the system.

Ref. [2]
 BJT Transistor Modeling
➢ The key to transistor small-signal analysis is the use of the equivalent circuits (models)
➢ A model is a combination of circuit elements, properly chosen, that best approximates the actual
behavior of a semiconductor device under specific operating conditions.
➢ Once the ac equivalent circuit is determined, the schematic symbol for the device can be replaced by
this equivalent circuit and the basic methods of circuit analysis applied to determine the desired
quantities of the network.
➢ In the formative years of transistor network analysis the hybrid equivalent network is employed the
most frequently
➢ The drawback to using this equivalent circuit, however, is that it is defined for a set of operating
conditions that might not match the actual operating conditions. In most cases, this is not a serious
flaw because the actual operating conditions are relatively close to the chosen operating conditions
➢ on the data
Because wesheets.
are interested only in the ac response of the circuit, all the dc supplies can be replaced
by a zero-potential equivalent (short circuit) because they determine only the dc (quiescent level)
of the output voltage and not the magnitude of the swing of the ac output. This is clearly
demonstrated by Fig. a. The dc levels were simply important for determining the proper Q -point of
operation. Once determined, the dc levels can be ignored in the ac analysis of the network. In
addition, the coupling capacitors C1 and C2 and bypass capacitor C3 were chosen to have a very
small reactance at the frequency of application. Therefore, they, too, may for all practical purposes
be replaced by a low-resistance path or a short circuit. Note that this will result in the “shorting out”
of the dc biasing resistor RE . Recall that capacitors assume an “open-circuit” equivalent under dc Ref. [2]
steady-state conditions, permitting an isolation between stages for the dc levels and quiescent
conditions.
 Fig. b: The network of Fig. a following removal of
the dc
Fig. a: Transistor circuit under examination supply and insertion of the short-circuit equivalent
for the capacitors.
➢ If we establish a common ground and rearrange the
elements of Fig. b , R1 and R2 will be in parallel, and RC
will appear from collector to emitter as shown in Fig. c
➢ Now we will study transistor small-signal ac
equivalent circuit i.e h-parameters equivalent circuit
of the transistor

Ref. [2] Fig. c: Circuit of Fig. b redrawn for small-signal ac anal

 Definition of Various Parameters
➢ The small signal analysis is used to mainly find out the input impedance, Zi, output impedance Zo,
voltage gain Av and current gain Ai
➢ To determine the all these above mentioned parameters, we consider the following two port
network shown in Fig. a
➢ For all the analysis, we will consider the directions of the currents, the
polarities of the voltages, and the direction of interest for the
impedance levels as appearing in Fig. a .
➢ For Example, if I had been defined as the opposite direction in Fig.
o

a, a minus sign would have to be applied Fig. a Defining the

𝑽𝒊 important
➢ Input Impedance 𝒁𝒊 =
𝑰𝒊
𝑽𝟎 Considering source voltage to zero and
Parameters of any system.
➢ output Impedance 𝒁𝟎 =
𝑰𝟎 load impedance to infinite

𝑽𝟎
➢ V𝐨𝐥𝐭𝐚𝐠𝐞 𝐠𝐚𝐢𝐧 𝑨𝒗 =
𝑽𝒊
𝑰
➢ C𝐮𝐫𝐫𝐞𝐧𝐭 𝐠𝐚𝐢𝐧 𝑨𝒊 = − 𝟎 Fig. b: Demonstrating the reason
𝑰𝒊
for
the defined directions and
polarities.
Ref. [2]
 The Hybrid Equivalent Model (h-parameters model)
➢ The description of the hybrid equivalent model will begin with the general two-port system of Fig. a.
The following set of equations (I) and (II) is only one of a number of ways in which the four variables
of Fig. a can be related.
𝑉1 = ℎ11 𝑖1+ℎ12 𝑉2 −−−−−−−−− −(𝑖)
𝑖2 = ℎ21 𝑖1+ℎ22𝑉2 −−−−−−−−− −(𝑖𝑖)

➢ The parameters relating the four variables are called h-

parameters , from the word “hybrid.” The term hybrid
was chosen because the mixture of variables ( V and I ) in Fig. a Two-port system.
each equation results in a “hybrid” set of units of
measurement for the h -parameters
➢ We can write the following two equations of h-parameters in matrix form as

𝑉1 ℎ ℎ12 𝑖1
= 11
𝑖2 ℎ21 ℎ22 𝑉2

Ref. [2]
 ➢ Setting 𝑉2 = 0 and 𝑖1 = 0 the h-parameters can be calculated as follows
𝑉1
ℎ11 = ቚ ohms Short circuit Input Impedance parameter (𝒉𝒊)
𝑖1 𝑉 =0
2

𝑉1
ℎ12 = ቚ Unitless Open circuit reverse transfer voltage ratio parameter (𝒉𝒓)
𝑉2 𝑖 =0
1

𝑖
ℎ21 = 2ቚ Unitless Short circuit forward transfer current ratio parameter (𝒉𝒇)
𝑖1 𝑉 =0
2

𝑖
ℎ22 = 2 ቚ Siemens Open circuit output admittance parameter (𝒉𝟎)
𝑉2 𝑖 =0
1
Now consider the equation (i): Because each term of Eq. (i) has the unit volt, let us apply
Kirchhoff’s voltage law “in reverse” to find a circuit that “fits” the equation. Performing this
operation results in the circuit of Fig. a
𝑉1 = ℎ11 𝑖1+ℎ12 𝑉2 −−−−−−−−− −(𝑖)

𝒉𝟏𝟐 𝑽𝟐 is the voltage controlled voltage

source

Ref. [2] Fig. a: Hybrid input equivalent circuit

 Next consider the equation (ii): Because each term of Eq. (ii) has the units of current, let us now apply Kirchhoff’s
current law “in reverse” to obtain the circuit of Fig. b.
𝑖2 = ℎ21 𝑖1+ℎ22𝑉2 −−−−−−−−− −(𝑖𝑖)
𝒉𝟐𝟏 𝒊𝟏 is the current controlled current source
➢ The complete “ac” equivalent circuit for the basic three-terminal linear
device is indicated in Fig. c with a new set of subscripts for the h -
parameters
The choice of letters is obvious from the following listing
Fig. b: Hybrid output equivalent circu

𝐴𝑙𝑠𝑜 𝑉1 → 𝑉𝑖
𝑉2 → 𝑉0
𝐼1 → 𝐼𝑖
𝑎𝑛𝑑 𝐼2 → 𝐼0
Fig. c: Complete hybrid equivalent circuit.

Ref. [2]
 h-parameters for various BJT configurations
1. CE Configuration
➢ For the transistor, therefore, even
though it has three basic
configurations, they are all three-
terminal configurations, so that the
resulting equivalent circuit will have
the same format as shown in Fig. c.
therefore, the transistor model is a Fig. d
three-terminal two-port system.
➢ The h -parameters, however, will change with each configuration. To distinguish which parameter has been
used or which is available, a second subscript has been added to the h -parameter notation. For the
common-base configuration, the lowercase letter b was added, whereas for the common-emitter and
common- collector configurations, the letters e and c were added, respectively
➢ The hybrid equivalent network for the common-emitter configuration appears with the standard notation
in Fig. c. Note that Ii = Ib, Io = Ic, and, through an application of Kirchhoff’s current law, Ie = Ib + Ic. The input
voltage is now Vbe , with the output voltage Vce. For the common-base configuration of Fig.e , Ii = Ie, Io = Ic
with Veb = Vi and Vcb = Vo. The networks of Figs. c and d are applicable for pnp or npn transistors.

Ref. [2]
2. CB Configuration
➢ Using the similar procedure as used
for CE configuration we can draw the
h-parameter equivalent network as
shown in Fig. e

Fig. e
3. CC Configuration
➢ Following the similar procedure of CE and CB configurations we can draw the h-parameter equivalent
network for CC configuration as shown in Fig. f

Fig. f

Ref. [2]
 Typical h-parameters Values
➢ Typical h-parameters Values for 𝑰𝒆 = 𝟏. 𝟑𝒎𝑨 and at room temperature are given as follows
Parameters CE CB CC Relationships
1. h fe + h fc = −1
2 h ic = h ie
.
50 -0.98 -51 3. hrc = 1
4. hoc = hoe

➢ For the common-emitter and common-base configurations, the magnitude of hr and ho is often
such that the results obtained for the important parameters such as Zi , Zo , Av , and Ai are only
slightly affected if hr and ho are not included in the model. So approximate CE equivalent h-
parameter model can be drawn as follows

Fig: Approximate h-parameter model for CE Ref. [1,2]

conf.
 Analysis of a Transistor Amplifier Circuit using h-parameters

The quantities of interest are:

1. Current gain: 𝐴𝐼 𝑎𝑛𝑑𝐴𝐼𝑠
2. Input impedance: 𝑍𝑖
3. Voltage gain: 𝐴𝑉 𝑎𝑛𝑑 𝐴𝑉𝑠
4. Output impedance: 𝑍0
1. Current Gain or Current Amplification
AI is defined as the ratio of o/p to i/p
currents Fig. a: A basic Amplifier Circuit
𝐼𝐿 𝐼2
𝐴𝐼 = = −
𝐼1 𝐼1
From the circuit of Fig. b we have,
𝐼2 = ℎ𝑓 𝐼1 + ℎ0 𝑉2
𝑉2 = −𝐼2 𝑍𝐿
𝐼2 = ℎ𝑓 𝐼1 −𝐼2𝑍𝐿 ℎ0 Fig. b: The transistor in Fig. a is
replace by its h-parameter model
𝐼2 ℎ𝑓
Hence 𝐴𝐼 = − =− Current gain
𝐼1 1+ℎ0 𝑍𝐿

Ref. [1]
 2. Input Impedance
➢ The resistance 𝑅𝑠in Fig represents the signal source
resistance. The impedance we see looking into the
amplifier input terminals (1 1’) is the amplifier input
impedance Zi or 𝑉1
𝑍𝑖 =
𝐼1
𝑉1 = ℎ𝑖 𝐼1 + ℎ𝑟 𝑉2
ℎ𝑖 𝐼1 + ℎ𝑟 𝑉2 𝑉2
𝑍𝑖 = = ℎ𝑖 + ℎ𝑟
𝐼1 𝐼1
𝑉2 = −𝐼2 𝑍𝐿 = 𝐴𝐼 𝐼1𝑍𝐿
Hence
ℎ𝑓 ℎ𝑟 𝐼2 ℎ𝑓
𝑍𝑖 = ℎ𝑖 + ℎ𝑟 𝐴𝐼 𝑍𝐿 = ℎ𝑖 − 𝐴 𝐼 = − = −
𝑌𝐿 + ℎ0 𝐼1 1 + ℎ0 𝑍𝐿
ℎ𝑓 ℎ𝑟 1
Hence 𝑍𝑖 = ℎ𝑖 − Where, 𝑌𝐿 =
𝑌𝐿 + ℎ0 𝑍𝐿

Ref. [1]
 3. Voltage gain: 𝑨𝑽 𝒂𝒏𝒅 𝑨𝑽𝒔
➢ The ratio of output voltage V2 to the input voltage V1 gives the voltage gain of the transistor
𝑉2
𝐴𝑉 =
𝑉1
𝑉2 = −𝐼2 𝑍𝐿 = 𝐴𝐼 𝐼1 𝑍𝐿
𝐴𝐼 𝐼1 𝑍𝐿 𝐴𝐼 𝑍𝐿
𝐴𝑉 = =
𝑉1 𝑍𝑖
𝐴𝐼 𝑍𝐿
Hence 𝐴𝑉 =
𝑍𝑖
➢ The voltage amplification 𝑨𝑽𝒔 taking into account the source resistance
𝑅𝑠overall
The : voltage gain 𝐴𝑉𝑠 is defined by
𝑉2 𝑉2 𝑉1 𝑉1
𝑨𝑽𝒔 = = × = 𝐴𝑉 ×
𝑉𝑠 𝑉1 𝑉𝑠 𝑉𝑠
From the equivalent I/p circuit of the fig. shown Thevenin’s Model
we have 𝑉 𝑍 𝑉1 𝑍𝑖
𝑠 𝑖
𝑉1 = ⇒ =
𝑍𝑖 + 𝑅𝑠 𝑉𝑠 𝑍𝑖 + 𝑅𝑠
𝐴𝑉 𝑍𝑖 𝐴𝐼 𝑍𝐿 𝐴𝐼 𝑍𝐿
𝑨𝑽𝒔 = = 𝑠𝑖𝑛𝑐𝑒 𝐴𝑉 =
𝑍𝑖 + 𝑅𝑠 𝑍𝑖 + 𝑅𝑠 𝑍𝑖
Ref. [1]
Norton model
 4. Current Amplification AIs taking in to account the source R s
resistance
If the i/p source is a current generator Is in parallel with the resistance Rs as indicated in the previous
A Is
slide, then the overall current gain is define as
I2 I I I
A Is = − = − 2  1 = AI 1
Is I1 Is Is
From the previous Fig. we can find I1 as
I s Rs I Rs
I1 =  1 =
Z i + Rs I s Z i + Rs
AI Rs
Hence, AIs =
Z i + Rs
Hence we can say that independent of the transistor characteristics, the voltage and current gains taking
source impedance into account, are related by
Z 𝐴𝑉 𝑍𝑖 𝐴𝐼 𝑍𝐿
AVs = AIs L Since 𝑨𝑽𝒔 =
𝑍𝑖 +𝑅𝑠
=
𝑍𝑖 +𝑅𝑠
Rs
Valid provided that voltage and current generators have the same source resistance
Rs
Norton model

Ref. [1]
5. Output impedance or admittance
1
By definition the output Z =
Y0 Is obtained by setting the source
0 Vs to zero
impedance
And the load impedanceZ L to infinite voltage
I2
Y0 = with Vs = 0 and RL = 
V2
Since I 2 = h f I1 + h0V2
I2 I
Y0 = = h f 1 + h0
V2 V2
With Vs = 0
Rs I1 + hi I1 + hrV2 = 0 ( From the input side)
I1 hr
=−
V2 hi + Rs
h f hr
Y0 = h0 −
hi + Rs

Ref. [1]
 Fixed-Bias Configuration
For the fixed-bias configuration of Fig. a , the small-signal ac equivalent network will appear as shown in
Fig. b using the approximate common-emitter hybrid equivalent model.

Ref. [2]
 Since input and output are
completely separated to each other.
Also the same can be calculated by
Vi Vi
Ii = + just using the KCL at the input side to
RB hie
obtain the ratio of Vi/Ii
Ii 1 1 1
Hence = + = Fig. b
Vi RB hie Z i
Recall that the output impedance of any system is defined as
the impedance Zo determined when Vi = 0. For Fig. b , when
Vi = 0, Ii = Ib = 0, resulting in an open circuit equivalence for Fig. c
the current source.
𝐴𝐼 𝑍𝐿 ℎ𝑓 ℎ𝑟
𝐴𝑉 = 𝑍𝑖 = ℎ𝑖 −
𝑍𝑖 𝑌𝐿 + ℎ0 ℎ𝑓
Put 𝑍𝐿 = 𝑅𝑐 and ℎ𝑟 = 0So,𝑍𝑖 = ℎ𝑖 and 𝐴𝐼 = −
1+ℎ0 𝑅𝐶
Hence 𝐴𝑣 =
𝑅𝑐ℎ𝑓
Now ,use the subscript ‘e’ because of
− CE
Assuming
(1+𝑅𝑐ℎ𝑜)ℎthat
𝑖 R >>h and 1/h ≥ 10R , we find 𝐼𝑏 ≈ 𝐼𝑖 and
B ie oe C

𝐼0 = 𝐼𝑐 = ℎ𝑓𝑒 𝐼𝑏 = ℎ𝑓𝑒 𝐼𝑖 , and so

The same 𝑅𝑐 ℎ𝑓𝑒

= expression
− we can verify from the Ref. [2]
(1 + 𝑅derived
earlier expressions 𝑐 ℎ𝑜𝑒 )ℎ𝑖𝑒
for general case
Problem: For the network of Fig. a, determine:

Ref. [2]
Ref. [2]
 Voltage-Divider Configuration
For the voltage divider-bias configuration of Fig. a , the small-signal ac equivalent network will appear as
shown in Fig. b using the approximate common-emitter hybrid equivalent model

Fig. a

Ref. [2]
 For the voltage-divider bias configuration of Fig. a , the resulting small-signal ac equivalent network
will have the same appearance as Fig of foxed bias configuration, with R replaced by R’ = R ||R .
B 1 2

Negative sign in the gain signifies that output

signal is 180 degree out of phase to that of input
signal I I i R' If 1/hoe >>Rc
Ai = 0 h fe I 0 = h fe I b
Ii R'+ hie h fe I i R'
I0 = =
1 Rc hoe + 1 ( Rc hoe + 1)( R'+ hie ) I = I i R '
h fe I b R '+ h ie
b
h oe h fe I b h fe R'
I0 = = Ai = h fe I i R '
Rc +
1 R c h oe + 1 ( Rc hoe + 1)( R'+ hie ) I0 =
h oe R '+ h ie
Exact expression which
IiR ' Ai =
h fe R ' As written
Ib = can also be verified R '+ h ie on LHS
R ' + h ie from general analysis
Ref. [2]
 Common-Base Configuration
➢The CB configuration to be examined with the approximate hybrid equivalent circuit is shown in Fig. a.

Ref. [2]
If RE >> hib

Ref. [1]