SN Computer Science (2024) 5:457

[Link]

ORIGINAL RESEARCH

Design and Analysis of Low Power Approximate Multiplier Using Novel

Compressor
Garima Thakur1 · Harsh Sohal2 · Shruti Jain2

Received: 17 March 2023 / Accepted: 19 February 2024

© The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd. 2024

Abstract
The multiplier is one of the most essential arithmetic blocks in computer architecture, as it has an impact on the system’s
overall performance. Approximate computing help in improving multiplier performance with low power consumption at the
expense of computing precision. In this paper, approximate novel compressors are proposed and further used for the imple-
mentation of the proposed approximate multiplier. In the multiplication, process compressors are used for the reduction of
partial products with low consumption of power. In comparison to the exact multiplier, the proposed multiplier shows efficient
results in terms of Look-up tables, area, memory utilization, and power consumption. The validation of the approximate
multiplier is done in an error-tolerant application. In this paper, validation is done in an image processing application for
image blending which results in 23.87 dB and 22.7 PSNR values for set 1 and set 2 respectively.

Keywords Approximate compressor · Approximate multiplier · Error-resilient application · System generator ·

Approximate computing

Introduction One of the most difficult issues in designing digital cir-

cuits is lowering energy usage [11]. Several techniques for
Arithmetic circuits, such as adders and multipliers play a reducing power and energy consumption in digital circuits
crucial role in the operational efficiency of many digital have been proposed [12, 13]. Approximate computing is
circuits [1, 2]. Adders and multipliers increase the compu- a new paradigm that is being employed in error-tolerant
tational speed of the digital circuits and consume the maxi- applications [15, 16]. The goal of approximation comput-
mum amount of circuit power. Among the arithmetic units ing is to design a system that is low-power and high-speed
such as addition, subtraction, division, and so on, multipli- [17]. There are system, circuit, storage and software levels
cation is a more complex and particularly important opera- of abstraction in the approximation computing proposed
tion [3]. The multiplication block affects most of the power study. These levels range from a low level of abstraction
consumption of the whole circuits and systems in which it is (circuit level) to a high abstraction level (system level) [18,
present [4, 5]. Numerous applications use the multiplication 19]. Although a trade-off between power and delay is fre-
block for computation [6–10]. quent in computing circuit designs, a successful design in
the field of approximate computing also necessitates a bal-
ance of quality and efficiency [20, 21]. The first stage is to
create partial products, the second stage is to accumulate
This article is part of the topical collection “AI Based Internet of the partial products, and the final stage is to use an adder
Healthcare: Analysis and Future Perspectives” guest edited by to obtain the final result. The second stage of a multiplier
Diganta Sengupta, Debashis De and Prasenjit Bhadra.
requires the more area utilization and power because the
* Garima Thakur longer the operand length of the inputs, the more additions
garimathakur1994@[Link] are necessary [22–24]. The second stage that is reduction
of partial products is the most important block for the con-
1
Department of ECE, Chandigarh University, Gharuan, tribution of the overall delay of the circuit. So, researchers
Punjab, India
are trying to optimize this stage for the better performance
2
Department of ECE, Jaypee University of Information of the circuit [25, 26]. The Wallace multiplier algorithm
Technology, Solan, H.P, India

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made a substantial contribution to achieving delay-optimized hardware resources as well as processing time. Multipliers
structures in the accumulation stage [27]. By using compres- are implemented in VLSI with three key considerations:
sors in the reduction stage of partial products, delay can be power, latency, and area. Multiplication’s fundamental oper-
further reduced but optimization of power is still a major ations may be broken down into three steps: The first step
concern. So, for the optimization of power consumption, the is to generate partial products by multiplying the multipli-
approximation is applied in the reduction stage of the partial cand and multiplier together. The following phase might be
product. Several new metrics are proposed and a comparison thought of as the reduction of partial products. The third and
is made among some of the adder designs [3]. An approxi- last phase will be the addition with carry propagation. The
mate multiplier is proposed by authors in [11], in which reduction of partial products in line with the conditions of
a trade-off between energy and accuracy is maintained for power and delay plays a vital role. Approximate computing
DSP and recognition applications. An efficient multiplier is plays an important role in the reduction of power consump-
implemented with the help of a Parallel Prefix Adder (PPA) tion in the multiplication process. In this paper approximate
[22]. PPA increases the overall efficiency of the multiplier multiplier is implemented with the help of a multiplier using
structure which is further used for high-speed applications. It the compressor and approximated parallel prefix adder. The
is important to design an efficient adder [23] and multiplier, proposed methodology is shown in Fig. 1. This methodol-
for applications where these parameters are basic building ogy is used for the validation of the proposed approximated
blocks [24]. Some applications are error-tolerant such as multiplier, in image blending technique.
image/signal processing and to improve the functionality
approximate circuits are used [25]. The approximation can Compressor
increase the speed of the circuit while reducing the chip area.
In the multiplication process the final addition of the The inputs are equally weighted in the compressor, and binary
partial products is done using adders. As adders plays a output is obtained. The goal of simultaneous multi-operand
significant role in the multiplication process, it's important addition and multiplication is to minimize the number n, which
to boost adder performance. The approximate Han-Carlson necessitates the use of n: 2 compressors (n is the number of
adder [28] is used to improve performance at the expense
of precision. In this paper the power-optimized circuit is
implemented by using approximate compressors at the
reduction stage of the multiplier block. Proposed approxi-
mated multiplier designs consist of speculation parallel-pre-
fix adder and multiplier using the compressor. By applying
approximation, power consumption is reduced but it affects
the accuracy of the circuit. For the validation of results, the
proposed approximated multiplier is used in blending/fusing
two images using the Xilinx system generator. The analy-
ses show that the proposed compressors and multiplier are
capable of approximate computing.
The structure of the paper is as follows: The methodology
and analysis of approximate compressors and multipliers
are shown in Section "Materials and methodology". Section
"Results and Discussion" shows the results and discussion of
the approximated designs. Image processing application by
using system generator is shown in Section "Image Process-
ing Application Using System Generator" which is followed
by the conclusion.

Materials and methodology

Multiplication is a power-intensive process that is an impor-

tant part of the arithmetic unit. A typical CPU devotes a
significant amount of time to execute the arithmetic unit's
of multiplication operation. When compared to addition
and subtraction, multiplication demands significantly more Fig. 1  Proposed methodology for approximate multiplier

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inputs). The schematic diagram of the n: 2 compressors for

the addition of multi-operand is shown in Fig. 2. The inequal-
ity must be met for the circuit depicted in Fig. 2 to operate
effectively (1).
n + 𝜓1 + 𝜓2 + 𝜓3 + … ≤ 2 + 2𝜓1 + 4𝜓2 + 8𝜓3 + … (1)
where ψj is the number of carry bits from slice i to i + j.
In this paper, approximate novel compressors (3:2, 4:2) are
proposed and simulated. After simulation different param-
eters are calculated that include cell usage, area, memory,
power, and junction temperature. Approximate compressors
play a vital role in the multiplication process; it helps in the
reduction of partial product and enhances the performance of
multiplication.

Approximate 3:2 Compressor

The addition of the exact 3:2 compressor is faster than the rip-
ple carry adder but has an irregular structure which increases
its complexity. To overcome this problem approximate 3:2
compressor is proposed and the final sum and carry are calcu-
lated by using (2) and (3). Figure 3(a) and (b) shows the actual
and approximate 3:2 compressor.
sum = ((x3 + x1) ⊕ x2) (2)

carry = ((x3 + x1).x2) (3)

Fig. 3  a Actual and b Approximate 3:2 compressor

The proposed approximated 3:2 compressor provides a sim-
ple layout with reduced delay, power consumption, and area,
as compared to the exact 3:2 compressor.
cout = (x1 ⊕ x2) + (x2 ⊕ x3) + (x3 ⊕ x1) (5)
Approximate 4–2 Compressor ( ) ( )
carry = (x1 ⊕ x2 ⊕ x3 ⊕ x4) + x4 ⊕ cin + cin ⊕ x1 ⊕ x2 ⊕ x3
The exact 4:2 compressor consists of two full adders (FAs) (6)
with five inputs and three outputs, also known as (5,3) coun- The sum has the same weight as of input 1 while cout
ter. Its input includes × 1, × 2, × 3, × 4, and cin, while outputs and carry consists weight of 2. The exact 4:2 compressor
include sum, carry, and cout and is expressed by (4), (5), and requires a large area for its implementation which increases
(6) respectively. the complexity of the circuit and consumes more power.
To overcome this problem approximate 4:2 compressor is
sum = x1 ⊕ x2 ⊕ x3 ⊕ x4 ⊕ cin (4)

Fig. 2  Schematic diagram of n:

2 compressors

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proposed using (7) and (8). Figure 4(a), (b) shows the actual group with fewer than three rows is carried to the next stage
and approximate 4:2 compressor. of addition without being changed. A Wallace tree multi-
plier of 8 × 8 is shown in Fig. 5. There are five phases in all.
sum = (x3 + x2 + x1) ⊕ x4 (7) Stage 0 allows for two groups of three rows, with two rows
remaining unchanged. In stage 1, the remaining two rows
carry = ((x4 + x3).(x2 + x1)) + (x4.x3) + (x2.x1) (8) form a group. A typical adder is used to accomplish the final
addition in the last step.
A novel approximated compressor algorithm is proposed
with some inaccurate results. In the multiplication process,
Proposed Multiplier
compressors play a critical role. In the reduction process of
The purpose of this section is to demonstrate how to use
multiplication, the compressor serves as the main compo-
the suggested speculative Han-Carlson parallel prefix adder
nent. They efficiently reduce partial products and enhance
and multiplier using an approximate compressor for the
the performance of the multiplier.
implementation of the approximate multiplier. There are
three primary steps in parallel multipliers. The formation
Multiplier
of partial products is the first stage, which is carried out by
AND gates. The second stage is the reduction of the partial
In this research paper, authors used Wallace multiplier. It
products which can be done by using approximate novel
differs from an array multiplier, though, in that it sums up all
compressors. The final addition of the partial products is
partial products. The addition of all partial products occurs
done using approximate Han-Carlson parallel prefix adder
at numerous stages in the Wallace tree multiplier. At every
[28], in the third stage. The second stage, out of the three,
level, parallel addition takes conducted by forming groups
is the most power-hungry stage. As a result, enhancing the
of three rows, which helps to speed up the process. Any
second stage improves the multiplier's performance while
lowering its cost.
As the bit-width of approximated Han-Carlson parallel
prefix adder increases the power consumption and area
utilization is also double when compared with the previ-
ous bit-width. In approximate Han-Carlson parallel prefix

Fig. 4  a Actual and b Approximate 4:2 compressor Fig. 5  8 × 8 Wallace tree multiplier

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adder the power and area are increasing exponentially n×n

n×n n×n n×n
which is shown in Fig. 6(a) and (b). Multiplier
Multiplier Multiplier Multiplier
The implementation of the proposed approximated mul- using novel
using novel using novel using novel
tiplier using novel compressors and parallel-prefix adder compressor
compressor compressor compressor
increases the performance of the circuit. In this paper, the
authors implemented architectures of the approximate [2n: 1] [2n: 1]
multiplier by using the approximate Han-Carlson adder [2n: n+1] [n:1]
[2n: 1] [2n: n+1]
[28] and multiplier using novel compressor as shown in 2n bit
Speculative Han
Fig. 7. Carlson Adder
For the implementation of the proposed approximated 2n bit
multiplier Algorithm 1 is used. Speculative Han
Carlson Adder [n:1]
Algorithm 1: Proposed Approximated Multiplier
2n bit
Speculative Han
Carlson Adder [2n: n+1]
[n:1]

S [4n+1: 2n+2] S [2n+1] S [2n: n+1] S [n :1]

Fig. 7  Block diagram of proposed approximated multiplier

Input: Two n-bit binar y num ber s

Output: 2n-bit
S ta rt
S te p 1: T wo n- bit bina ry numbe rs are c onsid ere d ( A7- A0,
and B 7-B 0).
S te p 2: AND ga te is used for the ge ner ation of par tia l
produc ts.
S te p 3: Re duction of the par tia l pr oduct is done b y
e mploying a pproxima te novel c omp ressors (N_C ).
x1 N _C (A [n/ 2: 1], B[n / 2:1 ], P 1[ n:1 ])
x2 N _C (A [n: n /2 +1], B[n /2 :1 ], P 2[n :1 ])
x3 N _C (A [n /2 :1], B[n : n /2+1 ], P 3[n :1 ])
x4 N _C (A [n: n /2+ 1], B[n : n /2 +1], P4 [n: 1])
S te p 4: C ar ry propa gatio n a dder ha s be en for ca lc ula ting the
final produc t.
End

Figure 8 shows the proposed architecture of the approxi-

mate multiplier. This architecture is further used in the error-
tolerant application.
Implementing a Verilog code for an entire novel approxi-
mate multiplier using approximate parallel prefix adders
would be quite extensive. However, authors can provide with
a simplified example code that demonstrates the concept of
an approximate multiplier using approximate parallel prefix
adders. The Verilog code provided below is a basic illustration
for actual implementations.

Fig. 6  Approximate Han-Carlson Parallel-Prefix Adder graph a Area

(cells) b Power

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Fig. 8  Proposed architecture of

the approximate multiplier

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Table 1  Quantitative analysis of exact and approximated 3:2 com-

pressor
module ApproximateMultiplier(
input wire [n:0] A, Exact 3:2 Approximated
input wire [n:0] B, compressor 3:2 compressor
output wire [2n+1:0] Result
); Cell usage LUT 2 2
IBUF 3 3
wire [2n+1:0] partial_products[n:0]; OBUF 2 2
wire [2n+1:0] prefix_sums[n:0]; Area Cells 7 7
wire [2n+1:0] scaled_results[n:0];
Power (W) Dynamic 0.900 0.712
// Generate partial products Static 0.120 0.116
genvar i, j; Total on-chip power 1.02 0.828
generate
for (i = 0; i < n+1; i = i + 1) begin
for (j = 0; j < n+1; j = j + 1) begin
assign partial_products[i*(n+1) + j] = A[i] & B[j]; Table 2  Quantitative analysis of exact and approximated 4:2 com-
end pressor
end
endgenerate Exact 3:2 Approximated
// Approximate parallel prefix adders for prefix sum compressor 3:2 compressor
computation
Cell usage LUT 3 2
genvar k;
generate IBUF 5 4
for (k = 0; k < n+1; k = k + 1) begin OBUF 3 2
assign prefix_sums[k] = partial_products[k]; Area Cells 11 8
Power (W) Dynamic 1.545 0.995
ApproximateParallelPrefixAdder adder_instance (
Static 0.135 0.122
.inputs(partial_products[k*(n+1) + 1 : k*(n+1)]),
.output(prefix_sums[k]) Total on-chip power 1.68 1.11
);
end
endgenerate
The proposed approximated and exact 3:2 compressor
// Scale the approximate results results in 0.828 W and 1.02 W respectively total power
genvar l;
consumption. The proposed algorithm saves 23.18% power
generate
for (l = 0; l < (n+1); l = l + 1) begin consumption compared to the exact 3:2 compressor. After
assign scaled_r esults[l] = prefix_sums[l] << l; designing the proposed 3:2 compressor, the 4:2 compressor
end is designed and the results are tabulated in Table 2. Table 2
endgenerate shows the results of the exact and proposed approximated
// Final result calculation
4:2 compressor.
assign Result = scaled_results The proposed approximated and exact 4:2 compressor
results in 1.11 W and 1.68 W respectively total power con-
sumption. The proposed algorithm saves 51.35% power con-
sumption compared to the exact 4:2 compressor.
Table 3, tabulates the comparison of the truth table for
Results and Discussion approximated 4–2 compressor from existing papers and the
proposed algorithm. In Table 3, E represents the error (the
Approximate computing plays an essential role in error- difference between the no. of inputs of 1 and the approxi-
tolerant systems by reducing power consumption. For the mated count calculated from the compressor). Lin and Lin
efficient computing of the circuit, approximation tech- [17] and the proposed compressor shows only one error
niques are proposed and implemented in this paper. The when × 4 × 3 × 2 × 1 = ‘1’ but the proposed algorithm con-
results obtained from the proposed compressor and multi- sumes 6.5% less power in comparison to the existing [17].
plier design are studied and compared to standard designs Yang et al. [15], proposed algorithm getting more than one
in this section. The simulation and implementation of the error but our proposed algorithm shows remarkable results,
proposed designs is done in VIVADO 2018.3. Table 1 and the efficiency of the circuit is also improved.
shows the results of the exact and proposed approximated From the comparison, it is clear that our proposed algo-
3:2 compressor. rithm can be used as a basic component. The proposed

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Table 3  Comparison Of The Proposed Approximated 4:2 Algorithm With State-Of-Art Work
x4x3x2x1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Strollo et al. CS 00 01 01 10 01 10 10 10 01 10 10 11 10 11 11 11
[14] E -1 −1
Yang et al. CS 00 01 01 10 01 10 10 11 01 10 10 11 11 10 10 11
[15] E +1 -1 -1 −1
Lin and Lin CS 00 01 01 10 01 10 10 11 01 10 10 11 10 11 11 10
[17] E −2
Proposed CS 00 01 01 10 01 10 10 11 01 10 10 11 10 11 11 10
E −2

Table 4  Quantitative Analysis Exact multiplier [29] Multiplier using

Of multiplier using compressor novel Compres-
with state-of-art work sor

Cell usage LUT 57 54 80

IBUF 16 16 16
OBUF 16 16 16
Area Cells 89 86 112
Memory (MB) Peak 434.422 609.281 435.641
Gain 152.527 327.320 153.223
Power (W) Dynamic 10.284 7.845 6.884
Static 1.039 0.349 0.707
Total on-chip power 11.323 8.194 7.591
Junction temperature (°C) 125 121.4 112.5
Thermal margin (°C) − 70.6 (− 5.4 W) − 30.0 (− 3.4 W) − 27.5 (− 2.0 W)

algorithm shows a remarkable result and less error in Table 5  quantitative analysis of approximate multiplier using novel
comparison to other algorithms. Table 4 shows the result compressor and speculative han-carlson adder
of the multiplier using compressor with state-of-art work.
Approximated multiplier
Table 4 illustrates that the multiplier using compressor
shows remarkable results in comparison to the exact mul- Cell usage LUT 121
tiplier, and [29]. The multiplier using novel compressor, IBUF 16
exact multiplier and [29] results in 7.591 W, 11.323 W, OBUF 17
and 8.194 W respectively total power consumption. The Area Cells 154
proposed algorithm saves 49.16% and 7.94% power con- Memory (MB) Peak 726.836
sumption compared to the exact multiplier and [29]. Also, Gain 408.297
the multiplier using compressor results in a − 27.5 °C Power (W) Dynamic 12.583
thermal margin and 112.5 °C junction temperature. For Static 0.341
validation of results, the proposed approximated multi- Total On- 12.923
plier is used as a basic building block in image process- Chip Power
ing applications. Image processing applications are error- Junction temperature (°C) 43.2
resilient and the use of approximation in it doesn’t affect Thermal margin (°C) 41.8 (28.7 W)
the overall performance of the circuit. Table 5 shows the
result of the approximated multiplier using compressor
and speculative Han-Carlson adder.

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Image Processing Application Using System Table 6  Comparison of the existing approximate multiplier and pro-
Generator posed approximate multiplier
PSNR (dB) (Set 1) PSNR(
The approximate multiplier is used in image processing dB) (Set
applications like image blending, or edge detection. The 2)
model design is constructed in a system generator by using Momeni et al. [12] 8.21 15.09
the Xilinx Blockset Library. Matlab/Simulink environment Toan and Lee [13] 17.88 20.54
is used for the simulation and implementation of the cir- Strollo et al. [14] 15.17 14.63
cuits. With the help of the video viewer, the final result is Proposed multiplier 23.87 22.7
reflected. For the facilitation of hardware design of FPGA,
Xilinx’s System Generator tool is used. It provides a well-
suited interface between software (MATLAB) and hardware 35.55% improvement when compared to [12, 13], and [14]
(Xilinx Vivado). The System generator can automatically respectively. The proposed approximated multiplier shows
run all design processes including implementation, debug- significant results compared to state-of-art work. In this
ging, and verification. It can also import an HDL file for research paper, the authors designed low-power consump-
simulation and verifies its result. Two sets consisting of two tion image processing applications that have paved the way
images of dimension 128 × 128 are considered as shown in for a whole new area in low power consumption error-
Fig. 9. These two images are fed into the pre-processing tolerant circuits with approximate computing. These appli-
stage followed by the multiplication and post-processing cations save power consumption at the cost of a reduction
stages. With the help of the image viewer, the output is in inaccuracy. Furthermore, such implementations reduce
obtained. The state-of-art works with the same set of images the complexity of the system architecture and delay.
are also shown in Fig. 9. Conclusion And Future Work
Figure 9 evaluates the image blending application using an In this research paper, the approximate multiplier is
approximate multiplier. Two images are multiplied with each proposed using the approximate novel compressor and
other pixel-by-pixel which results in the blending of two images speculative Han-Carlson adder. The design and analy-
into one output image. PSNR is used as an evaluation param- sis of the approximate multiplier are implemented with
eter. Two different sets consisting of two images are blended reduced power consumption when compared with the
and results in 23.87 dB and 22.7 dB PSNR respectively. The existing architectures. Simulation and verification of the
proposed results are compared with the existing state-of-art proposed compressors and multipliers are done with the
technique and the results are tabulated in Table 6. shows the help of VIVADO 2018.3. After approximation of multi-
comparison between the proposed and the prior work in terms plication block, it is further used for image processing
of quality (PSNR) of images. PSNR is calculated regarding the application for image blending of two sets of images,
output image obtained using the exact multiplier. resulting in PSNR of 23.87 dB and 22.7 dB respectively.
For set 1, the proposed approximated multiplier shows The same work may be extended for different bit lengths
65.60%, 25.09%, and 36.44% improvement in compari- of the approximate multiplier by exploring the possibility
son to [12, 13], and [14] respectively. For set 2, the pro- of various architectures.
posed approximated multiplier shows 33.52%, 9.51%, and

Input image 1 of Input image 2 of Output image using Output image using an
[12] [13] [14]
dimension 128×128 dimension 128×128 exact multiplier approximate multiplier

Set 1

Set 2

(a) (b) (c) (d) (e) (f) (g)

Fig. 9  a and b Input images of dimension 128 × 128 c Output image using exact multiplier d Output image using proposed approximate multi-
plier e Output image using algorithm in [12] f Output image using algorithm in [13] g Output image using algorithm in [14]

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Computer Design (ICCD), Asheville, NC, 2013, pp. 33–38.
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