La Salle University

Practice #10: '4-bit Synchronous Counter'

José Guillermo González González

April 14, 2010

MEMBERS:
Álvarez Del Castillo Balderas Gabriela
Bucio Ramírez Ariana
Zamora Samara Itandehui Castle
Leader González Gerardo Enrique
Cruz Fernández Ricardo Mario
González Medina Lilia Elena
Ponce Martínez Jorge Roberto
David Isaí Robles González
Roberto Antonio SolanoVargas
Waltier Barraza Christian Axel
Zepeda Martínez Celia Susana
 Practice #10: Synchronous Counter

Objective
Experimentally understand the operation of a 4-bit synchronous up/down counter
bits, with upper and lower limits and load/count signal.

Materials
7404- NOT Gate.
7408- Gates AND.
7427- NOR gates with 3 inputs.
7400- NAND Gates.
•7432- Gates OR.
Integrated-74LS193
ET100 - Logic Computer.
Protoboards.
Cables.
Signal Generator.
Pointed and Cutting Pliers

Theoretical Framework
Asynchronous counters cannot be used to keep exact counts when we need them.
with the highest possible precision, we must use Synchronous or "Parallel" Counters. The synchronous counter
"Paralelo" has more complex connections, but it also has many advantages:

All the FFs, no matter how many there are, change at the same time, synchronized by the signal.
of clock.
An advantage derived from the first is that the propagation time is minimized,
that the counting should only propagate through one or two gates and a FF (because they change to the
same time, and do not depend on another FF to operate.
The delay of these counters will be much lower than that of an asynchronous counter with the same number.
from FF (BITS).

The term synchronous refers to events that have a fixed temporal relationship with each other. With
Regarding the operation of the counter, synchronous means that all the flip-flops of the counter receive
at the same instant the clock signal.

In a synchronous counter, all flip-flops are triggered simultaneously. This allows the use of a
general clock frequency is higher than in the case of asynchronous counters, due to the
the minimum clock period is limited to the time necessary to calculate the next state using very
few levels of doors.

4-bit Synchronous Counter

The following figure illustrates the circuit of a synchronous counter (Parallel):

The 4-bit synchronous binary counter is implemented with flip-flops triggered by the negative edge.

In a synchronous 2-bit binary counter, it initially starts at 0, the two flip-flops are
they are found in RESET state. When the positive edge of the first clock pulse is applied, then Q0
it is set to HIGH. Although delays are an important factor in the operation of a
synchronous counter, they are often omitted to simplify the general timing diagrams. If not
they show the small delays and timing differences, it is possible to relate better
the signals resulting from a logic circuit. However, in high-speed digital circuits, these
small delays are an important consideration in the design and localization of failures.

Under normal operating conditions, the J and K inputs of each flip-flop must remain
stable at 1 or 0 logic while the counter pulse experiences its transitions. A logic in the
Clear control line will force all the counter outputs to assume a logical 0 and will keep them that way.
until the clear line returns to 0 logical (its normal logical value). The Inhibit control signal serves
to block the counting pulses and leave the counter in some non-zero state, if required
data retention behavior for a particular application.
When the counters reach the state where all values are equal to one, the signal of
Overflow will be high. In some designs of counters, this overflow signal is used.
to control the cascading counter modules and produce counters with longer word lengths.
In these cases, the overflow signal is called cascading carry-out (RCO).

Up/Down Synchronous Counter

An up/down counter is one that is capable of progressing in either direction.

along a certain sequence. An ascending descending counter, sometimes also
the so-called bidirectional counter can have any specified sequence of states. A
3-bit binary counter that advances in ascending mode through the sequence (0 - 7) and then
it can be reversed to traverse the sequence in the opposite direction (7 - 0) is an example of a way to
ascending / descending sequential operation. These counters can be reversed at any point.
of its sequence.

Desarrollo y Resultados
FIRST PART

It is composed of 4 parts of the project carried out in a team:

First, we assembled the first part of a synchronous counter with the 74LS109 integrated circuit, which we had to
deny the entry k, as it was with negated logic,

The result of this first part is a 2-bit synchronous counter that can hold data with a signal of
load/count.
The second part was to create the second block of the counter with an additional 2 bits, so that when combined with a
gate and let's obtain a 4-bit synchronous counter

The third part is 4 AND gate blocks with an OR, which has as input the signals Q and Qnegated,
they have in common a signal from a switch to load data, or to count, we connect these outputs
LEDs to see our result, the result of the connection with AND gates and an OR allows us to visualize.
an ascending or descending count as we change the switch, and these data outputs are connected to
our 4th part of the project

The 4th part is the connection of each of the ascending or descending data outputs respectively.
connected to a switch via an exclusive OR gate these switches allow us to define the upper limit
How far should our meter count?

SECOND PART
We conducted research in the integrated circuit manuals to find an integrated circuit that
It will function as a 4-bit synchronous counter, ascending and/or descending.

We assembled each of the flip-flops in the ET100.

With the oscilloscope, we were checking the clock signal.

We connected the output to the LED to observe the responses in relation to the inputs proposed by the
truth table.
Conclusions

Team: Zepeda Martínez Celia Susana, González Medina Lilia Elena and Castillo Zamora Samara Itandehui
When we connect all the flip-flops to the same clock, we achieve that the outputs change.
simultaneously with each pulse, this mode of operation eliminates the delays associated with the
asynchronous counters.
As this circuit uses two enable signals, when we wanted to count upwards down
It should have been on logic level 1. And when we wanted to count downwards, up had to be enabled.
Team: Jorge Roberto Ponce Martínez and Álvarez Del Castillo Balderas Gabriela
In this practice, we have already learned to develop a synchronous 4-bit counter.
ascending as descending and that retained a value with the load signal and count, the counters
they have many applications, such as timers, clocks, frequency dividers, and
frequency meters. Timers are very important in computers, just like in
communications
We also learned to set the upper and lower limits for the counter, and unlike the practice
This counter is synchronous since the clock is common for the flip-flops, and this helps us in
applications where we require more precision and would be adversely affected by delays that exist in the
asynchronous counters.
Team: Bucio Ramírez Ariana, Cruz Fernández Ricardo Mario and Solano Vargas Roberto Antonio
This time we had to develop a circuit that can count both synchronously and asynchronously in parts.
depending on the use of a clock frequency, in an ascending or descending manner
to maintain data that could be used to manipulate its limits.
-
Team: Waltier Barraza Christian Axel and Caudillo González Gerardo Enrique
In conclusion, the counter allows us to keep the data until we manage to save it, however
we managed to understand the operation of a synchronous and asynchronous counter through the
understanding of each of its components.

Comments and Suggestions

Team: Zepeda Martínez Celia Susana, González Medina Lilia Elena and Castillo Zamora Samara Itandehui
This practice was supposed to be done with the 74191 integrated circuit; however, this integrated circuit was not
was available in the university laboratories, nor in any store, so that
we use a similar integrated circuit.
Team: Jorge Roberto Ponce Martínez and Álvarez Del Castillo Balderas Gabriela
The practice was a bit complicated as we experienced difficulties in joining the different ones.
parts of the circuit, the up/down signals and the load/count, but in doing so it helped us understand
step by step how each part and component of the circuit worked.
Team: Bucio Ramírez Ariana, Cruz Fernández Ricardo Mario and Solano Vargas Roberto Antonio
An asynchronous counter cannot keep exact counts and when precision is needed we use a
synchronous counter, the main advantage we find in synchronous counters over the
Asynchronous systems rely on all Flip-Flops changing at the same time, regardless of how many there are.
synchronized by the clock signal.
The 74 109 integrated circuit was used due to the lack of the 108 integrated circuit; we would recommend obtaining these.
integrated to carry out this practice in a simpler way
Team: Waltier Barraza Christian Axel and Caudillo González Gerardo Enrique
It is a bit complicated to maintain the integrity of a circuit using equipment since each one
the teams have their personal way of assembling circuits, and therefore when connecting them,
It takes a little effort to reach an agreement; however, it is useful due to being such a large practice.