EE5311 Tutorial-3
Pranav Suraj STP
EE22B131
Problem-1
Solving for (W/L)p
• Inverter threshold voltage Vinv ≈ VDD /2.
Figure 1: Solving for (W/L)p
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Figure 2: Vin vs Vout for calculated (W/L)p = 7.9
(a) Noise Margins
Figure 3: Schematic setup for determining noise margins
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Figure 4: Derviative of Vout
Figure 5: Showing ViH, ViL
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(b) Effect of (W/L)p
Figure 6: (W/L)p = 0.1192
Figure 7: (W/L)p = 1.192.
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Figure 8: (W/L)p = 11.92.
Observations:
• Increasing (W/L)p : PMOS becomes stronger, Vinv decreases, transition
is shallower.
• Decreasing (W/L)p : PMOS becomes weaker, Vinv increases, transition
is sharper.
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(c) Effect of Different VDD Values
Figure 9: DC transfer characteristic for VDD ranging from 0.2V to 1.8V
Observation:
• At very low VDD (e.g., 0.2V): both NMOS and PMOS may operate in
subthreshold, leading to weak drive currents.
• At higher VDD (e.g., 1.8V): strong inversion, well-defined switching.
• For VDD <= 1.4, this can’t be used as an inverter.
Adjustment Strategy:
• If Vinv too high ⇒ increase (W/L)p (strengthen PMOS).
• If Vinv too low ⇒ decrease (W/L)p (weaken PMOS).
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Figure 10: Ids vs Vin for VDD = 0.2, 0.8, 1.8 V
(d) Analytical value of peak Ids
• The following are the values of IDS at VDD = 0.8V and VDD = 1.8V:
– VDD = 0.8V : 32 nA @ 510mV
– VDD = 1.8V : 26.30 µA @ 900mV
• For VDD = 0.8V, VSG = 0.29V , which is less than |VT p |. Hence,
according to the analytical model, current should be 0. The current
flowing in the circuit in this case is sub-threshold current
• For VDD = 1.8V, the current according to the analytical model is 33.13
µA, which, though off by 10 µA, is the same order of magnitude as the
simulated value of current.
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Problem-2
Sizing pMOS transistor
Figure 11: Calculation of Wp and Lp
• Substituting all values and solving for (W/L)p, we get (W/L)p = 2.26,
with the corresponding width = 0.34 µm for L = 0.15 µm. Since a
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width of 0.34 µm is not allowed, L was increased such that (W/L)p =
2.26.
• Sweeping the Length of pMOS from L = 0.189 µm (corresponding to
W = 0.42 µm and (W/L)p = 2.26).
Figure 12: Plot showing VOL converging to 0.1 V
Figure 13: Schematic
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(a) Inverter Threshold Voltage
Figure 14: DC Transfer Characteristics
The inverter threshold voltage Vth is 1.097 V
Figure 15: Vth from simulation
Analytical Expression
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Figure 16: Vth Calculation
(b) Noise Margins
Figure 17: Schematic and SPICE code
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• VIH and VIL were calculated by looking at the points where the deriva-
tive of the transfer function becomes -1 using SPICE.
• Since VOH = VDD and VOL = 0.1 V , the noise margins were calculated
as, NM L = VIH - VOL and NM H = VDD VIH .
• Using these, the noise margins were found to be as follows:
Figure 18: NM L and NM H values
• Below is the plot of the derivative of transfer function:
Figure 19: Derivative plot for noise margin extraction
• The analytical calculations for getting VIH and VIL are as shown:
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Figure 20: VIH and VIL calculation
(c) Average Power Dissipation
• Average power dissipated is found as, Pdiss = IDS × VDD
Figure 21: Pdiss from simulation
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Figure 22: Pdiss Calculation
NOTE:
Nomenclature used as follows:
• V inv (inverter threshold voltage) was also denoted as V th sometimes.
• Kp = µp Coxp
• Kn = µp Coxn
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