ELECTRONICS AND COMMUNICATION ENGINEERING
ECL 203 LOGIC DESIGN LAB CATEGORY L T P CREDIT
PCC 0 0 3 2
Preamble: This course aims to (i) familiarize students with the Digital Logic Design through
the implementation of Logic Circuits using ICs of basic logic gates (ii) familiarize students
with the HDL based Digital Design Flow.
Prerequisite: Nil
Course Outcomes: After the completion of the course the student will be able to
CO 1 Design and demonstrate the functioning of various combinational and sequential
circuits using ICs
CO 2 Apply an industry compatible hardware description language to implement digital
circuits
CO 3 Implement digital circuis on FPGA boards and connect external hardware to the
boards
CO 4 Function effectively as an individual and in a team to accomplish the given task
Mapping of course outcomes with program outcomes
PO PO PO 3 PO 4 PO 5 PO 6 PO 7 PO 8 PO 9 PO PO PO
1 2 10 11 12
CO 1 3 3 3 3 3
CO 2 3 1 1 3 3 3 3
CO 3 3 1 1 3 3 3 1 3
CO 4 3 3 3 3 3 3
Assessment
Mark distribution
Total CIE ESE ESE Duration
Marks
150 75 75 2.5 hours
Continuous Internal Evaluation Pattern:
Attendance : 15 marks
Continuous Assessment : 30 marks
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Internal Test (Immediately before the second series test) : 30 marks
End Semester Examination Pattern: The following guidelines should be followed regarding award
of marks
(a) Preliminary work : 15 Marks
(b) Implementing the work/Conducting the experiment : 10 Marks
(c) Performance, result and inference (usage of equipments and trouble shooting) : 25 Marks
(d) Viva voce : 20 marks
(e) Record : 5 Marks
General instructions: End-semester practical examination is to be conducted immediately after
the second series test covering entire syllabus given below. Evaluation is to be conducted under
the equal responsibility of both the internal and external examiners. The number of candidates
evaluated per day should not exceed 20. Students shall be allowed for the examination only on
submitting the duly certified record. The external examiner shall endorse the record.
Course Level Assessment Questions
Course Outcome 1 (CO1): Design and Development of combinational circuits
1. Design a one bit full adder using gates and implement and test it on board.
2. Implement and test the logic function f(A,B,C)=∑m(0,1,3,6) using an 8:1 Mux IC
3. Convert a D flip-flop to T flip-flop and implement and test on board.
Course Outcome 2 and 3 (CO2 and CO3): Implementation of logic circuits on tiny
FPGA
1. Design and implement a one bit subtracter in Verilog and implement and test it on a tiny
FPGA board.
2. Design and implement a J-K flip-flop in Verilog, implement and test it on a tiny FPGA
board.
3. Design a 4:1 Multiplexer in Verilog and implement and test it on tiny FPGA board.
List of Experiments:
It is compulsory to conduct a minimum of 5 experiments from Part A and a minimum of 5
experiments from Part B.
Part A (Any 5)
The following experiements can be conducted on breadboard or trainer kits.
1. Realization of functions using basic and universal gates (SOP and POS forms).
2. Design and Realization of half /full adder and subtractor using basic gates and universal
gates.
3. 4 bit adder/subtractor and BCD adder using 7483.
4. Study of Flip Flops: S-R, D, T, JK and Master Slave JK FF using NAND gates.
5. Asynchronous Counter:3 bit up/down counter
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6. Asynchronous Counter:Realization of Mod N counter
7. Synchronous Counter: Realization of 4-bit up/down counter.
8. Synchronous Counter: Realization of Mod-N counters.
9. Ring counter and Johnson Counter. (using FF & 7495).
10. Realization of counters using IC’s (7490, 7492, 7493).
11. Multiplexers and De-multiplexers using gates and ICs. (74150, 74154)
12. Realization of combinational circuits using MUX & DEMUX.
13. Random Sequence generator using LFSR.
PART B (Any 5)
The following experiments aim at training the students in digital circuit design with verilog and
implementation in small FPGAs. Small, low cost FPGAs, that can be driven by open tools for
simulation, synthesis and place and route, such as TinyFPGA or Lattice iCEstick can be used.
Open software tools such as yosis (for simulation and synthesis) and arachne (for place and
route) may be used. The experiments will lay the foundation for digital design with FPGA with
the objective of increased employability.
Experiment 1. Realization of Logic Gates and Familiarization of FPGAs
(a) Familiarization of a small FPGA bboard and its ports and interface.
(b) Create the .pcf files for your FPGA board.
(c) Familiarization of the basic syntax of verilog
(d) Development of verilog modules for basic gates, synthesis and implementation in the
above FPGA to verify the truth tables.
(e) Verify the universality and non associativity of NAND and NOR gates by uploading the
corresponding verilog files to the FPGA boards.
Experiement 2: Adders in Verilog
(a) Development of verilog modules for half adder in 3 modeling styles (dataflow/structural/
behavioural).
(b) Development of verilog modules for full adder in structural modeling using half adder.
Experiement 3: Mux and Demux in Verilog
(a) Development of verilog modules for a 4x1 MUX.
(b) Development of verilog modules for a 1x4 DEMUX.
Experiement 4: Flipflops and coutners
(a) Development of verilog modules for SR, JK and D flipflops.
(b) Development of verilog modules for a binary decade/Johnson/Ring counters
Experiment 5. Multiplexer and Logic Implementation in FPGA
(a) Make a gate level design of an 8 : 1 multiplexer, write to FPGA and test its functionality.
(b) Use the above module to realize the logic function f (A, B, C) = ∑m(0, 1, 3, 7) and test it.
(c) Use the same 8 : 1 multiplexer to realize the logic function f (A, B, C, D) = ∑m(0, 1, 3, 7,
10, 12) by partitioning the truth table properly and test it.
Experiment 6. Flip-Flops and their Conversion in FPGA
(a) Make gate level designs of J-K, J-K master-slave, T and D flip-flops, implement and test
them on the FPGA board.
(b) Implement and test the conversions such as T to D, D to T, J-K to T and J-K to D
Experiment 7: Asynchronous and Synchronous Counters in FPGA
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(a) Make a design of a 4-bit up down ripple counter using T-flip-lops in the previous
experiment, implement and test them on the FPGA board.
(b) Make a design of a 4-bit up down synchronous counter using T-flip-lops in the previous
experiment, implement and test them on the FPGAboard.
Experiment 8: Universal Shift Register in FPGA
(a) Make a design of a 4-bit universal shift register using D-flip-flops in the previous
experiment, implement and test them on the FPGA board.
(b) Implement ring and Johnson counters with it.
Experiment 9. BCD to Seven Segment Decoder in FPGA
(a) Make a gate level design of a seven segment decoder, write to FPGA and test its
functionality.
(b) Test it with switches and seven segment display. Use ouput ports for connection to the
display.
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