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Verilog Code for Logic Gates and Tests

The document contains Verilog code for various digital logic gates including NOT, OR, and NAND gates, along with their respective test benches. Each gate is defined in a module with input and output specifications, and the test benches simulate the behavior of the gates with different input combinations. The NAND gate is implemented in both structural and behavioral styles, demonstrating different approaches to digital design.

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Jaya Kumar
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7 views7 pages

Verilog Code for Logic Gates and Tests

The document contains Verilog code for various digital logic gates including NOT, OR, and NAND gates, along with their respective test benches. Each gate is defined in a module with input and output specifications, and the test benches simulate the behavior of the gates with different input combinations. The NAND gate is implemented in both structural and behavioral styles, demonstrating different approaches to digital design.

Uploaded by

Jaya Kumar
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

NOT GATE

module not_gate(y, a);

output y;

input a;

assign y = ~a;

endmodule

module tb;

reg a;

wire y;

not_gate uut (y, a);

initial begin

a = 1'b0;

#100 a = 1'b1;

#100 a = 1'b0;

end

endmodule

OR GATE

module OR_Gate(Y, A, B);

output Y;

input A, B;

or (Y, A, B);

endmodule
module OR_GATE_TB;

reg a, b;

wire y;

OR_Gate m1 (y, a, b);

initial begin

a = 1'b0; b = 1'b0;

#100 a = 1'b0; b = 1'b1;

#100 a = 1'b1; b = 1'b0;

#100 a = 1'b1; b = 1'b1;

end

endmodule
NOT GATE

Module nand_gate(z, x, y);

output z;

input x, y;

wire w1;

and (w1, x, y);

not (z, w1);

endmodule

module nand_gate_tb;

wire z;

reg x, y;

nand_gate_data m2 (z, x, y);

initial begin

x = 1'b0; y = 1'b0;

#100 x = 1'b0; y = 1'b1;

#100 x= 1'b1; y = 1'b0;

#100 x = 1'b1; b = 1'b1;

end

endmodule
module nand_gate_data(z, x, y);

output z;

input x, y;

assign z = ~(x & y);

endmodule

module nand_gate_data_tb;

wire z;

reg x, y;

// Instantiate the NAND gate

nand_gate_data n1(z, x, y);

initial begin

// Test case 1

x = 1'b0; y = 1'b0;

#100;

// Test case 2

x = 1'b0; y = 1'b1;

#100;

// Test case 3

x = 1'b1; y = 1'b0;

#100;

// Test case 4

x = 1'b1; y = 1'b1;

#100;

end

endmodule
module nand_gate_beh(z, x, y);

output reg z;

input x, y;

always @ (x or y) begin

if (x == 1'b1 && y == 1'b1) begin

z = 1'b0;

end

else begin

z = 1'b1;

end

end

endmodule
`timescale 1ns/1ps

module tb_nand_gate_beh;

// Testbench signals

reg x, y;

wire z;

// Instantiate the NAND gate behavioral model

nand_gate_beh uut (

.z(z),

.x(x),

.y(y)

);

initial begin

$display("Time | x y | z");

$display("----------------");

// Test case 1

x = 1'b0; y = 1'b0; #10;

$display("%4t | %b %b | %b", $time, x, y, z);

// Test case 2

x = 1'b0; y = 1'b1; #10;

$display("%4t | %b %b | %b", $time, x, y, z);

// Test case 3

x = 1'b1; y = 1'b0; #10;

$display("%4t | %b %b | %b", $time, x, y, z);

// Test case 4
x = 1'b1; y = 1'b1; #10;

$display("%4t | %b %b | %b", $time, x, y, z);

$finish;

end

endmodule

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