Draw state diagram for given pattern detector. Write verilog codes.
Simple logic
questions.
verilog
module pattern (input sequence[2:0],output out);
state typedef enum={
3b'000=initial,
3b'001=sec,
3b'011=thi,
3b'111=final
}
state current,next;
always(*)begin
case(current)begin
initial:
next=(sequence==001)?sec:initial;
sec:
next=(sequence==011)?thi:sec;
thi:
next=(sequence==111)?final:initial;
endcase
current =next;
if(next==final)
assign out=1'b1;
endmodule
//////////////////////////////////////////////////////
module pattern (
input clk, // clock
input rst_n, // active-low reset
input [2:0] sequence, // 3-bit input
output reg out // output
);
// State encoding
parameter INITIAL = 2'b00,
SEC = 2'b01,
THI = 2'b10,
FINAL = 2'b11;
reg [1:0] current, next;
// State register
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
current <= INITIAL;
else
current <= next;
end
// Next-state logic
always @(*) begin
next = current; // default stay
case (current)
INITIAL: begin
if (sequence == 3'b001)
next = SEC;
else
next = INITIAL;
end
SEC: begin
if (sequence == 3'b011)
next = THI;
else
next = INITIAL; // reset if mismatch
end
THI: begin
if (sequence == 3'b111)
next = FINAL;
else
next = INITIAL;
end
FINAL: next = INITIAL;
default: next = INITIAL;
endcase
end
// Output logic (Moore type)
always @(*) begin
if (current == FINAL)
out = 1'b1;
else
out = 1'b0;
end
endmodule
//////////////////////////////////////////////////////////////////
module pattern (
input logic clk, // clock signal
input logic rst_n, // active-low reset
input logic [2:0] sequence, // 3-bit input sequence
output logic out // output signal
);
typedef enum logic [1:0] {
INITIAL = 2'b00,
SEC = 2'b01,
THI = 2'b10,
FINAL = 2'b11
} state_t;
state_t current, next;
// State register
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)
current <= INITIAL;
else
current <= next;
end
// Next-state logic
always_comb begin
next = current;
case (current)
INITIAL: if (sequence == 3'b001) next = SEC;
SEC: if (sequence == 3'b011) next = THI;
THI: if (sequence == 3'b111) next = FINAL;
FINAL: next = INITIAL; // reset or loop back
default: next = INITIAL;
endcase
end
// Output logic (Moore type)
assign out = (current == FINAL);
endmodule
////////////////////////////////////////////////////
Verilog code for AND gate using MUX
module and(input wire A,input wire B, output out);
assign out=A?B:1'b0;
endmodule
///////////////////////////////////////////////////
// 4:1 mux module (select[1:0], d3..d0 -> y)
module mux4 (
input wire [1:0] sel,
input wire d3, d2, d1, d0,
output wire y
);
assign y = sel == 2'b00 ? d0 :
sel == 2'b01 ? d1 :
sel == 2'b10 ? d2 :
d3 ;
endmodule
// 3-input XOR implemented using the mux4 above
module xor3_using_mux (
input wire A,
input wire B,
input wire C,
output wire Y
);
// select = {B,C}
wire [1:0] sel = {B, C};
// Data inputs as derived: D0=A, D1=~A, D2=~A, D3=A
mux4 u_mux4 (
.sel(sel),
.d3(A),
.d2(~A),
.d1(~A),
.d0(A),
.y(Y)
);
endmodule
////////////////////////////////////////////////////////
module 41multiplier(input [1:0] sel,
input A,
input B,
input C,
input D,
output out);
assign out=(sel==2'b00)?A:
2'b01?B:
2'b10?C:D;
endmodule
////////////////////////////////////////////////////////
jk flip flop
module jkff(intput j,input k,intput clk,input rst,output q,output qb)
always@(posedge clk or negedge rst )
begin
Case({j,k})
begin
2'b00:begin
q<=q;
qb<=qb;
end
///////////////////////////////////////////////////////////////////
module jkff(
input j,
input k,
input clk,
input rst, // active-low reset
output reg q,
output qb
);
assign qb = ~q; // keep qb always inverse of q
always @(posedge clk or negedge rst) begin
if (!rst) begin
q <= 1'b0; // reset state
end
else begin
case ({j, k})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // Reset
2'b10: q <= 1'b1; // Set
2'b11: q <= ~q; // Toggle
endcase
end
end
endmodule
////////////////////////////////////////////
mod 3 counter
module counter(input clk,intput rst,output [1:0]count);
always@(posedge clk or negedge rst)
begin
if(!rst)
count<=2'b00;
else if(count ==2'b10)
count<=2'b00;
else
count<=count+1;
end
endmodule
//////////////////////////////////////////
module counter(
input clk,
input rst,
output reg [1:0] count
);
always @(posedge clk or negedge rst) begin
if (!rst)
count <= 2'b00;
else if (count == 2'b10) // When count reaches 2 (decimal 2)
count <= 2'b00; // Reset to 0
else
count <= count + 1;
end
endmodule
///////////////////////////////////////////////////
`timescale 1ns/1ps
module tb_counter;
reg clk;
reg rst;
wire [1:0] count;
// Instantiate the counter
counter uut (
.clk(clk),
.rst(rst),
.count(count)
);
// Clock generation: 10ns period
initial clk = 0;
always #5 clk = ~clk;
initial begin
// Initialize reset
rst = 0;
#12; // Hold reset low for a bit more than one clock cycle
rst = 1; // Release reset
// Run simulation for enough cycles to see the count wrap
#100;
$finish;
end
// Monitor outputs
initial begin
$monitor("Time=%0t | rst=%b | count=%b", $time, rst, count);
end
endmodule
/////////////////////
// 2-to-4 Decoder
module decoder2to4(
input [1:0] in,
output reg [3:0] out
);
always @(*) begin
out = 4'b0000;
case(in)
2'b00: out = 4'b0001;
2'b01: out = 4'b0010;
2'b10: out = 4'b0100;
2'b11: out = 4'b1000;
endcase
end
endmodule
/////////////////////
/////////////////////
// 1-to-4 Demux
module demux1to4(
input wire in,
input wire [1:0] sel,
output reg [3:0] out
);
always @(*) begin
out = 4'b0000;
case(sel)
2'b00: out = {3'b000, in};
2'b01: out = {2'b00, in, 1'b0};
2'b10: out = {1'b0, in, 2'b00};
2'b11: out = {in, 3'b000};
endcase
end
endmodule
/////////////////////
/////////////////////
// 4-to-2 Encoder (no priority)
module encoder4to2(
input wire [3:0] in,
output reg [1:0] out
);
always @(*) begin
casez(in)
4'b0001: out = 2'b00;
4'b0010: out = 2'b01;
4'b0100: out = 2'b10;
4'b1000: out = 2'b11;
default: out = 2'b00;
endcase
end
endmodule
/////////////////////
/////////////////////
// 4-to-2 Priority Encoder
module priority_encoder4to2(
input wire [3:0] in,
output reg [1:0] out,
output reg valid
);
always @(*) begin
valid = 1'b1;
if(in[3]) out = 2'b11;
else if(in[2]) out = 2'b10;
else if(in[1]) out = 2'b01;
else if(in[0]) out = 2'b00;
else valid = 1'b0; // no input active
end
endmodule
/////////////////////
| Aspect | Verilog |
SystemVerilog |
| ------------------------------------- | ----------------------------------- |
---------------------------------------------------------------------- |
| **Purpose** | Hardware Description Language (HDL) | HDL
+ Hardware Verification Language |
| **Design vs Verification** | Mostly design focused |
Adds major verification features |
| **Data types** | Limited (wire, reg, integer, etc.) |
Extended data types (logic, bit, byte, enum, struct, union, class) |
| **Syntax enhancements** | Basic syntax |
Rich syntax: `foreach`, `unique`, `priority` case, `interface`, etc. |
| **Assertions** | No built-in assertions |
Built-in assertions (immediate and concurrent) for formal verification |
| **Object Oriented Programming (OOP)** | No support |
Supports classes, inheritance, polymorphism |
| **Randomization** | None |
Built-in constrained random stimulus generation |
| **Interfaces** | None (uses ports and wires) |
Interfaces to bundle signals and simplify connections |
| **Clocking blocks** | No |
Yes, to define synchronous regions explicitly |
| **Enumerations** | Simple `parameter` based constants |
Strongly typed enums with better readability |
| **Functions and Tasks** | Basic |
Enhanced with better scoping, automatic variables, void functions |
| **Packages** | Not supported |
Supports packages for better code reuse and namespaces |
| **Multidimensional arrays** | Limited support |
Full support, dynamic, associative, queues |
| **Coverage and Testbench support** | None |
Functional coverage, assertions, testbench classes, randomization |
#include <stdio.h>
#include <stdlib.h>
// Merge two sorted subarrays arr[l..m] and arr[m+1..r]
void merge(int arr[], int l, int m, int r) {
int n1 = m - l + 1;
int n2 = r - m;
// Create temp arrays
int *L = (int *)malloc(n1 * sizeof(int));
int *R = (int *)malloc(n2 * sizeof(int));
// Copy data to temp arrays L[] and R[]
for (int i = 0; i < n1; i++)
L[i] = arr[l + i];
for (int j = 0; j < n2; j++)
R[j] = arr[m + 1 + j];
// Merge temp arrays back into arr[l..r]
int i = 0, j = 0, k = l;
while (i < n1 && j < n2) {
if (L[i] <= R[j])
arr[k++] = L[i++];
else
arr[k++] = R[j++];
}
// Copy remaining elements of L[], if any
while (i < n1)
arr[k++] = L[i++];
// Copy remaining elements of R[], if any
while (j < n2)
arr[k++] = R[j++];
free(L);
free(R);
}
// l = left index, r = right index of the subarray of arr to sort
void mergeSort(int arr[], int l, int r) {
if (l < r) {
int m = l + (r - l) / 2;
// Sort first and second halves
mergeSort(arr, l, m);
mergeSort(arr, m + 1, r);
merge(arr, l, m, r);
}
}
// Utility function to print array
void printArray(int arr[], int size) {
for (int i = 0; i < size; i++)
printf("%d ", arr[i]);
printf("\n");
}
// Test program
int main() {
int arr[] = {12, 11, 13, 5, 6, 7};
int arr_size = sizeof(arr) / sizeof(arr[0]);
printf("Given array is \n");
printArray(arr, arr_size);
mergeSort(arr, 0, arr_size - 1);
printf("Sorted array is \n");
printArray(arr, arr_size);
return 0;
}