DESIGN AND ANALYSIS OF LOW POWER

APPROXMATE MULTIPLIER USING 15:4

COMPRESSOR
A Main Project Report submitted in partial fulfillment of the

requirements for the award of degree of

BACHELOR OF TECHNOLOGY
in
ELECTRONICSANDCOMMUNICATION ENGINEERING
Submitted

By

[Link] 22A95A0415
[Link] 21A91A04G6
[Link] 21A91A04B0
[Link] 21A91A04B2

Under the esteemed guidance of

Mr.S. HariChandra Prasad,

Asst. Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
ADITYA UNIVERSITY
(Formerly Aditya Engineering College (A))

2024-2025
 DEPARTMENTOF ELECTRONICS AND COMMUNICATION
ENGINEERING

CERTIFICATE

This is to certify that the project work entitled “DESIGN AND ANALYSIS OF LOW

POWER APPROXMATE MULTIPLIER USING 15:4 COMPRESSOR” is being submitted

by

[Link] 22A95A0415
[Link] 21A91A04G6
[Link] 21A91A04B0
[Link]
21A91A04B2

in partial fulfillment of the requirements for award of the [Link] degree in Electronics &

Communication Engineering.

Project Guide Head of the Department

Mr. S. HariChandra Prasad,[Link].,(Ph.D) Dr. Sanjeev Kumar, Ph.D.

Asst. Professor Assoc. Prof., Dept. of ECE

.
External Examiner
 DECLARATION

I hereby declare that the project entitled “DESIGN AND ANALYSIS OF

LOW POWER APPROXMATE MULTIPLIER USING 15:4
COMPRESSOR” is a
genuine project. This work has been submitted to the ADITYA UNIVERSITY
(Formerly Aditya Engineering College (A)), Surampalem in partial fulfillment
of the [Link]., degree. I further declare that this project work has not been
submitted in full or part of the award of any degree of this or any other
educational institutions.

by

P. INDU (22A95A0415)

[Link] (21A91A04G6)

SK. MUSTAK (21A91A04B0)

S. NIKITHA (21A91A04B2)
 ACKNOWLEDGEMENT

It is with immense pleasure that I would like to express my in debuted gratitude to my

project Guide Mr. S. HariChandra Prasad [Link].,(Ph.D), who has guided me a lot and
encourage in every step of the project work, his valuable moral support and guidance throughout
the project helped me a greater extent.
I owe our sincere gratitude to my project coordinator Dr. A L Siridhara, Assoc.
Professor for providing a great support and guidance throughout the project.

I am grateful to Dr. Sanjeev Kumar, Assoc. Prof. and HOD, for inspiring us all the
way and for arranging all the facilities and resources needed for my project.

I wish to thank our Dr. M.V. Rajesh, Assoc. Dean and Dr. Dola Sanjay S, Dean
School of Engineering for their encouragement and support during the course of my project.

I would like to extend my sincere thanks to Dr. G. Suresh, Registrar, Dr. S. Rama
Sree, Pro Vice-Chancellor, Dr. M.B. Srinivas, Vice-Chancellor, Dr. M. Sreenivasa Reddy,
Deputy Pro Chancellor and Management, Aditya University for unconditional support for
providing me the best infrastructural facilities and state of the art laboratories during my project.

Not to forget, Faculty, Lab Technicians, Non-Teaching Staff and our Friends who
have directly or indirectly supported me in completing this project on time
 Project-PO Mapping

A.Y: 2024-25 (AR 20) Sem.: VIII Section& Batch: C9

Project Title: DESIGN AND ANALYSIS OF LOW POWER APPROXMATE MULTIPLIER

USING 15:4 COMPRESSOR

Abstract

Approximate computing in multiplier design, which plays a pivotal role in error-resilient

applications like multimedia, offering fast results even at the cost of reduced accuracy. A novel 16-
bit Approximate multiplier architecture incorporating a 15:4 approximate compressor is proposed
to enhance reliability while balancing performance metrics. The design is simulated and
synthesized using Xilinx ISE , with a Kogge Stone Adder utilized in the final addition stage to
further improve speed. The proposed method demonstrates better efficiency compared to
traditional architectures using Han-Carlson adder.

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Overall Mapping 1 3 1 2 2 1 1 2 1 1 2

PSO1 PSO2
Overall Mapping 1 2

Signature of Project Members:

1.22A95A0415 2.21A91A04G6

3.21A91A04B0 4.21A91A04B2

Guide Signature
 Contents
Page No.
List of Figures i
List of Tables ii
Nomenclature iii

1. INTRODUCTION 1-6
1.1 Introduction To Approximate Arithmetic Unit 1
1.2 Types Of Multipliers In VLSI 2
1.2.1 Array Multiplier 3
1.2.2 Wallace Tree Multiplier 3
1.2.3 Dadda Multiplier 3
1.2.4 Booth Multiplier 4
1.2.5 Sequential Multiplier 4
1.3 Role Of Approximate Computing 4
1.4 Objectives Of The Project 5
1.5 Organization Of The Thesis 6
2. LITERATURE SURVEY 7-15

2.1 Adder 7
2.2 Compressors 9
2.3 Multipliers 12
3. DESIGN OF APPROXIMATE MULTIPLIER 17-20
3.1 Related Approximate Compressors 17
3.1.1 5:2 Compressor 17
3.1.2 6:2 Compressor 18
3.1.3 7:2 Compressor 18
3.1.4 7:3 Compressor 20
4. INTRODUCTION TO SOFTWARE TOOL 21-35
4.1 Xilinx 21
4.2 Introduction to Xilinx ISE 22
4.3 Xilinx Software 24
4.3.1 Creating a new Project 25
4.4 About Verilog 34
5. EXISTING METHOD 36-43

5.1 Block diagram of Existing method 36

5.2 Existing Compressor and Adder 37
5.2.1 3:2 Compressor 37
5.2.2 4:2 Compressor 38
5.2.3 Han-Carlson adder 40
6. PROPOSED METHOD 44-48
6.1 Block diagram Proposed method 44
6.2 Proposed compressor and Adder 45
6.2.1 5:3 Compressor 45
6.2.2 15:4 Compressor 46
6.3 Proposed Adder 47
6.3.1 Kogge stone adder 47
7. RESULT AND DISCUSSION 49-53
7.1 Code for16-bit proposed multiplier 49
7.2 Implementation 50
7.3 Comparison 52

8. CONCLUSION AND FUTURE SCOPE 54

REFERENCES 55-59
APPENDIX 60-70
 LIST OF FIGURES

Figure Number Figure Name Page No.

1.1 Approximate arithmetic unit 2

2.1 Different stages of parallel-prefix adder 7
3.1 Methodology for approximate multiplier 16
3.2 Diagram of 5:2 compressor 17
3.3 Diagramof6:2 compressor 18
3.4 Diagramof7:2 compressor 19
3.5 Diagramof7:3 compressor 20
5.1 Block Diagram Of Han-Carlson Adder 36
5.2 Block Diagram Of 3:2 Compressor 37
5.3 Block Diagram Of 4:2 Compressor 39
5.4 Han-CarlsonAdder 41
6.1 Block Diagram of 5-3 compressor 45
6.2 Function ofbasic KSA 47
6.3 Block Diagram of KSA 48
7.1 Simulationresult 16-bit multiplier 50
7.2 Schematic diagram of 15-4 compressor 50
7.3 Delay report of16-bit multiplier 50
7.4 Power report for 16-bit multiplier 51

i
 LIST OF TABLES

Table Number Table Name Page No.

7.5 Comparison of exact Compressors 52

7.6 Comparison of approximate Compressors 53

ii
 NOMENCLATURE

Abbreviation Description
CSA Carry Save Adder
CPU Central Processing Unit
ALU Arithmetic Logic Unit
FFT Fast Fourier Transform
LSB Least Significant Bit
VLSI Very Large-Scale Integration
LSI Large Scale Integration
IC Integrated Circuit
CAD Computer Aided Design
CAE Computer Aided Engineering
CMOS ComplementaryMetal
Oxide Semiconductor
FPGA Field Programmable Gate Array
SSI Small Scale Integration
MOS Metal Oxide Semiconductor
MSI Medium Scale Integration
DSP Digital Signal Processing
ASIC Application
Specific Integrated
Circuits
ULSI Ultra large Small Integration
SOC System On Chip
AI Artificial Intelligence
IOT Internet Of Things
HDL Hardware Description Language
PLD Programmable Logic Device
CPLD ComplexProgrammable
Logic Device
AMD Advanced Micro Devices
ISE Integrated Software Environment
CLA Carry Look Ahead Adder
LUT Look Up Table

ii
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 DESIGN AND ANALYSIS OF LOW POWER APPROXIMATE MULTIPLIER USING 15:4 COMPRESSOR

CHAPTER-1
INTRODUCTION
1.1 INTRODUCTION TO APPROXIMATE ARITHMETIC UNIT

Arithmetic and Logic Units are the essential components of any digital Very
Large- Scale Integration (VLSI) system. Realizing efficient ALU is required for
better performance of a data path unit in microprocessors or Digital Signal
Processors (DSP). Data path element actually perform computational operations like
read/write to memory, arithmetic, logic operations, and numerical shift operations
with elements like adder, subtractor, logical, and the shifting units etc. All
microprocessors contain these elements in some form or another, satisfying price and
performance constraints. The adders and multipliers are also essential for digital
operations such as data conversions, filtering and convolutions in digital signal
processing etc. The ability of data generations decides the speed and operations of
every device. Among these multipliers are the significant elements that contribute for
the total delay and hardware complexity in CMOS logic design. Hence this research
concentrates on the design of multipliers suitable for data path systems.

The miniaturization of digital circuits generally can be achieved by either

reducing the size of transistor or by optimizing the gate count of the circuit. The first
approach extensively concentrates on transistor level designs. The latter approach deals with
the application of Boolean rules and it is accomplished by logical analysis of digital design.
The ultimate outcome is to have an area, power, delay optimized
architecture/approach that optimizes the circuit at gate level. Digital arithmetic in
logic design develops appropriate. algorithms in order to achieve an efficient
utilization of the available hardware. Since ultimately, speed, power and chip area are
the most often used measures of the efficiency of an algorithm in hardware aspects,
there is a strong link between the algorithms and technology used for its
implementation. VLSI system in digital signal processing, image processing adds
features through different types of algorithms for implementing multipliers and
adders to give better results in processors design.

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1.2 TYPES OF MULTIPLIERS IN VLSI

In digital system the multipliers are the most energy hungry blocks as they
are fundamental sub-system for digital signal processors; application based
embedded systems etc. Existing literatures introduce diverse multiplication methods
by providing novelty in Partial Product Generation (PPG), Partial Product Reduction
(PPR) and final addition to provide better performance in terms of area, power and
delay metrics. Generally for the multiplication of an n- bit multiplicand with an m bit
multiplier, m partial products are generated and product formed is n + m bits long. Recent
growths in processor design focus on low power multiplier architecture in most
cases. In VLSI design the main concentration is done to get higher speed, lower
cost, and less area. Taking into consideration these constraints, the design of low
power multiplier is of great interest. Many research efforts in the multiplier design
have been introduced to obtain energy efficiency in VLSI circuits. The various
multiplication algorithms normally used are discussed in the following subsections.

10101010 10101010

111000011100100 111000011100111

Accurate Output Approximate

Figure 1.1 Approximate arithmetic unit

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1.2.1 ARRAY MULTIPLIER

Array multiplier has regular and simple structure. This multiplier uses
repetitive addition and shifting to produce final product. Each partial product is
generated by the multiplication of the multiplicand with one multiplier digit. The
partial product are shifted according to their bit sequences and then added. The
summation can be performed with normal carry propagation adder. N-1 adders are
required where N is the no. of multiplier bits. Though the design time is less the array
multiplier has disadvantages like high power consumption and requires digital gates
resulting in large chip area in spite of its regular structure.
1.2.2 WALLACETREE MULTIPLIER
A fast multiplication of two numbers was developed by Australian computer
scientist Chris Wallace (1964). This method witnessed that it is possible to perform
the addition operations in parallel, resulting in less delay for multiplication. Parallel
addition of the partial product bits using a tree of carry save adders, also known as
―Wallace Tree¦ (WT). A Wallace tree is an efficient hardware implementation of a
digital circuit that multiplies two integers where partial product matrix is reduced to a
two-row matrix by using a carry save adder and the remaining two rows are summed using a
fast carry propagate adder to form the product. This is advantage for multipliers more
than 16 bits. WT increases speed because the addition of partial products is now. In
WT architecture, all the bits of all of the partial products in each column are added
together by a set of counters in parallel without propagating any carries. Another set of
counters then reduces this new matrix and so on, until a two-row matrix is generated.
Wallace method uses three-steps to process the multiplication operation.
1.2.3 DADDAMULTIPLIER
A hardware multiplier design invented by computer scientist Luigi Dadda(1965) . It
is similar to the Wallace multiplier, but it is slightly faster and requires fewer gates.
Dadda and Wallace multipliers have the same three steps for multiplication. Wallace
tree multipliers reduce as much as possible on each layer but Dadda multipliers
reduce the number of gates used and delay.

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1.2.4 BOOTH MULTIPLIER

An increasing number of high speed DSP applications have need of high precision
fixed or floating point multiplier suitable for VLSI implementation. In Modified
Booth multiplier partial products are added one at time using adder array whose final
results is obtained with a final carry propagate adder stage. Modified booth algorithm
reduces the number of partial products to be generated and is known as fastest
multiplication algorithm. Modified Booth multiplier performs both signed and
unsigned multiplications.
1.2.5 SEQUENTIAL MULTIPLIER
To multiply two binary numbers (multiplicand X has n bits and multiplier Y
has m bits) using single n bit adder, a sequential circuit that processes a single partial
product at a time and then cycle the circuit m times can be used. Sequential
multipliers are attractive for their low area requirement. In a sequential multiplier,
the multiplication process is divided into some sequential steps. In each step sequence of
partial products will be generated, added to the accumulated sum in the previous step,
and the partial sum will be shifted to align the accumulated sum with partial product of
next step. Therefore, each step in sequential multiplication consists of three different
operations viz., generating partial products, adding the generated partial products to
the accumulated partial sum, and shifting the partial sum. Figure 1 shows partial
product generation and addition in a sequential multiplier. Todays embedded
applications, mobile systems etc., depends on reduction of energy consumption. So
the proposed research focuses on design of efficient architectures using approximate
computing and compares the efficiency with accurate counterparts.
1.3 ROLE OF APPROXIMATE COMPUTING
Many scientific and engineering problems are computed using accurate, precise and
deterministic algorithms. However, in many applications involving signal/image
processing and multimedia, exact and accurate computations are not necessary,
because these applications are error tolerant and produce results that are good enough
for human perception. In these error resilient applications, a reduction in circuit
complexity, and thus area, power and delay is very important for the operation of a
circuit. Hence approximate computing can be used in error tolerant applications by

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reducing

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accuracy, but still providing meaningful results faster and with lower power
consumption. Many domains, like multimedia and big data analysis, exhibit an
intrinsic acceptance to a certain level of inaccuracies in computation. Functional
approximation in hardware mostly deals with the design of approximate arithmetic
units, such as adders and multipliers, at different abstraction levels, i.e., transistor,
gate, Register Transfer Level (RTL) and application. Approximate techniques are
needed to implement algorithms in image processing and video processing achieving
persistent, portable nature of electronic gadgets to tackle the present scenario of
increasing demand for ultra-low power consumption, small area, and high
performance objectives by compromising the accuracy.
Energy-efficient design techniques are addressed in many literatures at all levels of
design hierarchy. Schemes at lower level design process such as logic and circuit
levels are typically application-independent. At the algorithmic and architectural
levels, features are precise to a category of applications, and these lead to the
development of application specific energy. reduction techniques. The scaling of
CMOS technology plays a major role in reducing energy consumption of circuit.
The reduction in energy dissipation is also possible via voltage scaling. The amount of
voltage scaling is limited by the critical path delay of the architecture and the
throughput requirements of the application.
Moore‘s law states the transistors' need for VLSI design and gives the
experimental observation of component density and performance of integrated circuits,
which doubles every two years.
1.4 OBJECTIVE OF THE WORK
The main objective of this work is to design and implement a low-power
approximate Multiplier and implement a low-power approximate multiplier using a
15:4 compressor to achieve faster and more energy-efficient multiplication
operations. This project explores approximate computing, a paradigm that allows
controlled inaccuracies in favor of reducing power consumption, delay, and
hardware complexity—making it especially suitable for error-tolerant applications
such as image and video processing.
By incorporating novel approximate compressors, including modified 3:2 and 4:2

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compressors, and combining them into a 15:4 compressor structure, the design
significantly optimizes the partial product reduction stage of multiplication. To
enhance overall performance, the Kogge-Stone Adder (KSA) is used in the final
addition stage to minimize propagation delay and increase speed.
The proposed design aims to strike a balance between computational
accuracy, area, power efficiency, and speed. It is implemented using Verilog
HDL and synthesized on Xilinx Vivado tools to validate its functionality and
performance.
1.5 ORGANIZATION OF THE THESIS
Chapter 1 introduces the project by outlining the background, problem
importance of Efficient multiplication in VLSI systems, the need for low power
arithmetic units. Chapter 2 presents a detailed literature survey, highlighting
previous research in multiplier designs, approximate computing techniques, and
the role of compressor in optimizing performance.
Chapter 3 provides an introduction to the hardware and software tools used,
such as Xilinx Vivado, explaining their roles in simulation and synthesis the
proposed design.
Chapter 4 discusses the existing systems and standard compressor architectures
(such as exact 3:2 and 4:2 compressors), analyzing their structure, performance, and
limitations in low-power applications.
Chapter 5 describes the proposed method in detail, including the novel design of
the15:4 compressor using modified adders and 5:3 compressors, integration into a
multiplier, and the use of Kogge-Stone Adder for final addition.
Chapter 6 showcases the results obtained from simulation and synthesis,
providing a comparative performance analysis in terms of power, delay, and area
with tabulated results and thermal images.
Chapter 7 concludes the thesis with a summary of the research work, major
findings, and potential directions for future enhancements in approximate
multiplier designs for energy-constrained systems.

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CHAPTER-2
LITERATURE SURVEY
2.1 ADDER
Addition is a fundamental function in arithmetic operation; several adder designs
have been proposed for implementations in inexact computing. These adders show
different operational profiles; some of them are approximate in nature while others
rely on probabilistic features of nanoscale circuits. However, there has been a lack of
appropriate metrics to evaluate the efficacy of various inexact designs.
In this research work, parallel-prefix (PPx) adders are considered in comparison
to serial adders. The structure of serial adders is less complex but dissipates more
power. The addition in serial adders is executed sequentially, this is a time-consuming
process. To overcome this problem PPx adders are considered. In PPx adders, prefix
operation is done for efficient addition. PPx adders offer a solid theoretical foundation
for a variety of design trade-offs in terms of power consumption, speed, and area
utilization. Adders are a common circuit, and their regularity makes them an ideal
choice for VLSI synthesis, which may also be used to evaluate design trade- offs.
Figure 2.1 shows the flow diagram for computation stages of parallel-prefix adders.

Figure2.1: Different stages of Parallel-Prefix adder

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Andrew Kahng & Seokhyeong Kang (2012) proposed an area- error

optimized approximate adders in which accuracy can be configured during run time.
Evaluations revealed that area efficient variant demonstrated better power and delay
reductions at the expense of sacrifice in accuracy while the accuracy efficient
variant demonstrated better error reduction at the expense of high delay and power
dissipation.
Jinghang Liang et al. (2013) analysed the trade-off between performance and
error metrics of approximate adders that are reconfigurable between exact and inexact
modes. The error metrics considered are viz., Error distance, normalized error distance,
mean error distance.
Vaibhav Gupta et al. (2013) proposed a multibit adder targeting digital signal
processing applications in Discrete cosine transform and Finite Impulse Response
(FIR) filter. The proposed multi-bit adder incorporates various transistor designs of
approximate adder cells. Approximation is done in the full adder cells with logic
level changes at transistor level. Implementation results demonstrated significant area, and
power reductions of proposed adder based DSP systems compared to the standard
adder based DSP systems.
Muhammad Shafique et al. (2015) proposed a reconfigurable adder that can
work in variable approximation modes. The design incorporates an error correction
circuitry and it can be configured to vary the accuracy level of the proposed adder.
Experimental results demonstrated that the proposed reconfigurable adder exhibits lower
latency when compared to the state-of-the-art approximate adders. Functionality of
the proposed reconfigurable adder is verified with prototype on Xilinx Virtex-6
FPGA board.
Pawan Sonwane et al. (2015) proposed the design of low power inexact 4:2
compressor using approximation algorithm. The proposed inexact 4:2 compressor
trades-off accuracy at the benefit of power reduction. Analysis revealed that the
proposed design fair better when compared to prior designs.
Jothin & Vasanthanayaki(2018) proposed a High Performance Error Tolerant
Adders (HPETA) using Multiplexer Based Approximate Full Adder cells in the
inaccurate part. Simulations using Cadence Encounter with TSMC 90-nm ASIC
technology revealed that the proposed adder design exhibit high speed, low energy,
and less Area-Delay Product when compared to the recent previous approach.
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Ayad Dalloo et al. (2018) proposed a novel architecture for approximate adder
incorporating OR gates in the least significant part instead of full adder cells. The
OR gates in the least significant part not only reduces the gate count but produces better
accuracy compared to the other approximate logic based adder cells. Implementation
of the proposed methodology in an 8-bit approximate adder achieves improvement
in the mean squared error by 58.5%, compared to the previously reported best
architecture. Gnanambikai Palanisamy et al. (2019) proposed an error-tolerant
parallel adder with faithful approximation that can optimise area and accuracy. The
proposed adder performs parallel operation using carry select algorithm and utilizes
two variants of approximate full Adder cells in the least significant part. Evaluations
of the proposed approximate full adder cells are carried out by comparing with exact
full adder cell implemented adder. Evaluations revealed that exact full adder cell
implemented version perform better in accuracy while the approximate adder cells
implemented versions perform better in terms of power and area reductions. Driving
capability and functionality of the proposed parallel adders are verified with
implementations in digital image and digital signal processing applications.
2.2 COMPRESSORS
Hsiao et al. (1998) proposed a high-speed low-power full adder and 4–2
compressor targeting PP compression in multipliers. The proposed methodology
concentrates on the reduction of capacitance in the data-path of the arithmetic
elements. Performance evaluation in CMOS analog design environment revealed
that the proposed arithmetic units outperform in terms of power and delay reductions
in multiplier implementations compared to the prior multiplier designs.
Chang et al. (2003) proposed novel 4–2 and 5-2 compressors in CMOS
technology that can operate at ultra-low supply voltage. In the proposed approach
various architectures are proposed that incorporates either circuit level modifications
or gate level modifications. Pass Transistor Logic (PTL) was used to design the
proposed circuits to reduce area. However the weak driving capability of PTL was
overcome with PMOS-NMOS feedback transistors. Evaluations reveal that the
proposed arithmetic units are able to perform well in multiplier implementations in
terms of power reduction and driving capability.

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Chang et al. 2003) 4-2 compressor with the proposed XOR–XNOR module is
able to function at low supply voltage of 0.6 V, and outperform prior CMOS logic
compressors proposed in literature.
Minho ha & Sunggu Lee(2018) proposed low-power error- efficient
approximate multiplier targeting Digital Image Processing (DIP). The proposed
multipliers use new propose 4:2 compressor in few least significant columns and exact
4:2 compressor in the most significant columns. However the error due to
approximation in the least significant columns is reduced using error-recovery
modules. Evaluations revealed that the proposed multiplier out perform similar
designs in terms of power and error reductions.
Guo Y et al. (2018) proposed a low-error approximate multiplier by
employing new novel approximate compressors for PP compression. The error
percentage of the approximate multipliers are configured at run time using the
proposed compressors. Evaluations in CMOS SMIC 40nm process technology
revealed that the best accurate proposed multiplier demonstrate significant power, area,
and delay reductions compared to the standard Wallace tree multiplier. In addition the
functionality of the proposed approximate multipliers are verified with image
processing application.
Yen-Jen Chang et al. (2019) proposed fault-tolerant 4-2 compressor
targeting PP compression in the multipliers. The main significance of the proposed
work is that the proposed 4:2 compressors are configured based on the pattern
distribution of digital images considered in the application. The proposed
compressors and targeted multipliers are designed using 90nm CMOS technology
and simulations reveal that the proposed compressors and targeted multipliers
outperform state-of-the-art approaches in terms of power and error reductions.
Implementation of the proposed multipliers in digital image processing reveal
superior output image quality with better PSNR and SSIM metrics.
Ming-Roun Jiang et al. (1998) proposed a novel high-speed and low power
3- 2 counter and a 4-2 compressor for PP summation in array multiplier. Synthesis
results demonstrated less internal load capacitance that contributed for higher
speed and power performance than prior approaches.

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Radhakrishnan & A.P. Preethy (2000) proposed a transistor level CMOS 4-2
compressor targeting multiplier implementation. PTL is used to reduce area of the design
but at the expense of speed.
Jiangmin Gu & Chip-Hong Chang (2003) proposed a low power 4- 2
compressor at transistor level using low-power XOR-XNOR gate that is able to
operate with ultra- low supply voltage. Simulation results show that the proposed 4-
2 compressor demonstrate better performance compared to prior arts and is able to
operate at supply voltage as low as 0.6V.
Dursun Baran et al. (2010) proposed energy efficient 3:2 and 4:2 compressors.
The functionality of the proposed compressors are analysed with implementations in 16 bit
Booth and Non-Booth multipliers. Synthesis results demonstrated that Non-Booth
multipliers are more energy efficient compared to Booth counterparts.
Pourormazd M et al. (2011) proposed low power serial multiplier and serial
adder, combinational booth multiplier and shift/add multipliers, targeting design of
digital FIR filters. Synthesis results demonstrated that shift/add multiplier based FIR
filter exhibit better performance in terms of power dissipation and high speed
improvement. Momeni & Lombardi (2015) proposed novel approximate 4-2
compressors targeting PP reduction in multiplier. Extensive simulations with
implementations in Dadda multiplier revealed that the proposed designs perform
better in image processing applications. In addition the performance metrics revealed
that the proposed designs fair significant reductions in power dissipation, delay and
transistor count compared to standard design.
Omid Akbari et al. (2017), proposed approximate 4:2 compressors, that are
reconfigurable to work both in exact and approximate operating modes. In the
approximate mode, these dual-quality compressors provide better speed improvement and
dissipate less power.
The proposed compressors are employed for PP reduction in multipliers. Evaluations
with Dadda multiplier implementations with standard CMOS technology revealed
that the proposed multipliers achieve lower delay and power consumption in the
approximate mode. In addition implementations in image processing applications
revealed better processed images with high SSIM metric.

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Yi Guo et al. (2018) proposed probability –driven inexact compressors and

inexact half- adders targeting PP reduction in multipliers. Several error reducing
schemes are proposed to keep the error in the multiplier output within a fixed range.
Evaluations revealed that the proposed multipliers perform best in terms of error
minimization compared to the best of prior approximate designs and demonstrate
50.52%, 52.46%, 33.90% reduction in power, area and delay, respectively,
compared to the conventional counterpart.
Minho Ha & Sunggu Lee (2018) proposed approximate 4-2 compressors for
PP accumulation in a multiplier. Error recovery Modules are proposed and used to
reduce error due to approximate compressors in PP columns. The error in the proposed
multiplier is bound within range by use of an approximate compressor in least significant PP
columns and exact compressor in the most significant PP columns.
Karri Manikantta Reddy et al. (2019) proposed a novel approximate 4–2 compressor
and utilized it for PP accumulation in Dadda Multiplier. The proposed multiplier is
targeted for error-resilient applications in digital image processing. Evaluations in a
45 nm standard CMOS technology revealed that the proposed compressor realize a
significant reduction in error rate compared to the similar prior approximate designs, and
proposed multiplier achieved 35%, 36% and 17% reduction in power consumption,
delay and area respectively, compared to the conventional counterpart.
Implementations revealed that the proposed multiplier demonstrated nearly 90%
structural similarity in processed outputs compared to the output images processed
by conventional multiplier-based systems.
2.3 MULTIPLIERS

Zhongde Wang et al. (1995) proposed novel full and half adders for PP
compression in multipliers. Evaluations revealed that the proposed multiplier fair better
interms of area and node capacitance reductions. Implementations in higher end 2s
complement multiplier revealed their functionality and driving capability.
Guoping Wang & James Shield (2005) proposed an area efficient array
multiplier that exhibits better power and delay reductions. Evaluations
demonstrated that the proposed multiplier exhibit better performance compared to the
previous similar designs. Implementations revealed that the proposed scheme is
moresuitable for FPGA
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prototype development.
Chip-Hong Chang & Ravi Kumar Satzoda (2010) proposed a multiplexer
based array multiplier utilizing adaptive pseudo-carry generation circuitry with
least significant bit truncation. The adaptive pseudo-carry generation circuitry
demonstrates low average error compared to prior truncation multipliers.
Evaluations demonstrated that the proposed pseudo truncation array multiplier achieves
25% and 40% reductions in silicon area and dynamic power, respectively when compared
to conventional full-width multiplier for 32-bits in input operand. Also the
implementations in digital image processing systems revealed that the proposed
multiplier is able to produce output images with SSIM metric close to the
conventional multiplier based systems. a novel approach for multiplier that
engaged power, delay and accuracy metrics in design parameter. Evaluations
revealed that the proposed multiplier outperform peers in terms of power reduction
and speed improvement.

Chia-Hao Lin & Ing-Chao Lin (2013) proposed a inaccurate 4-2 counter and
implemented for PP reduction in Wallace multiplier. To reduce error due to
inaccurate compressors, Error detection and correction circuitry is incorporated in
Wallace multiplier. Experimental results demonstrated that the proposed multiplier
exhibit 10.74%, and 9.8% reductions in power.
Zervakis et al. (2015) proposed an area efficient approximate multiplier using
heuristic optimization technique for design evaluation viz., synthesis, simulation,
power and timing analysis. Experimental analysis revealed that the algorithm
optimized multiplier design is able to perform better when compared to the state-of-art
approaches. Evaluations reveal that the proposed multiplier able to realize power savings of
11% to 30% for variation in error bounds from small to large.
Srinivasan Narayanamoorthy et al. (2015) proposed a novel multiplier architectures
that can tradeoff computational accuracy with energy consumption. Simulations
revealed that the proposed multiplier consumes 58% less energy compared to the
standard multiplier with average computational error of not more than 1%. Implementations
in DSP applications revealed that the proposed multiplier perform close to standard design
and the error exhibited is noticeably tolerable.
Manjunath et al. (2015) proposed thedesign of16*16 Modified Booth multiplier

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with Carry Select Addition algorithm for PP accumulation. Evaluations revealed

that the proposed CSLA based MBE multiplier demonstrate minimum hardware,
and low power dissipation compared to the prior arts .
Suganthi Venkatachalam & Seok-Bum Ko (2017) Proposed an area efficient
multiplier using approximate compressor units for PP accumulation. Optimizations
in area and error metrics are achieved by varying logic depth in approximate
compressor based on probabilistic models. Synthesis results of area efficient and
error efficient variants of proposed multipliers revealed power savings of 72% and
38%, respectively, compared to the standard design. On an average, the proposed
area and error efficient variants exhibited mean relative error of 7.6% and 0.02%,
respectively, and it is significantly low compared to the prior approaches. Finally
implementations in digital image processing application, of the proposed models
achieved lowest MSE compared to other approximate design.
Ihsen Alouani et al. (2018) proposed a new architecture for parallel
multiplication that engages variants of approximate compressors for PP
accumulation. Design evaluation revealed that the multi variant approximate compressor
based parallel multiplier achieves better performance in power, area and delay metrics
coupled with error minimization when compared to the single approximate
compressor based multiplier and prior designs.
Aloke Saha et al. (2018) proposed a novel 7:3 counter for PP accumulation in
multiplier. Evaluations with standard 90nm CMOS process revealed superior performance
of the proposed multiplier in terms of Power- Delay-Product (PDP) compared to
the already reported designs. To the least, the proposed design exhibits 36% and
55% less PDP, compared to the best of the prior design for n-8 and n-16 in the
input bitwidth, respectively.
Suganthi Venkatachalam et al. (2018) proposed a novel approximate radix-4
Booth Multiplier incorporating probabilistic approach for PP generation and accumulation.
Evaluations revealed that the proposed multiplier achieves 41% area reduction and
49% power reduction compared to the conventional Booth multiplier. Analysis
with image processing applications revealed superior performance in terms of error
metrics compared to prior similar designs.

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VijeyaKumar et al. (2018) proposed a high speed and energy- efficient

error bound fixed width approximate multiplier for unsigned integers. The
proposed algorithm reduces error by addition of constant bias at the least
significant column of the exact part of multiplier. Moreover the proposed
multiplier employs parallel algorithm for PP generation to reduce overall delay.
Performance evaluations with structural VHDL model and synthesis with Synopsys
design compiler exhibits 66.19% and 36.2% reductions in Chip-Area Ratio (CAR
%) and PDP compared to the exact design for an 8X8 multiplication.

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COMPRESSOR

CHAPTER-3
DESIGN OF APPROXIMATE MULTIPLIER
Image processing and multimedia application can tolerate errors and can
provide meaningful results. Inexact (approximate) computing techniques have become
popular be- cause of its low complexity and less power consumption. Inexact
computing produces reasonable result; even it has low accuracy in those
applications. In these applications, multipliers for those applications.
Approximation can be applied to every stages of the multiplier. Normally,
approximation is applied in anyone stage at a time.
Error performance of the multiplier becomes worst when we apply
approximation in more than one stage at the same time. Multi-result. In literature,
researchers proposed several approximate multipliers (Kyaw et al. 2010, Bhardwaj et al.
2014, Lau et al. 2009, Venkatesan et al. 2011, Farshchi et al. 2013). Fig.2.11 shows the
various methodologies for approximate multiplier. In ap- proximate computing, the
value of error rate (ER), Error Distance (ED) and Normal-and Han Jie 2013). Among
these, NED is an invariant parameter for any approximate multipliers. Jiang et al.
(201б), compared the performance of various approximate multipliers. From the
results, use of compressors in the partial product tree gives the lowest error rate,
minimum normalized error distance and decent circuit metrics. This section reviews
on different approximate multipliers.

Figure 3.1:Methodology for approximate multiplier

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In this approach, generation of partial product is approximated to reduce the circuit

complexity and delay. This approach was introduced by Kulkarni et al. (2011). 2 2
bit multiplier was designed by altering the logic function of the multiplier. This
multiplier has 1б possible combination outputs. Out of 1б combinations, only one output
was altered. The Karnaugh map (K-map) of this multiplier is shown in Fig.2.12. Output
length of this accurate unsigned multiplier is 4 bits. Instead of using all four bits, three
Œth bit when it multiplying “11” and “11”. The actual answer for this input is
“1001”. Accurate multiplier uses four output bits to get this answer. Except this
output, remaining all other outputs can be represented with the help of three bits. From
the truth table, when “AlA0” and “BlB0” value are “ll” and “ll”, the output is forced
to set “lll”. This is the maximum possible output for 3 bit data (23-1 = 7).
3.1 RELATED APPROXIMATE COMPRESSORS
A compressor is a logic circuit which takes “N” bits as inputs from same or
different columns of the multiplier and generates a “Sum” and more than one
“Carry” bits as the output.

3.1.1 5:2 COMPRESSOR

Figure 3.2 :Block diagram of 5:2 compressor

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3.1.2 6:2 COMPRESSOR

Parandeh-Afshar et al. (2009) proposed this structure. This compressor takes six pri- mary
inputs “(E0, El, E2, E3, E4, and E5)” and two carry inputs from previous stages “(Cout0
and Coutl)” and delivers two primary outputs “(Sum, Carry)” and two adjacent carry
outputs “(Cout0 and Coutl)”. This structure was implemented with the help of full
adders. Fig. shows the implementation of б-2 compressor using full and half adders. Later,
(Ma and Li 2008) implemented the structure using one 4- 2 compressor and one gate and 4
XOR gate respectively. Dandapat et al. (2010) proposed and implemented the б-3
compressor using two full adders and parallel adders. This compressor is not popular
because it has the compression ratio of 2 whereas compression ratio of another proposed б-
2 compressor is 3 (Parandeh-Afshar et al. 2009). Higher compression ratio offers
minimum partial product reduction stages of the multiplier.

Figure 3.3 Block Diagram of 6:2 compressor

3.1.3 7:2 COMPRESSOR

This compressor has seven primary inputs along with two adjacent carry inputs.
It delivers two primary outputs and two adjacent carry to next stages of compressor.
Parandeh- Afshar et al. (2009) proposed the direct implementation of this
compressor. This implementation has delay of 7 XORs. Rouholamini et al. (2007),
Ma and Li (2008) rearranged the expression for 7-2 compressor and worst case delay is re-

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duced to б XORs. Also

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this structure provides less power consumption, PDP and delay.

Fig.3.4 shows the structure7-2 compressor proposed by (Rouholamini et al. 2007).

Figure 3.4: Block Diagram of 7:2 compressor

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3.1.4 7:3 COMPRESSOR

Mehta et al. (1991) proposed the 7-3 compressor which implements the logic
expressions of 7- 3 compressor. Dandapat et al. (2010) implemented the 7-3 compressor using
4-3 compressor and full adder. This implementation reduces 1 XOR gate delay. It
has the limitation of irregular layout in the synthesis. Fig.3.5 shows the design of
this proposed compressor. Veeramachaneni, Avinash, Krishna and
Srinivas(2007)Modi-MUXs. Worst case delay of this compressor is 1 XOR gate and
3 MUXs. Compressors proposed by (Mehta et al. 1991, Dandapat et al. 2010,
Veeramachaneni, Avinash, Krishna and Srinivas 2007) has the compression ratio of
2.33. But the compression ratio of proposed compressor is 3.5 (Parandeh- Afshar et al. 2009,
Rouholamini et al.2007, Ma and Li 2008).
Highest compression ratio value is preferable in the reduction tree.

Figure 3.5: Block diagram of 7:3 compressor

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CHAPTER-4
INTRODUCTION TO SOFTWARE TOOL

4.1 XILINX
The main tool required for this project is Xilinx-Vivado 2016.4 version. Xilinx is
a leading American technology company that specializes in the development of
programmable logic devices (PLDs), most notably Field- Programmable Gate
Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). It was
founded in 1984 by Ross Freeman, Bernard Vonderschmitt, and James V Barnett II,
and is widely recognized as the pioneer of FPGA technology. Xilinx's innovations
have significantly influenced the fields of digital design, embedded systems, and
VLSI, allowing designers to implement custom hardware circuits that can be
reprogrammed even after manufacturing.

The core product offered by Xilinx is the FPGA, which allows users to create
digital circuits that can be reconfigured according to specific application
requirements. Unlike traditional Application-Specific Integrated Circuits (ASICs),
which are fixed in functionality once manufactured, FPGAs provide the flexibility of
hardware reprogramming, making them ideal for prototyping, research, and real-
time system updates. Xilinx FPGAs are widely used in applications such as
telecommunications, automotive systems, aerospace, defense, artificial intelligence,
and industrial automation.

Xilinx provides a comprehensive software suite called Vivado Design Suite,

which is used for designing, simulating, synthesizing, and implementing FPGA-
based systems. Vivado supports high-level synthesis (HLS), allowing users to design
hardware using C, C++, and System Verilog, which are then converted into
hardware description languages (HDLs) like Verilog or VHDL. This speeds up
development and makes FPGA programming accessible to a wider audience. Xilinx
also offers the older ISE Design Suite, mainly used for smaller or legacy FPGA
devices.

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In recent years, Xilinx has introduced advanced families of FPGAs, such as

the Zynq UltraScale+ MPSoCs and Versal ACAPs (Adaptive Compute Acceleration
Platforms), which integrate programmable logic with embedded processors, GPUs,
and AI engines on a single chip. These devices are designed to meet the performance
needs of next-generation applications like machine learning, edge computing, and
5G networks.

In 2020, Xilinx was acquired by AMD (Advanced Micro Devices), further

expanding its reach and innovation capabilities in the semiconductor and computing
industries. The combination of Xilinx’s flexible hardware and AMD’s high-
performance computing solutions is expected to drive the development of cutting-
edge technologies in the years to come.

Overall, Xilinx continues to be a major force in the world of programmable

logic, enabling designers to create highly efficient, customized digital systems with
the flexibility and scalability demanded by modern electronic applications.

4.2 INTRODUCTION TO XILINX ISE

Xilinx Integrated Software Environment (ISE) is a complete design suite

brought to life by Xilinx, Inc. for synthesis, simulation, and implementation of the
FPGA (Field-Programmable Gate Array) and CPLD (Complex Programmable Logic
Device) designs. This is a user-friendly environment for HDL or hardware
description language-based development, in conjunction with the Verilog and
VHDL. The design entry, synthesis, optimization, place-and-route, timing analysis,
and generation of bitstream all have tools in this Xilinx ISE making it an essential
platform for digital circuit design.

Xilinx ISE is known for one of its powerful features. The GUI (graphical
user Interface) includes functions for managing projects, analyzing design
constraints, as well as debugging circuits. It further has Integrated ModelSim for
simulation purposes to further verify digital designs before being drawn to hardware
realization. Besides, there is Hardware Co-Simulation offered by Xilinx ISE that
allows testing in real- time for the FPGA-based systems.

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Unfortunately, Xilinx ISE, as a replacement for Vivado Design Suite on

the modern FPGA families, continues to be used mostly for legacy device
spanning.
Xilinx ISE offers a user-friendly GUI that simplifies project navigation, code
debugging, and constraint management. In this project, Xilinx ISE 14.5 is used to
simulate and synthesize the proposed 16×16 Wallace Tree multiplier architecture
using the Kogge Stone Adder and approximate 15-4 compressors. The tool provides
detailed reports on device utilization, timing analysis, and power estimation, making
it highly effective for both academic and industrial applications in digital system
design
Xilinx ISE provides extensive support for analyzing the performance of the
design through timing reports, device utilization summaries, power estimation tools,
and waveform viewers. These tools help designers to refine their design for optimal
results in terms of speed, area, and power.
In the context of this project, Xilinx ISE 14.5 is used to design, synthesize,
and simulate a 16×16 Wallace Tree multiplier using approximate 15-4 compressors
and a Kogge Stone Adder. The tool assists in verifying the functional accuracy of the
design, analyzing device resource utilization, and generating a bitstream for FPGA
implementation.
Overall, Xilinx ISE is a robust and feature-rich platform that supports the
entire digital design flow, making it an essential tool for developing high-
performance and efficient digital systems from the Spartan to the Virtex and also in
Cool Runner series.

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It has landed quite popular in various institutions in the academia and because of the
small FPGA projects majorly due to the stability it maintains and compatibility with
outdated hardware used during implementation. Overall, Xilinx ISE has contributed
heavily towards putting together VLSI design and digital system development, with
the provision of a powerful platform for designing and testing FPGA applications.

4.3 XILINX SOFTWARE

Xilinx Software is defined as a number of tools developed by Xilinx, Inc.,

for the design, simulation, and implementation of applications based on FPGA
(Field- Programmable Gate Arrays), CPLD (Complex Programmable Logic
Devices), and SoC (System-on-Chip). Integrated for an environment for hardware
design, verification, and deployment, the software tools are an important facet of
VLSI (Very Large-Scale Integration) design and embedded system development.
Some key Xilinx software tools are:

 Xilinx ISE [Integrated Software Environment]- A complete design suite for

the development of FPGAs and CPLDs with tools for design entry, synthesis,
place-and-route, timing analysis, and hardware debugging. While now
regarded as "legacy software," ISE is still widely in use for older FPGA
families like Spartan and Virtex series.
 Vivado Design Suite- A more advanced and modern tool, is a replacement for
ISE for newer FPGA architectures. Vivado incorporates High-Level Synthesis
(HLS), block-based design entry, advanced timing analysis, and system-level
integration tools for SoCs. It is targeted toward the development of high-
performance FPGAs and is used in hardware-accelerated applications in AI,
IoT, and signal processing.

 Vitis Unified Software Platform- A tool designed for software development

and hardware acceleration of applications in Xilinx devices. With Vitis, users
can develop applications in C, C++, and Python and integrate them with
frameworks like TensorFlow for AI-based FPGA designs.
 ModelSim and Vivado Simulator- Tools used to perform functional and
timing simulation of digital circuits written in Verilog and VHDL, which help

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verify the design before actual hardware implementation.

The Xilinx tools have found application in digital system design, embedded
computing, and telecommunications and HPC. Designing tools among FPGA
recharge will be evolved to provide a robust solution to power-efficient, high-speed,
and scalable development, which is a prerequisite for hardware design today
4.3.1 CREATING A NEW PROJECT

Xilinx Tools can be started by clicking on the Project Navigator Icon on the
Windows desktop.
1. Select Vivado 2016.4 as shown below.

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2. Click on 'Create New Project'.

3. Select 'Next'.

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4. Choose appropriate project name and project location

5. Select RTL Project and tick on 'Do not specify sources at this time'

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6. Make New Project as shown below and select the last row and click Next

7. Click Finish

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8. Select Add Sources

9. Select Add or create design sources and Next

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10. Select Create File

11. Select File type as Verilog and give appropriate 'File name'

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12. Select Finish

13. Add I/O ports and click OK

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14. Double click on file created

15. Complete the program

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Simulation:
16. Click ‘Run Simulation’

17. Run Simulation

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4.4 ABOUT VERILOG

Verilog is a hardware description language (HDL) used for designing,
modeling, and verifying digital circuits and systems. It was introduced in 1984 by
Gateway Design Automation and later became an IEEE standard (IEEE 1364).
Verilog enables engineers to describe the functionality of digital circuits at different
levels of abstraction, making it an essential tool in Very Large-Scale Integration
(VLSI) design.
In modern digital design, Verilog helps in developing complex circuits by
providing a structured way to describe hardware components. It allows designers to
write code that defines how a circuit should function before its physical
implementation. This reduces design errors, speeds up development, and enhances
the efficiency of digital systems.
Verilog supports three major levels of abstraction: behavioral, dataflow, and
structural. The behavioral level describes how a circuit should work using high-
level constructs like always and if-else statements. The dataflow level focuses on
how data moves between components, using continuous assignments and logical
operations. The structural level represents a circuit in terms of interconnected logic
gates and components, resembling the actual hardware layout.
One of the most powerful features of Verilog is its concurrency, which
allows multiple operations to execute simultaneously, just like real hardware. The
language also includes event-driven simulation, where changes in signals trigger
circuit behavior, making it ideal for designing sequential circuits. Additionally,
Verilog supports modular design, allowing designers to break complex systems into
smaller, reusable modules for easier debugging and testing.
A Verilog program is composed of modules, which define the functionality
of a circuit. Modules contain input and output ports, internal signals, and a
description of how the circuit operates. Verilog also provides operators for
arithmetic, logical, and bitwise operations, as well as procedural blocks like always
and initial for sequential execution. The language includes timing controls such as
#delay and @(posedge clk), which help model the behavior of circuits over time.

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Verilog is widely used in the semiconductor industry for designing and

verifying digital circuits, including microprocessors, memory chips, and digital
signal processors (DSPs). It plays a crucial role in developing Field-Programmable
Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). The
ability to simulate hardware behavior before fabrication helps reduce costs and
improve system reliability.
Verilog remains one of the most important languages for digital circuit
design and verification. Its ability to represent hardware at different abstraction
levels, support for simulation, and modular structure make it an essential tool for
VLSI engineers. As technology advances, Verilog continues to evolve, supporting
new design methodologies and improving efficiency in digital system development.

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CHAPTER-5
EXISTING METHOD
5.1 BLOCK DIAGRAM OF EXISTING METHOD

Figure 5.1. Block diagram of Han-Carlson adder

There are three primary steps in parallel multipliers. The formation of partial
products is the first stage, which is carried out by AND gates. The second stage is
the reduction of the partial products which can be done by using approximate novel
compressors. The final addition of the partial products is done using approximate
Han- Carlson parallel prefix adder , in the third stage. The second stage, out of the
three, is the most power-hungry stage. As a result, enhancing the second stage
improves the multiplier's performance while lowering its cost. As the bit-width of
approximated Han- Carlson parallel prefix adder increases the power consumption and
area utilization is also double when compared with the previous bit-width. In
approximate Han-Carlson parallel prefix adder the power and area are increasing
exponentially. The implementation of the proposed approximated multiplier using
novel compressors and parallel-prefix adder increases the performance of the circuit.
In this paper, the authors implemented architectures of the approximate multiplier by
using the approximate Han-Carlson adder and multiplier using a novel compressor.

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5.2 EXISTING COMPRESSORS

5.2.1 3:2 COMPRESSOR
A 3:2 compressor is a fundamental building block used in high-speed
arithmetic circuits, especially in multipliers and adders. It is designed to reduce three
input bits into two output bits, optimizing the carry propagation and improving
overall performance in digital circuits.

Figure 5.2 Block diagram of 3:2

compressor Architecture of 3:2 Compressor

A 3:2 compressor takes three input bits (X, Y, Z) and compresses them into
two output bits, a Sum (S) and a Carry (C), similar to a full adder but optimized for
parallel computations. Table of 3:2 Compressor
Logic Equations

The 3:2 compressor outputs can be defined as:

Sum (S) = X ⊕ Y ⊕ Z

Carry (C) = Majority(X, Y, Z) = (X·Y) + (Y·Z) + (X·Z)

This structure is similar to a full adder, but in compressor-based designs, multiple

compressors are cascaded for efficient parallel computation in multipliers.

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Operation of 3:2 Compressor

The 3:2 compressor is widely used in multipliers and multi-operand adders.

Instead of processing addition serially, it reduces three bits to two, allowing
multiple compressors to operate in parallel, significantly improving speed.
Wallace Tree or Dadda Tree multiplier, multiple 3:2 compressors are used to
minimize partial product stages, reducing delay.
Compressors help in designing low-power and high-speed arithmetic circuits
in VLSI applications.
Advantages of 3:2 Compressor

• Reduces Carry Propagation Delay – allows faster addition in multipliers

and accumulators.

• Improves Speed – Reduces the number of logicstages comparedto traditional adders.

• Efficient for Large Bit-width Arithmetic – Commonly used in high-

performance multipliers (e.g., Wallace and Dadda Trees).

• Scalable Design– Can be extended to higher-order compressors (e.g., 4:2,

5:2, etc.) for further efficiency.

Disadvantages of 3:2 Compressor

• More Hardware than a Basic Adder– Requires extra logic gates compared
to simple adders.
• ImplementationComplexity– Need optimized VLSI layout to
minimize power and area consumption.
• Not Ideal for Small Circuits– More beneficialinhigh-speed applications
rather than basic arithmetic operations.
5.2.2 4:2 COMPRESSOR

A 4:2 compressor is a specialized digital circuit commonly used in high-

speed arithmetic operations like multiplication and addition. It plays a crucial role in
hardware implementations of multipliers, especially in Wallace tree and Dadda tree
architectures,
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which. aim to reduce the time delay in summing partial products. The name "4:2
compressor" indicates that it takes 4 primary inputs (A, B, C, D) and 1 carry-in
(Cin) from the previous stage, and produces 2 outputs — a sum and a carry, along
with a carry-out (Cout) to the next significant bit position.

Figure 5.3 Blockdiagram of4:2 compressor

Operation of 4:2 Compressor:

The main function of a 4:2 compressor is to compress five input bits (A, B, C, D,
Cin) into three outputs (Sum, Carry, Cout). This operation is typically done in two
stages:
1. First, three inputs (say A, B, and C) are fed into a full adder
to produce an intermediate sum and carry.
2. Second, this intermediate sum is added to the remaining input (D) and
the carry- in (Cin) using another full adder.
3. The final outputs are:

Sum: theresult of the second full adder.

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 Carry: the carry from the second adder (fed to the same bit position in the next
stage), Cout: the carry from the first full adder (propagated to the next higher bit
position). This parallel processing reduces the number of logic levels and increases
the speed of computation.
Advantages of 4:2 Compressor:
• Parallelism: Allows multiple operations to occur at once, improving
overall performance.

• Hardware Optimization: Reduces the number of components needed in a multiplier

tree, making it more compact.

Disadvantages of 4:2 Compressor:
• Complex Design: More complicated than basic adders like half and full adders.
• Increased PowerConsumption: Due to more gates and switching activity.
• Difficult Debugging: Analyzing and tracing errorsinthe circuit is harder
compared to simple arithmetic units.
• VLSI Challenges: In large-scale integration, routing and placement
of compressor circuits can be challenging.

5.2.3 HAN-CARLSON ADDER

The Han-Carlson Adder (HCA) is a parallel-prefix adder that efficiently balances
speed, power consumption, and area complexity. It is a hybrid design that takes
inspiration from the Kogge-Stone Adder and Brent-Kung Adder, aiming to reduce
wiring congestion while maintaining a high-speed addition process.

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Figure 5.4 Han-carlson

adder ARCHITECTURE OF HAN-CARLSON

ADDER
The Han-Carlson Adder consists of three main stages:

4. Generateand Propagate Calculation (G/P Stage)

 Each bit of the two input numbers generates G (Generate) and P

(Propagate) signals based on:
Gi=Ai⋅Bi
Pi=Ai⊕Bi
 These signals help determine whether a carry will be generated or propagated at
each bit position.

5. Parallel-Prefix Computation (Carry Propagation Stage)

 The carry computation process is structured in a way that blends the fast parallelism
of Kogge-Stone with the efficient serial structure of Brent-Kung.

 It starts with a fully parallel prefix network in early stages (similar to Kogge-
Stone) and transitions to a more serial structure in later stages (like Brent-
Kung).

6. Final Sum Computation (Sum Stage)

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 Thesum is computed using the carry signals and the propagatesignals through:

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Si=Pi⊕Ci−1
 This step finalizes the addition process, providing the correct sum output.
Operation of Han-Carlson Adder

The Han-Carlson Adderworks in the following steps:

1. Input Stage

 The input binary numbers are processed to generate the G

(Generate) and P (Propagate) signals.
2. Carry Computation Stage

 The carry network processes carry signals using a hybrid prefix tree.
 It uses parallel prefix computation in early stages
to quickly generate intermediate carries.
 In later stages, a more serial and structured approach is used to
reduce wiring complexity.
3. Sum Computation Stage
 Once all carry bits arecomputed, the final sum is obtained using
an XOR operation with the propagate signals.
Advantages of Han-Carlson Adder

Speed Optimization

• Provides faster addition than Brent-Kung Adder and is close in speed to Kogge-Stone.

• The hybrid prefix structure ensures efficient carry propagation.

• Lower Wiring Complexity

• Reduces the number of interconnects compared to Kogge-Stone, lowering wirings

• Congestion Power and Area Efficiency.

• Uses fewer logic gates than Kogge-Stone, making it more power-efficient.

• The hybrid prefix approach leads to a good balance between speed and area

usage. Scalability
• Suitable forlarge-bit-width additions, making it ideal for VLSI designs and ALUs.
• Work swell in high-performance computing environments.

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Disadvantages of Han-Carlson Adder

More Complex than Brent-Kung
• While optimized, it still requires more gates than the Brent-Kung Adder, making
it less area- efficient.
Higher Power Consumptionthan RCA or CLA
• Even though it is more efficient than Kogge-Stone, it still consumes more power than

simpler adders like Ripple Carry Adder (RCA) or Carry Look-Ahead Adder
(CLA).
Implementation Complexity
• Thehybrid prefix tree structure requires careful design, making it slightly
harder to implement in comparison to simpler adders.

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CHAPTER- 6
PROPOSED METHOD
6.1 INTRODUCTION TO PROPOSED MULTIPLIER
Multiplier has become the most significant portion of the digital circuits which carries the
majority of operation at system level. It is a circuit utilized in digital electronics,
kind of a computer, to multiply two binary numbers. Binary adders are used
construct a multiplier. An effective multiplier ought to have the subsequent
features:
• Accuracy :An efficient multiplier have got to produce proper results.
• Speed: Multiplier must achieve operations at tremendous speed.
• Area: A multiplier must cover a lesser amount of slices and LUTs.
• Power: Multiplier ought to use minimum
power. There are number of multipliers and some of
them are:
1. Booth multiplier,
2. Array based multiplier
3. Wallace tree structure multiplier,
4. Combinational circuit multiplier,
5. Sequential circuit multiplier.
A WTM is an effective hardware which makes use of electronic circuit that products numbers.
In this design, a Wallace tree multiplier since it has the advantages of superior
processing speed and minimal power utilization.
There are three stages for a multiplication process usually occurs are:
1. Generation of Intermediate partial products
2. Reduction of them
3. Additionat the end.

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6.2 PROPOSED COMPRESSOR

6.2.1 5:3 COMPRESSOR
A 5:3 compressor is a digital circuit widely used in high-speed arithmetic operations such as
multiplication and accumulation, particularly in applications involving digital
signal processing (DSP) and image processing. The main objective of a
compressor is to reduce the number of partial products in a multiplier or to
compress multiple inputs into fewer outputs while minimizing delay and power
consumption.

Figure 6.1 Block Diagram of 5-3 compressor

Advantages of 5:3 Compressor

1. ReducesAddition Stages – Compressesmultiple bits in a single step,
reducing the number of required adders.
2. Faster Computation – Decreases propagation delay compared to conventional adders.

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3. Efficient Multiplier Design– Used in high-speed multipliers to

optimize the partial product summation.
4. Lower Power Consumption – Reduces the number of
transitions in arithmetic circuits, leading to power savings.
5. Better Hardware Utilization – Saves area by replacing multiple full adders
with a single compressor.
Disadvantages of 5:3 Compressor
1. Increased Complexity – More complex logic gates comparedto standard full adders.
2. HigherWiring Overhead– More interconnections can lead to routing
congestion in ASIC and FPGA implementations.
3. Difficult Timing Optimization – Delays vary depending on the logic
levels, requiring careful design.
4. Not Always Optimal for Small Circuits – Overhead may not justify its use in
low- power, small-scale applications.
5. Potential Glitches – In asynchronousdesigns, timing variations can
cause glitches affecting performance.

6.2.2 15:4 COMPRESSOR

A 15:4 compressor is a high-performance digital circuit used primarily in the partial
product reduction stage of fast multipliers such as Wallace Tree or Dadda multipliers.
Its main function is to compress 15 input bits into 4 output bits, significantly reducing
the complexity and delay of arithmetic operations in large-bit multipliers. This is
especially critical in high-speed applications such as image processing, digital signal
processing (DSP), and real-time computing systems.
Advantages of 15:4 Compressor
1. Faster Computation – Reduces the number of addition stages, leading to
lower delay.
2. Efficient Area Usage– Uses fewer logic levels than ripple adders,
making it more compact.
3. Reduced Power Consumption – Since fewer additions are needed,
dynamic power consumption decreases.
4. Better Pipelining – Facilitates high-speed arithmetic designs by reducing

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propagation delays.
5. Improved Performance in Multipliers – Useful in Wallace Tree and
Dadda multipliers for faster accumulation of partial product.

Disadvantages of 15:4 Compressor

1. Complex Design – Requires more logic gates compared to simpler adders.

2. Higher Wiring Overhead – Increased interconnections can lead to
routing congestion.
3. More Power for Small Designs – Not always optimal for low-power
applications due to added control logic.
4. Difficult Implementation – Mayrequireadvanced circuit techniques for
efficient layout in ASIC or FPGA.
5. Propagation Delay Variability – The delayis not always
uniform, affecting timing analysis in high-frequency circuits.
6.3 PROPOSED ADDER

6.2.3 KOGGE STONE ADDER

The KSA is one of the well-known parallel prefix adder. KSA is found to be the fastest in terms
of addition in design perspective. The KSA acquires extra area when compared to
Brent–Kung adder, but KSA has lesser fan-outs at each phase, which rises execution.
In this design, a 4-bit KSA is used. These type of Adders are mostly categorized in 3
types.
A. Pre-processing stage

B. CarryGeneration section

C. Final processing or post-processing.

Figure 6.2 Functions of basic KSA

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Stages of Kogge-Stone Adder Architecture

The architecture consists of three main stages:
1. Pre-Processing Stage (Generate & Propagate Calculation)
Each bit iii of two input binary numbers AAA and BBBgenerates two signals:

• Generate: Gi=Ai⋅Bi (Indicatesifa carry is generated at bit 1)

• Propagate: Pi=Ai⊕Bi (Indicates if a carry is propagated)

2. Prefix Processing Stage (Carry Computation)

• The carries are computed in a hierarchical manner using a tree structure.

• Uses black and gray cells to compute the carry signals:

o Black Cells: Compute both generate and propagate values.

o Gray Cells: Computeonly generate values.
• The carry signals are computed using:
• The tree-based computation reduces the carry propagation delay to O(log N).

3. The sum bits are computed using :Post Processing Stage(Sum

Calculation) SiPi⊕Ci−1

WhereCi−1C_{i-1}Ci−1 is the carry computed in the prefix stage.

Figure 6.3 Block Diagram of KSA

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CHAPTER -7

RESULT AND DISCUSSION

7.1 Code for 16-bit proposed multiplier

modulefifteen_4_approx(x,sum); input
[14:0]x; output [3:0]sum; wire [4:0] s,c;
wire[2:0]p,q; wire c1,c2,c3; wire[3:0]a,b;

fa_approx fa1(x[0],x[1],x[2],s[0],c[0]);
fa_approx fa2(x[3],x[4],x[5],s[1],c[1]);
fa_approx fa3(x[6],x[7],x[8],s[2],c[2]);
fa_approx fa4(x[9],x[10],x[11],s[3],c[3]);
fa_approx fa5(x[12],x[13],x[14],s[4],c[4]);

five_three_comp_approx c1000(p[2],p[1],p[0],s[4],s[3],s[2],s[1],s[0]);
five_three_comp_approx c20(q[2],q[1],q[0],c[4],c[3],c[2],c[1],c[0]); assign
a[0]=p[0];
assign a[1]=p[1];
assigna[2]=p[2];assigna[3]=1'b0;assignb[0]=1'b0;assignb[1]=q[0];
assign b[2]=q[1];
assign b[3]=q[2];
koggeK1(a[3:0],b[3:0],1'b0,sum); endmodule

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7.2 Implementation of 16-bit results

Figure 7.1 simulation Result 16-bit multiplier

Figure 7.2 Schematic Diagram of 15:4 compressor

Figure 7.3 Delay report of 16-bit multiplier

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The total delay of the paths ranges from 21.665 ns to 22.739 ns, with net
delay contributing the majority of this delay—approximately 15.6 to 16.7 ns. Logic
delay values are relatively moderate, ranging from around 5.8 to 6.4 ns. The high net
delays suggest that routing or interconnects are causing significant delay, which could
be due to long wire lengths, high fan-out, or suboptimal placement. These paths may
not be critical to the timed portions of the design, but if left unconstrained, they can
become a source of unexpected timing issues.
The critical parameters observed in the report include Total Delay, Logic
Delay, and Net Delay. The total delay across these paths ranges approximately from
21.66 ns to 22.73 ns, with the net delay—representing routing and interconnect delays—
constituting the majority of the path delay. The logic delay, which accounts for the
delay due to combinational elements like gates, ranges from
5.88 ns to 6.42 ns, whereas net delay lies between 15.64 ns and 16.69 ns.
The dominance of net delay indicates that these paths are heavily influenced by
routing congestion, long wire lengths, or high fan-out, which may lead to
suboptimal timing performance.

Figure 7.4 power report for 16-bit multiplier

The power analysis derived from the implemented netlist, reveals a total on-
chip power consumption of 3.779 W. This power is predominantly dynamic in
nature,

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accounting for 3.701 W (98%), while the remaining 0.078 W (2%) is attributed to
static or leakage power. A detailed breakdown of the dynamic power indicates that
the I/O components consume the majority, drawing 3.415 W, which constitutes
approximately 92% of the dynamic power. Signal switching contributes 0.182 W (5%),
and internal logic operations consume 0.104 W (3%). The dominance of I/O power

highlights significant switching activity at the interface level, which could stem
from high toggle rates or strong drive strengths required for off-chip
communication. The thermal profile shows a junction temperature baseline of 0.0°C,
with a thermal margin of 85.0°C, and an effective thermal resistance (θJA) of
4.6°C/W.
In conclusion, by replacing the Han-Carlson Adder with the Kogge-Stone Adder has
improved the overall speed due to faster carry propagation, as evident from reduced
logic delays. However, this comes with increased power consumption, particularly
I/O power, and higher net delays due to complex routing. The Kogge-Stone Adder is
ideal for performance-critical designs, while the Han-Carlson Adder may still be
preferred in power- or area-sensitive applications. Thus, the choice depends on the
specific trade-offs between speed, power, and area.

7.3 Comparison of existing and proposed compressors

Compressor LUT IBUF OBUF Cells Dynamic Static Chip

Type power(W) power(W) power(W)

3:2(Exact) 2 3 2 7 0.900 0.120 1.02

4:2(Exact) 3 5 3 11 1.545 0.135 1.68

5:3 3 5 3 11 1.483 0.078 1.562

15:4 8,4,8 15 4 39 3.701 0.078 3.779

Figure 7.5 Comparison of exact compressors

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Compressor LUT IBUF OBUF Cells Dynamic Static Chip

Type power(W) power(W) power(W)
3:2(Approx) 2 3 2 7 0.712 0.116 0.828
4:2(Approx) 2 4 2 8 0.995 0.122 1.11
5:3 3 5 3 11 1.483 0.078 1.562
15:4 8,4,8 15 4 39 3.701 0.078 3.779

Figure 7.6 Comparison of approximate compressor

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CHAPTER-8

CONCLUSIONANDFUTURE SCOPE
The design and implementation of a low-power approximate multiplier
using a 15:4 compressor have demonstrated a promising balance between performance
efficiency and power reduction. By incorporating approximation techniques within the
compression stage, the proposed design achieves substantial improvements in power
consumption and area optimization while maintaining acceptable computational accuracy
for error-tolerant applications. The use of the 15:4 compressor effectively reduces the
critical path delay and logic complexity compared to traditional multiplication
architectures, leading to faster and more energy-efficient operations. Simulation results
confirm that this multiplier is well-suited for applications in image processing, machine
learning, and IoT devices, where low power and high speed are prioritized over
exact arithmetic precision. Overall, the proposed approach validates the potential of
approximate computing in modern VLSI systems, offering a scalable and practical
solution for energy- aware digital arithmetic units.
The proposed architecture is based on array structure. The design
depends on the approximate compressors as well as adders. The speed of design
mainly depends on the speed of compressors and the parallel prefix adder i.e., KSA.
The total process is designed by using Verilog HDL and synthesized on Xilinx Vivado.
The Output and RTL Schematics are observed on the tool. These dependencies carry
important information about the structure of the objects in the visual scene. Luminance
masking is a phenomenon whereby image distortions (in this context) tend to be less
visible in bright regions, while contrast masking is a phenomenon whereby distortions
become less visible where there is significant activity or "texture" in the image.

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COMPROSSER

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29. Suganthi Venkatachalam, Hyuk Jae Lee & Seok-Bum Ko 2018, Power efficient
approximate booth multiplier’, IEEE International Symposium on Circuits and
Systems (ISCAS), Florence, Italy.
30. IhsenAlouani, HamzehAhangari, Ozcan Ozturk & Smail Niar 2018, A novel
heterogeneous approximate multiplier for low power and high performance’,
IEEE Embedded Systems Letters, vol. 10, no.2, pp. 45-48.
31. lokeSaha, Rahul Pal, B, Akhilesh, G, Naik & Dipankar Pal 2018, Novel CMOS
multibit counter for speed-power optimization in multiplier design’, AEU -
International Journal of Electronics and Communications, vol. 95, pp. 189-198
32. VijeyaKumar, KN, Elango, S & Kalaiselvi, S 2018, VLSI implementation of
high- speed energy-efficient truncated multiplier’, Journal of Circuits, Systems
and Computer, vol. 27, no.5. pp.1850077
33. Bhardwaj (2014) wallace tree multiplier for error-resilient systems in
International Symposium on Quality Electronic Design pp. 2б3–2б9.

34. Lau M. S. K. Ling K.-V. and Chu Y.-C. (2009) Ener gy-aware probabilistic
multiplier: design and analysis in Proceedings of the international conference on
Compilers architecture and synthesis for embedded systems pp. 281–290.

35. Venkatesan R. Agarwal A. Roy K. and Raghunathan A. (2011) Macaco: Modeling

and analysis of circuits for approximate computing in proceedings of international
conference on Compilers architecture and synthesis for embedded systems pp.
667– б73.

36. Farshchi F. Abrishami M. S. and Fakhraie S. M. (2013) New approximate

multiplier for low power digital signal processing in 8th Midwest Symposium on
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37. Jinghang Liang, Jie Han & Fabrizio Lombardi 2013, New metrics for the
reliability of approximate and probabilistic adders’, IEEE Transactions on
Computers, vol. 62, no.9, pp. 1760-1771.

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38. Dandapat A. Ghosal S, Sarkar P and Mukhopadhyay D (2010). 1.2-ns16 x 16- bit binary
multiplier using high speed compressors International Journal of Electrical and
Electronic Engineering 4(3) 485–490.

39. Rouholamini M. Kavehie Omid Mirbaha A. P. Jasbi S. J. and Navi K. (2007) A

new design for 7:2 compressors in IEEE/ACS International Conference on
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41. Veeramachaneni S. Krishna M K. Avinash L. Puppala S. R. and Srinivas M. B.

(2007) Novel architectures for high-speed and low-power 3-2 4-2 and 5-2
compressors in 20th International Conference on VLSI Design and 6th
International Conference on Embedded Systems pp. 324–329.

42. Minho, ha & Sunggu, Lee 2018, Multipliers with approximate 4-2 compressors
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 DESIGN AND ANALYSIS OF LOW POWER APPROXIMATE MULTIPLIER USING 15:4
COMPROSSER

APPENDIX
modulewallace_approx(A,B,z); input
[15:0]A,B;
output wire [32:0]z;
wire [14:0] t0,t1,t2,t3,t4,t5,t6,t7;
wire[3:0] n0,n1,n2,n3,n4,n5,n6,n7; reg[15:0]
pp0,pp1,pp2,pp3,pp4,pp5,pp6,pp7,pp8,pp9,pp10,pp11,pp12,pp13,pp14,pp15; wire
[76:0]i;
wire [109:0]s;
wire [44:0] r;
wire [54:0] g;
wire [51:0] l;
wire [9:0] c;
//partialproduct generation
integer j;
always@(Aor B) begin
for(j=0;j<16;j=j+1)
begin
pp0[j] <= A[j] & B[0];
pp1[j] <= A[j] & B[1];
pp2[j] <= A[j] & B[2];
pp3[j] <= A[j] & B[3];
pp4[j] <= A[j] & B[4];
pp5[j] <= A[j] & B[5];
pp6[j] <= A[j] & B[6];
pp7[j] <= A[j] & B[7];
pp8[j] <= A[j] & B[8];
pp9[j] <= A[j] & B[9];

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COMPROSSER

pp11[j] <= A[j] & B[11];

pp12[j] <= A[j] & B[12];
pp13[j] <= A[j] & B[13];
pp14[j] <= A[j] & B[14];
pp15[j] <= A[j] & B[15];
end
end

assign z[0]= pp0[0];

//Stage 1
ha hfa1(pp1[0],pp0[1],s[1],c[0]);
fa ffa1(pp0[2],pp1[1],pp2[0],s[2],c[1]);
fa ffa2(pp0[3],pp1[2],pp2[1],s[3],c[2]);
five_three_comp ftc1(s[32],s[31],s[4],pp0[4],pp1[3],pp2[2],pp3[1],pp4[0]);
five_three_comp ftc2(s[34],s[33],s[5],pp0[5],pp1[4],pp2[3],pp3[2],pp4[1]);

five_three_compftc3(s[36],s[35],s[6],pp0[6],pp1[5],pp2[4],pp3[3],pp4[2]);
ha hfa2(pp5[1],pp6[0],s[37],c[3]);//
five_three_compftc4(s[39],s[38],s[7],pp0[7],pp1[6],pp2[5],pp3[4],pp4[3]);
fa ffa3(pp5[2],pp6[1],pp7[0],s[40],c[4]);
five_three_compftc5(s[42],s[41],s[8],pp0[8],pp1[7],pp2[6],pp3[5],pp4[4]);
fa ffa4(pp5[3],pp6[2],pp7[1],s[43],c[5]);
five_three_comp ftc6(s[45],s[44],s[9],pp0[9],pp1[8],pp2[7],pp3[6],pp4[5]);
five_three_comp ftc7(s[48],s[47],s[46],pp5[4],pp6[3],pp7[2],pp8[1],pp9[0]);
five_three_comp ftc8(s[50],s[49],s[10],pp0[10],pp1[9],pp2[8],pp3[7],pp4[6]);
five_three_comp ftc9(s[53],s[52],s[51],pp5[5],pp6[4],pp7[3],pp8[2],pp9[1]);
five_three_comp ftc10(s[55],s[54],s[11],pp0[11],pp1[10],pp2[9],pp3[8],pp4[7]);
five_three_compftc11(s[58],s[57],s[56],pp5[6],pp6[5],pp7[4],pp8[3],pp9[2]);
ha hfa3(pp10[1],pp11[0],s[59],c[6]);
assign
t0={pp0[12],pp1[11],pp2[10],pp3[9],pp4[8],pp5[7],pp6[6],pp7[5],pp8[4],pp9[3],pp1
0[2],pp11[1],pp12[0],1'b0,1'b0};

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COMPROSSER

assign
t1={pp0[13],pp1[12],pp2[11],pp3[10],pp4[9],pp5[8],pp6[7],pp7[6],pp8[5],pp9[4],pp
10[3],pp11[2],pp12[1],pp13[0],1'b0};
fifteen_4_approx
fif2(t1,n1); assign
t2={pp0[14],pp1[13],pp2[12],pp3[11],pp4[10],pp5[9],pp6[8],pp7[7],pp8[6],pp9[5],p
p10[4],pp11[3],pp12[2],pp13[1],pp14[0]};
fifteen_4_approx
fif3(t2,n2); assign
t3={pp0[15],pp1[14],pp2[13],pp3[12],pp4[11],pp5[10],pp6[9],pp7[8],pp8[7],pp9[6],
pp10[5],pp11[4],pp12[3],pp13[2],pp14[1]};
fifteen_4_approx
fif4(t3,n3); assign
t4={pp1[15],pp2[14],pp3[13],pp4[12],pp5[11],pp6[10],pp7[9],pp8[8],pp9[7],pp10[6]
,pp11[5],pp12[4],pp13[3],pp14[2]};
fifteen_4_approx
fif5(t4,n4); assign
t5={1'b0,pp2[15],pp3[14],pp4[13],pp5[12],pp6[11],pp7[10],pp8[9],pp9[8],pp10[7],p
p11[6],pp12[5],pp13[4],pp14[3],pp15[2]};
fifteen_4_approx
fif6(t5,n5); assign
t6={1'b0,1'b0,pp3[15],pp4[14],pp5[13],pp6[12],pp7[11],pp8[10],pp9[9],pp10[8],pp1
1[7],pp12[6],pp13[5],pp14[4],pp15[3]};
fifteen_4_approx
fif7(t6,n6); assign
t7={1'b0,1'b0,1'b0,pp4[15],pp5[14],pp6[13],pp7[12],pp8[11],pp9[10],pp10[9],pp11[
8],pp12[7],pp13[6],pp14[5],pp15[4]};
fifteen_4_approx
fif8(t7,n7); assign
s[62]=n0[3];
assigns[61]=n0[2];

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COMPROSSER
assign s[60]=n0[1];

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COMPROSSER

assign s[65]=n1[3];
assign s[64]=n1[2];
assign s[63]=n1[1];
assign s[13]=n1[0];

assign s[68]=n2[3];
assign s[67]=n2[2];
assign s[66]=n2[1];
assign s[14]=n2[0];

assign s[71]=n3[3];
assign s[70]=n3[2];
assign s[69]=n3[1];
assign s[15]=n3[0];

assign s[73]=n4[3];
assign s[72]=n4[2];
assign s[109]=n4[1];
assign s[16]=n4[0];

assign s[76]=n5[3];
assign s[75]=n5[2];
assign s[74]=n5[1];
assign s[17]=n5[0];

assign s[79]=n6[3];
assign s[78]=n6[2];
assign s[77]=n6[1];
assign s[18]=n6[0];

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DESIGN AND ANALYSIS OF LOW POWER APPROXIMATE MULTIPLIER USING 15:4 COMPRESSOR

assign s[82]=n7[3];
assign s[81]=n7[2];
assign s[80]=n7[1];
assign s[19]=n7[0];
five_three_comp
ftc12(s[84],s[83],s[20],pp5[15],pp6[14],pp7[13],pp8[12],pp9[11]);
five_three_comp
ftc13(s[87],s[86],s[85],pp10[10],pp11[9],pp12[8],pp13[7],pp14[6]);

five_three_comp
ftc14(s[89],s[88],s[21],pp6[15],pp7[14],pp8[13],pp9[12],pp10[11]);
five_three_comp
ftc15(s[92],s[91],s[90],pp11[10],pp12[9],pp13[8],pp14[7],pp15[6]);

five_three_comp
ftc16(s[94],s[93],s[22],pp7[15],pp8[14],pp9[13],pp10[12],pp11[11]);
five_three_comp ftc17(s[97],s[96],s[95],pp12[10],pp13[9],pp14[8],pp15[7],1'b0);

five_three_comp
ftc18(s[99],s[98],s[23],pp8[15],pp9[14],pp10[13],pp11[12],pp12[11]);
ha hfa4(pp14[9],pp13[10],s[100],c[7]);

five_three_comp
ftc19(s[102],s[101],s[24],pp9[15],pp10[14],pp11[13],pp12[12],pp13[11]);

five_three_comp
ftc20(s[104],s[103],s[25],pp10[15],pp11[14],pp12[13],pp13[12],pp14[11]);

five_three_comp
ftc21(s[106],s[105],s[26],pp11[15],pp12[14],pp13[13],pp14[12],pp15[11]);

five_three_comp
ftc22(s[108],s[107],s[27],pp12[15],pp13[14],pp14[13],pp15[12],1'b0);

fa ffa5(pp13[15],pp14[14],pp15[13],s[28],c[8]);
ha hfa101(pp14[15],pp15[14],s[29],c[9]);

assign z[1]= s[1];

assign z[2]= r[1];

// Stage 2
//inputs s
//outputs r

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ha hfa5(s[2],c[0],r[1],r[5]);

fa ffa6(pp3[0],s[3],c[1],r[2],r[6]);

ha hfa6(s[4],c[2],r[3],r[7]);

fa ffa7(s[5],pp5[0],s[31],r[4],r[40]);

ha hfa7(s[8],s[38],r[8],r[9]);

ha hfa8(s[9],s[41],r[10],r[11]);

fa ffa8(s[10],s[44],s[42],r[12],r[13]);
fa ffa9(s[11],s[49],s[45],r[14],r[15]);
fa ffa10(s[12],s[54],s[50],r[16],r[17])
ha hfa9(s[13],s[60],r[18],r[19]);
ha hfa10(s[20],s[80],r[20],r[21]);
fa ffa11(s[21],s[83],s[81],r[22],r[23]);
fa ffa12(s[22],s[88],s[84],r[24],r[25]);
ha hfa100(s[82],s[95],r[41],r[42]);
fa ffa13(s[23],s[93],s[89],r[26],r[27]);
fa ffa14(s[24],s[98],s[94],r[28],r[29]);
ha hfa11(s[25],s[101],r[30],r[31]);
ha hfa12(s[56],s[52],r[32],r[33]);
ha hfa13(s[57],c[6],r[34],r[35]);
fa ffa15(s[100],pp15[8],s[96],r[36],r[37]);
fa ffa16(c[7],pp14[10],pp15[9],r[38],r[39]);
ha hfa102(pp15[15],c[9],r[43],r[44]);
assign z[3]= i[0];
////Stage 3
//inputs r,s
//outputs i

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ha hfa14(r[2],r[5],i[0],i[1]);

ha hfa15(r[3],r[6],i[2],i[3]);

ha hfa16(r[4],r[7],i[4],i[5]);

five_three_comp ftc23(i[8],i[7],i[6],s[6],s[33],s[32],s[37],r[40]);

five_three_comp ftc24(i[11],i[10],i[9],s[7],s[35],s[34],s[40],c[3]);

five_three_comp ftc25(i[14],i[13],i[12],s[36],s[43],c[4],pp8[0],r[8]);

five_three_comp ftc26(i[17],i[16],i[15],s[39],s[46],c[5],r[10],r[9]);

five_three_comp ftc27(i[20],i[19],i[18],s[51],s[47],pp10[0],r[12],r[11]);

five_three_comp ftc28(i[23],i[22],i[21],s[48],s[59],r[14],r[13],r[32]);

five_three_comp ftc29(i[26],i[25],i[24],s[53],r[16],r[15],r[34],r[33]);

five_three_comp ftc30(i[29],i[28],i[27],s[55],s[58],r[18],r[17],r[35]);

five_three_comp ftc31(i[32],i[31],i[30],s[14],s[63],s[61],r[19],1'b0);

five_three_comp ftc32(i[35],i[34],i[33],s[15],s[66],s[64],s[62],pp15[0]);

five_three_comp ftc33(i[38],i[37],i[36],s[16],s[69],s[67],s[65],1'b0);

five_three_comp ftc34(i[41],i[40],i[39],s[17],s[109],s[70],s[68],1'b0);

five_three_comp ftc35(i[44],i[43],i[42],s[18],s[74],s[72],s[71],1'b0);

five_three_comp ftc36(i[47],i[46],i[45],s[19],s[77],s[75],s[73],1'b0);

five_three_comp ftc37(i[50],i[49],i[48],s[78],s[76],s[85],pp15[5],r[20]);

five_three_comp ftc38(i[53],i[52],i[51],s[79],s[90],s[86],r[22],r[21]);

five_three_comp ftc39(i[56],i[55],i[54],r[24],s[91],s[87],r[23],r[41]);

five_three_comp ftc40(i[59],i[58],i[57],s[92],r[26],r[25],r[36],r[42]);

five_three_comp ftc41(i[62],i[61],i[60],s[97],r[28],r[27],r[38],r[37]);

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DESIGN AND ANALYSIS OF LOW POWER APPROXIMATE MULTIPLIER USING 15:4 COMPRESSOR

five_three_comp ftc42(i[65],i[64],i[63],s[99],pp15[10],r[30],r[29],r[39]);

five_three_compftc43(i[68],i[67],i[66],s[26],s[103],s[102],r[31],1'b0);

fa ffa17(s[27],s[105],s[104],i[69],i[70]);

fa ffa18(s[28],s[107],s[106],i[71],i[72]);

fa ffa19(s[29],c[8],s[108],i[73],i[74]);

ha hfa17(r[44],pp15[15],i[75],i[76]);

assign g[54]=i[76];
////Stage 4
//inputs i
//outputs g

ha hfa18(i[2],i[1],g[0],g[1]);
ha hfa19(i[4],i[3],g[2],g[3]);
ha hfa20(i[6],i[5],g[4],g[5]);
ha hfa21(i[9],i[7],g[6],g[7]);
fa ffa20(i[12],i[10],i[8],g[8],g[9]);
fa ffa21(i[15],i[13],i[11],g[10],g[11]);
fa ffa22(i[18],i[16],i[14],g[12],g[13]);
fa ffa23(i[21],i[19],i[17],g[14],g[15]);
fa ffa24(i[24],i[22],i[20],g[16],g[17]);
fa ffa25(i[27],i[25],i[23],g[18],g[19]);
fa ffa26(i[30],i[28],i[26],g[20],g[21]);
fa ffa27(i[33],i[31],i[29],g[22],g[23]);
fa ffa40(i[36],i[34],i[32],g[24],g[25]);
fa ffa28(i[39],i[35],i[37],g[26],g[27]);
fa ffa29(i[42],i[40],i[38],g[28],g[29]);
fa ffa30(i[45],i[43],i[41],g[30],g[31]);
fa ffa31(i[48],i[46],i[44],g[32],g[33]);
fa ffa32(i[51],i[49],i[47],g[34],g[35]);
fa ffa33(i[54],i[52],i[50],g[36],g[37]);

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DESIGN AND ANALYSIS OF LOW POWER APPROXIMATE MULTIPLIER USING 15:4 COMPRESSOR

fa ffa34(i[57],i[55],i[53],g[38],g[39]);
fa ffa35(i[60],i[58],i[56],g[40],g[41]);
fa ffa36(i[63],i[61],i[59],g[42],g[43]);
fa ffa37(i[66],i[64],i[62],g[44],g[45]);
fa ffa38(i[69],i[67],i[65],g[46],g[47]);
fa ffa39(i[71],i[70],i[68],g[48],g[49]);
ha hfa22(i[73],i[72],g[50],g[51]);
ha hfa23(i[75],i[74],g[52],g[53]);

assign z[4]= g[0];

////Stage 5
//inputs g
//outputs l,z
ha hfa24(g[2],g[1],z[5],l[1]);
fa ffa41(g[4],g[3],l[1],z[6],l[3]);
fa ffa42(g[6],g[5],l[3],z[7],l[5]);
fa ffa43(g[8],g[7],l[5],z[8],l[7]);
fa ffa44(g[10],g[9],l[7],z[9],l[9]);
fa ffa45(g[12],g[11],l[9],z[10],l[11]);
fa ffa46(g[14],g[13],l[11],z[11],l[13]);
fa ffa47(g[16],g[15],l[13],z[12],l[15]);
fa ffa48(g[18],g[17],l[15],z[13],l[17]);
fa ffa49(g[20],g[19],l[17],z[14],l[19]);
fa ffa50(g[22],g[21],l[19],z[15],l[21]);
fa ffa51(g[24],g[23],l[21],z[16],l[23]);
fa ffa52(g[26],g[25],l[23],z[17],l[25]);
fa ffa53(g[28],g[27],l[25],z[18],l[27]);
fa ffa54(g[30],g[29],l[27],z[19],l[29]);
fa ffa55(g[32],g[31],l[29],z[20],l[31]);
fa ffa56(g[34],g[33],l[31],z[21],l[33]);
fa ffa57(g[36],g[35],l[33],z[22],l[35]);
fa ffa58(g[38],g[37],l[35],z[23],l[37]);

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DESIGN AND ANALYSIS OF LOW POWER APPROXIMATE MULTIPLIER USING 15:4 COMPRESSOR

fa ffa59(g[40],g[39],l[37],z[24],l[39]);
fa ffa60(g[42],g[41],l[39],z[25],l[41]);
fa ffa61(g[44],g[43],l[41],z[26],l[43]);
fa ffa62(g[46],g[45],l[43],z[27],l[45]);
fa ffa63(g[48],g[47],l[45],z[28],l[47]);
fa ffa64(g[50],g[49],l[47],z[29],l[49]);

fa ffa65(g[52],g[51],l[49],z[30],l[51]);
fa ffa66(g[54],g[53],l[51],z[31],z[32]);
endmodule

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DESIGN AND ANALYSIS OF LOW POWER APPROXIMATE MULTIPLIER USING 15:4 COMPRESSOR

STUDENT DETAILS

1. Roll number :22A95A0415

Name of the Student :P. Indu
Number 9849802743
Mail id :22A95A0415 @[Link]

2. Roll number :21A91A04B0

Name of the Student :Sk. Mustak
Phone Number 9014125267
Mail id :21A91A04B0@[Link]

3. Roll number :21A91A04G6

Name of the Student :S. Alekhya
Phone Number 7981370008
Mail id :21A91A04G6@[Link]

4. Roll number :21A91A04B2

Name of the Student :S. Nikitha
Phone Number 9866762339
Mail id :21A91A04B2@[Link]

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