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Analog IC Design Assignment Overview

The document outlines an assignment for the Analog IC Design course at Sri Eshwar College of Engineering, focusing on various design tasks related to CMOS op-amps and amplifiers. It includes questions on input differential pairs, DC differential voltage gain, flicker noise performance, high-frequency response, and bandwidth ratios of different amplifier configurations. Each question specifies design requirements and parameters for analysis, aimed at enhancing students' understanding of analog circuit design principles.

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5 views1 page

Analog IC Design Assignment Overview

The document outlines an assignment for the Analog IC Design course at Sri Eshwar College of Engineering, focusing on various design tasks related to CMOS op-amps and amplifiers. It includes questions on input differential pairs, DC differential voltage gain, flicker noise performance, high-frequency response, and bandwidth ratios of different amplifier configurations. Each question specifies design requirements and parameters for analysis, aimed at enhancing students' understanding of analog circuit design principles.

Uploaded by

skpavanprabhu
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Sri Eshwar College of Engineering

Department of Electronics and Communication Engineering P23VL404


Analog IC Design Assignment – I

Year/Semester : I/I Batch : 2025-2027

Class : I/ME VLSI Roll No:25MVL006

[Link] Questions CO BT Marks

1 Apply the design requirements for the input differential pair (M1, M2) of a two-stage CMOS 1 K3
op-amp that must achieve a minimum Slew Rate (SR) of while maintaining the total Power
Dissipation (Pdiss) of the input stage (differential pair and tail current source) below under a
supply voltage VDD = 3V. If the op-amp utilizes a compensation capacitor (Cc) of 4 pF,
determine the required bias current Itail and the corresponding minimum required W/L ratio
for the input transistors M1 and M2, assuming the entire tail current Itail is available for
slewing, and the effective overdrive voltage is set to VOV = 200mV. Use process
parameters.

Analyse the DC differential voltage gain (A_VD) and the minimum Input Common-Mode
Range (ICMR_min) of an nMOS input telescopic cascode amplifier operating under V_DD =
1.8 V. All transistors operate at a quiescent drain current I D = 20 μA and an effective
2 overdrive voltage VOV = 0.25 V. Given process parameters: VTHN = 0.4 V, V_THP = −0.45 1 K4
V, λ_N = 0.05 V⁻¹, and λ_P = 0.08 V⁻¹. Determine A_VD in dB and ICMR_min. Assume γ =
0 and the tail current source is implemented by a single MOSFET.

Apply the flicker noise performance of an nMOS input differential pair (M1, M2) where the
input nMOS transistors are the dominant sources of 1/f noise. The input-referred noise
3 voltage spectral density Sv,in(f) due to flicker noise is given by Sv,in(f) = Kn / (CoxWLf). 1 K3
Calculate the minimum required gate length L for M1 and M2 if the noise specification
requires Sv,in(f) to be less than 1 × 10⁻¹⁵ V²/Hz at a frequency f = 1 kHz. Assume a fixed
aspect ratio W/L = 100, and given parameters Kn = 3 × 10⁻²⁴ V²F and Cox = 7 fF/μm².

Analyse the high-frequency response of a Common-Source (CS) amplifier with an active


load, where the input resistance is effectively zero and the small-signal gain is Av0 = −50.
Determine the frequency of the non-dominant pole (fp,ND) and the Unity Gain Bandwidth
4 2 K4
(ωunity), assuming the circuit is dominated by two poles: a dominant pole at fp,D = 10 MHz
(due to the output node) and a non-dominant pole that arises primarily due to the Miller
capacitance (CMiller) at the input gate. Given gm = 2 mS and the actual gate-drain
capacitance Cgd = 50 fF.

Apply the ratio of the −3 dB Bandwidth (ω3dB) of a Common-Gate (CG) amplifier to that
of a Source Follower (SF), assuming both amplifiers use the same transistor with gm = 5
5 mS and ro → ∞. The CG stage is loaded by RD = 10 kΩ and CL = 1 pF, while the SF stage 2 K3
is loaded by RL = 10 kΩ and CL = 1 pF. Neglect input node capacitance and CG pole at the
low-impedance input source.

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