Design and Implementation of VLSI Systems

lecture01

Lecturer: Dr. Nguyễn Vũ Thắng

Use document from Brown University
Lecture 01: the big picture
• Introduction
• History
• Tour of VLSI Design and Implementation
• IC market
• Design flow
Objectives of the class

• Learn fundamental knowledge on IC design: design flow,

fabrication
• How to use commercial design software
• How to code Verilog
• Learn how to design a simple VLSI systems that implement
required functionalities.

• Syllabus
Course information
• Instructor: Nguyễn Vũ Thắng [Link]@[Link]
nvthanghn2011@[Link]
• Books: CMOS VLSI design, Weste and Harris, 4th edition.
• Grade:
-Homeworks: 10%
-Midterm exam: 30%
-Practical works and Project: 60%
Introduction

• A VLSI (Very Large Scale Integration) system integrates

millions of “electronic components” in a small area (few
mm2 → few cm2).

• What are the design metrics?

• Circuit Speed / Performance
• Power consumption
• Design Area
• Yield
The Transistor Revolution

First transistor
Bell Labs, 1948
Integrated Circuits
• 1958: Jack Kilby makes the first IC
• 1961: TI and Fairchild introduce the first logic ICs ($50 in quantity)
• 1962: RCA develops the first MOS transistor
• 1965: the Moores Law
Fairchild bipolar RTL Flip-Flop RCA 16-transistor MOSFET IC

Introduction Slide 7
Computer-Aided Design

• 1967: Fairchild develops the “Micromosaic” IC using

CAD
– Final Al layer of interconnect could be customized for different
applications

• 1968: Noyce, Moore leave Fairchild, start Intel

Introduction Slide 8
RAMs

• 1970: Fairchild introduces 256-bit Static RAMs

• 1970: Intel starts selling1K-bit Dynamic RAMs

Fairchild 4100 256-bit SRAM Intel 1103 1K-bit DRAM

Introduction Slide 9
The Microprocessor

• 1971: Intel introduces the first Microprocessor: 4004

– General purpose programmable computer instead of custom
chip for Japanese calculator company

1000 transistors
1 MHz operation

Introduction Slide 10
Intel Pentium (IV) microprocessor
The Microprocessor

• 1975: the first Personal computer and the birth of

Microsoft
• 1976: the birth of Apple

Introduction Slide 12
Moore’s Law

In 1965, Gordon Moore noted that the

number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months
 LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Moore’s Law

1959
1960
1961
1962

Electronics, April 19, 1965.

1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
Transistor Counts
1 Billion
K Transistors
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected

Courtesy, Intel
Moore’s law in Microprocessors
1000

100
2X growth in 1.96 years!
Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel
Die Size Growth
100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year
Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel
Frequency
10000
Doubles every
1000 2 years
Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years

Courtesy, Intel
Power Dissipation
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead Microprocessors power continues to increase

Courtesy, Intel
Power will be a major problem
100000
18KW
10000 5KW
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive

Courtesy, Intel
Power density
10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

Courtesy, Intel
Cost of Integrated Circuits

• NRE (non-recurrent engineering) costs

– design time and effort, mask generation
– one-time cost factor
• Recurrent costs
– silicon processing, packaging, test
– proportional to volume
– proportional to chip area
NRE Cost is Increasing
Die Cost

Single die

Wafer

Going up to 12” (30cm)

From [Link]
 Cost per Transistor

cost:
¢-per-transistor
1
0.1 Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
 Yield
No. of good chips per wafer
Y= 100%
Total number of chips per wafer
Wafer cost
Die cost =
Dies per wafer Die yield
  (wafer diameter/2)2   wafer diameter
Dies per wafer = −
die area 2  die area
Defects

−
 defects per unit area  die area 
die yield = 1 + 
  
 is approximately 3

die cost = f (die area) 4

Some Examples (1994)
Chip Metal Line Wafer Def./ Area Dies/ Yield Die
layers width cost cm2 mm2 wafer cost
386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 4 0.80 $1700 1.3 121 115 28% $53

601
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

Productivity Trends
Logic Transistor per Chip (M)
10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000

(K) Trans./Staff - Mo.

Tr./Staff Month.
100 1,000
Complexity

100,000 1,000,000

Productivity
10 58%/Yr. compounded 100
10,000 Complexity growth rate 100,000

1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
1995
1981
1983
1985
1987
1989
1991
1993

1997
1999
2001
2003
2005
2007
2009
Source: Sematech

Complexity outpaces design productivity

Courtesy, ITRS Roadmap

Scaling
• Technology shrinks by 0.7/generation
• With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
• Cost of a function decreases by 2x
• But …
– How to design chips with more and more functions?
– Design engineering population does not double every two
years…
• Hence, a need for more efficient design methods
– Exploit different levels of abstraction
Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
Design Metrics
• How to evaluate performance of a
digital circuit (gate, block, …)?
– Cost
– Reliability
– Scalability
– Speed (delay, operating frequency)
– Power dissipation
– Energy to perform a function
Analog Signal Processing vs Digital
Signal Processing in VLSI
Comparing Analog and Digital IC
Analog Circuits Digital Circuits
Signals are continuous in amplitude and can Signal are discontinuous in amplitude and time
be continuous or discrete in time – binary signals have 2 amplitude states
Designed at the circuit level Designed at the systems level
Components must have a continuum of Component have fixed values
values
Customized Standard
CAD tools are difficult to apply CAD tools have been extremely successful
Requires precision modeling Timing models only
Performance optimized Programmable by software
Irregular block Regular blocks
Difficult to route automatically Easy to route automatically
Dynamic range limited by power supplies Dynamic range unlimited
and noise (and linearity)
What are VLSI systems composed of?
[Link] 2. Wires

nMOS

=
design
pMOS

Circuits

CMOS logic gates

How does an IC look like from the inside?

wires

transistors

R. Noyce J. Kilby
Technology scaling
Moore’s Law. The number of transistors in an integrated
circuit doubles every 2 years.
Technology scaling

1971: Intel 4004 – 2300 transistors – 10um tech

1979: Motorola 68000 – 68000 trans – 3.5um tech
1982: Intel 80286 – 134k trans – 1.5um tech
1989: Intel 80486 – 1180k trans – 1um tech
1999: AMD K7 – 22M trans – 250nm tech
2002: Intel – Itanium – 220M trans – 180nm tech
2010: Sun/Oracle – 16 core Sparc T3 – 1B trans – 40nm tech
2015: Oracle - 32-core Sparc M7 – 10B trans – 20nm tech

2017: AMD - 32-core AMD Epyc – 19.2B trans – 14nm tech

Feature sizes

Human Hair
~75 m

. 0.18 m
180 nm
. feature

~40,000 (65-nm node) transistors could fit on cross-section

[C. Keast]
IC market
IC market
2017 2016 2017 2017 Market 2016 2016-2017
Rank Rank Vendor Revenue Share (%) Revenue Growth (%)
1 2 Samsung Electronics 61,215 14.6 40,104 52.6

2 1 Intel 57,712 13.8 54,091 6.7

3 4 SK Hynix 26,309 6.3 14,700 79.0

4 6 Micron Technology 23,062 5.5 12,950 78.1

5 3 Qualcomm 17,063 4.1 15,415 10.7

6 5 Broadcom 15,490 3.7 13,223 17.1

7 7 Texas Instruments 13,806 3.3 11,901 16.0

8 8 Toshiba 12,813 3.1 9,918 29.2

9 17 Western Digital 9,181 2.2 4,170 120.2

10 9 NXP 8,651 2.1 9,306 -7.0

Others 174,418 41.6 157,736 10.6

Total Market 419,720 100.0 343,514 22.2

Source: Gartner (January 2018)
IC market
IC market
Silicon wafer size
Silicon wafer size
Silicon wafer size
Silicon wafer size
IC industry Revenue

Nguyen Vu Thang - FET

- HUT
IC revenue vs Market by region
Regional shift in Market force

Nguyen Vu Thang - FET

- HUT
Business models for IC companies

Nguyen Vu Thang - FET

- HUT
IC development

• World:
– Fabrication to Asia
– Outsource to Asia, especially to South East of
Asia
=> Vietnam

Nguyen Vu Thang - SET - HUT

IC design in Vietnam
• Hanoi:
– Analog IC : Active Semiconductor, ETA, Viettel
– Layout and verification: Dolphin
– Service: FPT LSI, Toshiba
– Related: Panasonic R&D, Toshiba, Samsung, Viettel,
VNPT Tech, VP9
• HCM city:
– Renesas, ACMM
– Arrive Technologies, ESilicon …
– ICDREC

Nguyen Vu Thang - SET - HUT

System on a Chip
Source: ARM
What does it take to design VLSI systems?
What does it take to design VLSI systems?
1. Applications / Ideas
2. Specifications
• Instruction set
• Interface (I/O pins)
• Organization of the system
• Functionality of each unit in
the and how it to
communicate to other unit
3/4/5. Design, Code, Compile
VHDL / Verilog / SystemC

compilation/
synthesis

design

• Design development is
facilitated using design schematics
Computer-Aided Design
(CAD) tools
6. Layout

mask layout patterns find wire routes device layout

• Design development is facilitated using Computer-Aided Design

(CAD) tools
6. Fabrication

tapeout

mask layout patterns mask writer masks

printing
test and
packaging
dice

chip die
wafer
7. Evaluate design and compare to model.

• Check signal integrity

• Power consumption
• Input/output behavior

• Does the chip function as it is

supposed to be?
• Does it work at desired clock
frequency? (can we overclock?)

board
What are we going to cover in this class?

• Overview of VLSI CMOS fabrication

• MOS transistor theory
• VLSI Layout design
• Circuit analysis and performance estimation
• Computer-aided design and analysis tools
• Design project
Textbooks

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