BASIC PROCESSING UNIT

Module 5
Some fundamental concepts
Load Instructions
Consider the instruction
Load R5, X(R7)
which uses the Index addressing mode to load a word of data from memory location X +
[R7] into register R5. Execution of this instruction involves the following actions:
• Fetch the instruction from the memory.
• Increment the program counter.
• Decode the instruction to determine the operation to be performed.
• Read register R7.
• Add the immediate value X to the contents of R7.
• Use the sum X + [R7] as the effective address of the source operand, and read the
contents of that location in the memory.
• Load the data received from the memory into the destination register, R5.
• Depending on how the hardware is organized, some of these actions
can be performed at the same time.
• We will assume that the processor has five hardware stages, which is
a commonly used arrangement in RISC(Reduced Instruction Set
Computer.)-style processors.
• Execution of each instruction is divided into five steps, such that each
step is carried out by one hardware stage.
• 1. Fetch the instruction and increment the program counter.
• 2. Decode the instruction and read the contents of register R7 in the
register file.
• 3. Compute the effective address.
• 4. Read the memory source operand.
• 5. Load the operand into the destination register, R5.
Arithmetic and Logic Instructions
Instructions that involve an arithmetic or logic operation can be executed using similar
steps.
They differ from the Load instruction in two ways:
• There are either two source registers, or a source register and an immediate source
operand.
• No access to memory operands is required.
A typical instruction of this type is Add R3, R4, R5
It requires the following steps:
1. Fetch the instruction and increment the program counter.
2. Decode the instruction and read the contents of source registers R4 and R5.
3. Compute the sum [R4] + [R5].
4. Load the result into the destination register, R3.
• It is advantageous to use the same multistage processing hardware
for as many instructions as possible.
• This can be achieved if we arrange for all instructions to be executed
in the same number of steps.
• To this end, the Add instruction should be extended to five steps,
patterned along the steps of the Load instruction.
• Since no access to memory operands is required, we can insert a step
in which no action takes place between steps 3 and 4 above
 ADD R3,R4,R5
1. Fetch the instruction and increment the program counter.
2. Decode the instruction and read registers R4 and R5.
3. Compute the sum [R4] + [R5].
4. No action.
5. Load the result into the destination register, R3.
 PIPELINING
• The concept of pipelining, which overlaps the execution of successive instructions is to
achieve high performance.
• The speed of execution of programs is influenced by many factors. One way to improve
performance is to use faster circuit technology to implement the processor and the main
memory.
• Another possibility is to arrange the hardware so that more than one operation can be
performed at the same time.
• In this way, the number of operations performed per second is increased, even though
the time needed to perform any one operation is not changed.
• Pipelining is a particularly effective way of organizing concurrent activity in a computer
system. The basic idea is very simple.
 Pipelining Issues
• Any condition that causes the pipeline to stall is called a hazard.
Add R2, R3, #100
Subtract R9, R2, #30
• The destination register R2 for the Add instruction is a source register
for the Subtract instruction.
• There is a data dependency between these two instructions, because
register R2 carries data from the first instruction to the second.
• The Subtract instruction is stalled for three cycles to delay reading
register R2 until cycle 6 when the new value becomes available.
• Data hazard due to pipelining can be handled by the following:
• Stalling
• Data Forwarding
• Data reordering
 Operand Forwarding
• Pipeline stalls due to data dependencies can be alleviated through the use of
operand forwarding.
• Consider the pair of instructions discussed above, where the pipeline is
stalled for three cycles to enable the Subtract instruction to use the new
value in register R2.
• The desired value is actually available at the end of cycle 3, when the ALU
completes the operation for the Add instruction.
• This value is loaded into register RZ ,which is a part of interstage buffer B3.
• Rather than stall the Subtract instruction, the hardware can forward the value
from register RZ to where it is needed in cycle 4, which is the ALU input.
• In this, data dependencies may be handled by the processor hardware, either
by stalling the pipeline or by forwarding data.
Handling Data Dependencies in Software
Handling Data Dependencies in Software
 Memory Delays
• Delays arising from memory accesses are another cause of pipeline
stalls.
• For example, a Load instruction may require more than one clock
cycle to obtain its operand from memory.
• This may occur because the requested instruction or data are not
found in the cache, resulting in a cache miss.
• A cache miss causes all subsequent instructions to be delayed.
• A similar delay can be caused by a cache miss when fetching an
instruction.
• There is an additional type of memory-related stall that occurs when
there is a data dependency involving a Load instruction
 Branch Delays
• For pipelining, the branch condition must be tested as early as possible
to limit the branch penalty.
 Conditional Branch
• Assume that the branch target address and the branch decision are
determined in the Decode stage, at the same time that instruction
Ij+1 is fetched.
• The branch instruction may cause instruction Ij+1 to be discarded,
after the branch condition is evaluated.
• If the condition is true, then there is a branch penalty of one cycle
before the correct target instruction Ik is fetched.
• If the condition is false, then instruction Ij+1 is executed, and there is
no penalty. In both of these cases, the instruction immediately
following the branch instruction is always fetched.
• Based on this observation, we describe a technique to reduce the
penalty for branch instructions.
• The location that follows a branch instruction is called the branch
delay slot.
• Rather than conditionally discard the instruction in the delay slot, we
can arrange to have the pipeline always execute this instruction,
whether or not the branch is taken.
• That is, branching takes place one instruction later than where the
branch instruction appears in the instruction sequence.
• This technique is called delayed branching.