Microprogrammed Control Unit and Pipelining with Hazards
1. Microprogrammed Control Unit
A Microprogrammed Control Unit (MCU) generates control signals using a sequence of
microinstructions stored in a special memory called control memory. Each microinstruction
defines a set of micro-operations to be executed.
Components:
• Control Memory (stores microinstructions)
• Control Address Register (CAR)
• Control Data Register (CDR)
• Sequencing Logic
• Control Signal Generator
Working Steps:
1. Fetch Microinstruction – Retrieved from Control Memory using CAR.
2. Decode Microinstruction – Converted to control signals.
3. Execute Micro-operations – Signals activate data transfers or ALU actions.
4. Next Address Generation – Determines address of next microinstruction.
Types of Microinstructions:
• Horizontal Microinstructions – Direct control signals, fast but wide memory words.
• Vertical Microinstructions – Encoded format, compact but slower.
Comparison with Hardwired Control:
Feature Hardwired Control Microprogrammed Control
Implementation Fixed Logic Stored Microinstructions
Speed Fast Slower
Flexibility Difficult to Modify Easily Modified
Use RISC CISC
Advantages:
• Easy to modify
• Simpler to design
• Supports complex instruction sets
Disadvantages:
• Slower performance
• Requires more memory
2. Pipelining and Hazards
Pipelining is a technique that improves CPU performance by overlapping execution of
multiple instructions. It divides instruction execution into stages such as IF, ID, EX, MEM,
and WB.
Pipeline Stages:
1. IF – Instruction Fetch
2. ID – Instruction Decode
3. EX – Execute
4. MEM – Memory Access
5. WB – Write Back
Pipeline Performance:
Speedup = Time without pipeline / Time with pipeline
Ideal Speedup = Number of stages
Types of Hazards:
• Structural Hazard: When multiple stages need the same resource (e.g., memory).
• Data Hazard: When one instruction depends on the result of a previous one.
• Control Hazard: When the pipeline makes wrong decisions on branch instructions.
Data Hazard Types:
• RAW (Read After Write)
• WAR (Write After Read)
• WAW (Write After Write)
Hazard Solutions:
• Structural: Duplicate hardware or use separate instruction/data memory.
• Data: Forwarding, pipeline stalls, or compiler scheduling.
• Control: Branch prediction, delayed branch, or pipeline flushing.
Key Points:
• Pipelining increases throughput, not latency.
• Hazards reduce pipeline efficiency.
• Ideal speedup = number of stages (rare in practice).