Power Electronics Laboratory

Lab Instructor:
Syed Abdul Rahman Kashif

Three Phase Inverter Implementation and

Simulations

Name:
Umair Bin Toheed Chughtai

Registration No.
2012-EE-22

Section:
A
 University of Engineering and Technology Lahore.
Three Phase Inverter
Introduction:
Three phase inverter is the circuit which coverts DC voltage into three phase AC
voltage with peak equal to input DC voltage for line to line output voltage across a
Y connected load when all the switches are conducting for half of the cycle (180°).
The major characteristic of the AC output voltage is that it is not only time dependent
but ensuring zero DC value. When all the switches are conducting for half of the
cycle (180°) and remain on for the intervals that are one third of the cycle (120°)
apart from one another then line to line voltages have peak equal to input DC voltage
with a dead band of one sixth of the cycle (60°) and line to neutral voltage has two
steps in positive as well as negative cycle in which first step is equal to one third of
input DC voltage and second step is equal to two third of input DC voltage for Y
connected load. These steps like stair case last for one sixth interval of the cycle
(60°). All the three line to line and line to neutral voltages are one third of the cycle
(120°) apart from one another.
There are multiple techniques of PWM operation for which the three phase inverter
can conduct. Depending upon the switches conduct for how much duration half of
the cycle (180°) or one third of the cycle (120°), the output line to line and line to
neutral voltages for Y connected load are different. Three-phase inverters are used
for variable-frequency drive applications and for high power applications such as
HVDC power transmission. It is an application of power electronics which includes
high voltage switching devices like MOSFETs. National Instruments (NI) micro-
controller technology along with FPGA (Field Programmable Gate Array)-MyRIO-
1900 is used with programming environment LabVIEW MyRIO 2014 for
compilation of different logics and generation of pulses. National Instruments
Multisim software is used for simulation results. Modern Pulse Width Modulation
(PWM) techniques including sinusoidal pulse width modulation and simple square
wave pulse are tested on this inverter. The detailed procedures for generation of these
pulses on LabVIEW MyRIO 2014 and simulation methods on NI Multisim are given
in this document.
Theoretical Concepts:
A three phase inverter consists of Six switches connected to supply voltage Vs and
Y connected load as shown in the figure 1. These switches may be Bi-Junction polar
Transistors (BJTs), Multiple Oxide Field Effect Transistors (MOSFETs) or Power
MOSFETs etc supported for high frequency switching.

Figure 1: Three phase inverter with Y connected load

Two types of control signals can be applied to the transistors: 180° conduction or
120° [Link] 180° conduction has better utiliza-tion of the switches and is
the preferred method.
180-Degree Conduction:
In 180° conduction each transistor conducts or remains on for half of the cycle
(180°). At maximum three transistors remain on at any instant of time. When
transistor Q1, Q5 and Q6 are switched on the terminal A is connected to the positive
terminal of the DC input voltage (Vs), the terminal B is also connected to the positive
terminal of the DC input voltage (Vs) but the terminal C is connected to the negative
terminal of the DC input voltage (-Vs). When transistor Q2, Q3 and Q4 are switched
on the terminal A is connected to the negative terminal of the DC input voltage (-
Vs), the terminal B is also connected to the positive terminal of the DC input voltage
(Vs) and the terminal C is connected to the negative terminal of the DC input voltage
(-Vs). There are six modes of operation in a cycle and the duration of each mode is
60°. The transistors are switched on according to the gate pulses applied which are
shifted from one another by 60° to obtain three-phase balanced (fundamental)
voltages which are shown below.
 Figure 2: Gate pulses for 180° conduction
The transistors of any leg of the inverter (Q1 and Q4, Q3 and Q6, or Q5 and Q2)
cannot be switched on simultaneously because this would result in a short circuit
across the DC voltage supply. For the above mentioned switching configuration for
the 60° intervals, the output voltage of line to neutral for Y connected load is as
follows.

Figure 3: Line to Neutral Voltages for 180° conduction for Y connected load
For the above mentioned switching configuration for the 60° intervals, the output
voltage of line to line for Y connected load is as follows.

Figure 4: Line to line voltages for 180° conduction for Y connected load

120-Degree Conduction:
In 120° conduction, each transistor conducts for one third of the cycle (120°). At
maximum only two transistors remain on at any instant of time. The gate pulses that
are applied to the switches are shown below.

Figure 5: Gate pulses for 120° conduction

When transistor Q1 and Q6 are switched on the terminal A is connected to the
positive terminal of the DC input voltage (Vs), the terminal B is also connected to
the negative terminal of the DC input voltage (-Vs) but the terminal C is floating.
When transistor Q1 and Q2 are switched on the terminal A is connected to the
positive terminal of the DC input voltage (Vs), the terminal B is floating and the
terminal C is connected to the negative terminal of the DC input voltage (-Vs). For
the above mentioned switching configuration for the 60° intervals, the output voltage
of line to neutral for Y connected load is as follows.

Figure 6: Line to neutral voltages for 120° conduction for Y connected load
For the above mentioned switching configuration for the 60° intervals, the output
voltage of line to line for Y connected load is as follows.
 Figure 7: Line to line voltages for 120° conduction for Y connected load
Circuit Diagram

Figure 8: Two PWMs generated from MyRIO are fed through two opto-couplers
independently to a gate driver’s Hin and Lin which operate two MOSFETs’ Vgs of
each leg
Hardware Implementation:
For hardware implementation of three phase inverter following important equipment
and ICs were used.
• National Instruments MyRIO-1900
• Opto-couplers TLP250
• Gate Driver IC IR2101
• High frequency diodes UF4007
• Polar Capacitors - 10uF
• Gate resistors - 33 ohm
• Power MOSFET IRF3710
 National Instruments MyRIO-1900:
Pulses are generated from National Instruments MyRIO-1900. It is a very compact
and reliable microcontroller. NI MyRIO places dual-core ARM® Cortex™-A9 real-
time processing and Xilinx FPGA customizable I/O into the single casing. It has its
own built in Wifi router. Moreover it supports 12 Analogue input channels (8 for
5V, 2 for 10V and 2 for Audio input). It has 8 Analogue output channels (4 for 5V,
2 for 10V and 2 for Audio signals). It has 32 Digital input output lines. Software
LabVIEW MyRIO 2014 is used for programming of pulses in VIs both in real time
as well as in FPGA.

Figure 9: NI MyRIO-1900 micro-controller

 Figure 10: MyRIO-1900 different on board parts
 Opto-Coupler (TLP250):
Since the pulses applied from micro-controller therefore if due to higher current
MOSFET is damaged and its gate is no more isolated from drain and source then
higher current flowing through gate to gate driver input can damage the micro-
controller processor at input of the gate driver. Its protection is done by optical
insolation by separating the grounds of micro-controller and the ground of the entire
circuit. For this purpose opto-coupler TLP250 is used before gate driver.
Figure 11: TLP20 pin configuration Figure 12: Opto-coupler IC TLP250
At pin 2, Pulse width modulation is applied from the microcontroller and pin 3 is
microcontroller’s ground. At pin 8 Vcc=12V is applied and pin 5 is common with
the ground of the entire circuit. At pin 7 PWM of 12V peak is obtained and is
supplied to gate driver inputs pins 2 and 3.
 Supply voltage (VCC): 10−35V
 Output current (IO): ±1.5A (max.)
 Maximum Operating Frequency: 25kHz

 Gate Driver (IR2101):

Since we have to apply the pulses at the gates of transistors Q1 and Q4 therefore
what would be the reference of these pulses. If it’s the ground then Vgs at Q4 is
ensured to be positive but Vgs at the gate of Q1 is not ensured to be positive because
the source of Q1 is shorted with the drain of Q4 thus this node is different from the
ground and cannot be shorted with ground to apply same pulse at Q1 and Q4 because
shorting of common node of source of Q1 and drain of Q4 with ground would
destroy the bridge configuration. Thus we need a floating ground at the common
terminal of source of Q1 and Drain of Q4 comprising 1st leg of transistors. Same
problem rises in other leg of transistors comprising Q3 & Q6 and Q5 & Q2.
This problem is solved by providing gate pulses to each leg of transistor via gate
driver IC (IR2101). The main purpose of gate driver is to create a floating ground
with the help of a capacitor at the common node of 2 transistors’ source and drain
and thus ensuring that the upper transistor in the leg is properly switching ON and
OFF with the pulses.
The IR2101(S)/IR2102(S) are high voltage, high speed power MOSFET and IGBT
drivers with independent high and low side referenced output channels. The logic
input is compatible down to 3.3V logic. The floating channel can be used to drive
an N-channel power MOSFET or IGBT in the high side configuration which
operates up to 600 volts.

Figure 13: IR2101 pin configuration Figure 14: Gate Driver IR2103
The circuit diagram according to which MOSFETs are attached with gate driver is
as follows

Figure 15: Gate driver circuit with MOSFET leg

The inputs pins 2 & 3 i,e; HIN and LIN are connected separately with 2 optocouplers
and Pulses are applied at them. Vcc=12V is applied at pin 1 and pin 4 is shorted with
ground of the entire circuit. Polar capacitors are attached between pins 1 & 4 and
8 & 6 respectively of gate driver IC. The values of polar capacitors are 10uF both.
The resistors through which the outputs of gate driver IC are attached with the gate
of MOSFET are of 33 ohm. High frequency diode UF4007 is used because of its
very less switching off time and attached between pins 1 and 8. Its reverse recovery
time is 75ns.
 Gate Resistors:
It is generally a good idea to include a gate resistor to avoid ringing. Ringing
(parasitic oscillation) is caused by the gate capacitance in series with the connecting
wire's inductance and can cause the transistor to dissipate excessive power because
it doesn't turn on quickly enough and hence the current through drain/source in
combination with the somewhat high drain-source impedance will heat the device
up. A low ohm resistor of 33 ohm will solve (dampen) the ringing.
 Power MOSFET (IRF3710):
We need high frequency operating unilateral switch, this is fulfilled by Power
MOSFET IRF3710. Most dominating characteristics of IRF3710 are its high
switching rate (Turn OFF time) and greater drain current rating (Id).

Figure 16: IRF3710

 Drain-Source Voltage (Vds) = 100V
 Gate-Source Voltage (Vgs) = ± 20V
 Continuous Drain Current (at Vgs = 10 V and Tc = 25 °C) Id = 57 A
 Turn-On Delay Time td(on) = 12ns
 Rise Time (tr) = 58ns
 Turn-Off Delay Time td(off) = 45ns
 Fall Time (tf) = 47ns
Softwares Used:
Following softwares were used for programming the pulses generation on MyRIO
and simulation.
 National Instruments LabVIEW MyRIO 2014
 National Instruments Multisim

 National Instruments LabVIEW MyRIO 2014:

LabVIEW (short for Laboratory Virtual Instrument Engineering Workbench) is a
system-design platform and development environment for a visual programming
language from National Instruments. LabVIEW includes built-in support for NI
hardware platforms such as CompactDAQ and CompactRIO, with a large number
of device-specific blocks for such hardware, the Measurement and Automation
eXplorer (MAX) and Virtual Instrument Software Architecture (VISA) toolsets.
This software here is used to program NI MyRIO microcontroller. This is a software
environment which facilitates us to code our logics of different pulse generations on
the Virtual Instrument (VI) Windows. After validating the logics and checking the
desired results from the simulated environment of NI Lab View, we can burn this
code in NI MyRIO-1900 microcontroller.
 National Instruments Multisim:
NI Multisim (formerly MultiSIM) is an electronic schematic capture and simulation
program. Multisim is one of the few circuit design programs to employ the original
Berkeley SPICE based software simulation. Here Multisim is used for the simulation
of single phase inverter with different PWM techniques like Square Wave, Sine
Wave for Unipolar Output, Sine Wave for Bipolar Output and Duty cycle RMS
Variation. Switches that ON and OFF depending upon the threshold voltage on their
inputs become useful for simulation of PWM techniques.
Generation of pulses for switches at Environment LABVIEW
MyRIO 2014:
 Gate Pulses for 180° conduction:
Three Square Waves of 50Hz with 120° phase shift are generated and their NOT are
taken and all are sent to Digital Out. The complete method is provided below:
We start from the scrap and create a new MyRIO FPGA program. Now in a Virtual
Instrument (VI) Window, right click on the screen and go to the option “Structures”.
From where we select While-loop and create a loop on the screen. Right click on
the red dot appearing within the loop and click the option “Create Constant”. This
sets the logic that while loop runs indefinitely until we stop the program. Next we
again right click on the screen and go to the “FPGA Math” then to “Generation”
from where we selected Square Wave block and place it within the while loop. We
select IO Node by right clicking on the screen and going to “FPGA IO” from the
options. Right click on the IO Node, go to “Select FPGA IO”, then go to “Connector
A”, then go to “Digital IO7:0” and then select “DIO 0”. Now place NOT gate by
right clicking on VI within while loop from Boolean Section.
Double click the Sqaue Wave block and set its frequency to 50 Hz and duty cycle to
50%. Also change to Boolean in data type so that we may get amplitude equivalent
to True or False in Boolean that is 3.3V or 0V respectively. Now again right click
on DIO 0 block and check the option “Change to write”, this allows us to connect
our Square Wave block output with the Digital I/O pin that is now available on one
of the physical pin of NI MyRIO-1900. Connect Square Wave block output directly
to first pin of Digital I/O block, and the invert of Square Wave block to second pin
of Digital I/O block. In this case DIO-0 and 1 are available at pins number 11 and
13 of MyRIO. Similarly create two other VIs and repeat the same procedure but
provide phase shifts equal to 120° and 240° respectively in their respective square
waves. Frequency control can also be made by making a local variable in the first
VI and then connecting it to the control of frequency of the square waves in the other
two Vis. The VIs are then played and and after compilation the desired waveforms
are available on the desired pins on MyRIO. The VI in NI Lab View MyRIO 2014
is given below.
 Figure 17: Gate pulses Generation for 180° conduction VI
 Gate Pulses for 120° conduction:
Six Square Waves of 50Hz with 33.33% duty cycle are generated and their phase
sequences are set 0, 180, 120, 300, 240 and 60° and all are sent to Digital Out. The
complete method is provided below:
We start from the scrap and create a new MyRIO FPGA program. Now in a Virtual
Instrument (VI) Window, right click on the screen and go to the option “Structures”.
From where we select While-loop and create a loop on the screen. Right click on
the red dot appearing within the loop and click the option “Create Constant”. This
sets the logic that while loop runs indefinitely until we stop the program. Next we
again right click on the screen and go to the “FPGA Math” then to “Generation”
from where we selected Square Wave block and place it within the while loop. We
select IO Node by right clicking on the screen and going to “FPGA IO” from the
options. Right click on the IO Node, go to “Select FPGA IO”, then go to “Connector
A”, then go to “Digital IO7:0” and then select “DIO 0”.
Double click the Sqaue Wave block and set its frequency to 50 Hz and duty cycle to
33.33%. Also change to Boolean in data type so that we may get amplitude
equivalent to True or False in Boolean that is 3.3V or 0V respectively. Also provide
the phase shift equal to 0°. Now again right click on DIO 0 block and check the
option “Change to write”, this allows us to connect our Square Wave block output
with the Digital I/O pin that is now available on one of the physical pin of NI
MyRIO-1900. Connect Square Wave block output directly to first pin of Digital I/O
block. Similarly create Six other VIs and repeat the same procedure but provide
phase shifts equal to 180°, 120°, 300°, 240° and 60° respectively in their respective
square waves. The VIs are then played and and after compilation the desired
waveforms are available on the desired pins on MyRIO. The VI in NI Lab View
MyRIO 2014 is given below.

Figure 18: Gate Pulses for 120° conduction VI

  Sine PWM for three phase inverter:
Triangular wave of 0 to 2V is generated of higher frequency and compared with
three 0 to 2V sine waves with 120° phase shifts between one another. Thus generated
SPWM pulses and their not are provided at the switches such that non inverted
SPWM pulses are given to the high side MOSFETs and inverted SPWM pulses are
given to the low side MOSFETs. The complete method is provided below:
We added a “Triangular VI” in the project that we needed as carrier wave. We open
the default VI of the project. We go onto the structures from where we made a
“While loop” and gave it the logic false for indefinitely running until stopped. Right
click on the screen and add a triangular VI, now we have a triangular module which
is giving a triangular wave of -1 to +1V. We gave the offset of +1V to have a
triangular waveform of [Link] create a local variable and gave it the name
Triangular that we can use in other While loops.
Now create another While loop by right clicking on screen and gave it to logic false
for indefinitely running until stopped. We go to the FPGA Math and then to
generation module and select a block of sinusoidal waveform. We double click it
and set its properties with frequency 50Hz, amplitude 1bit and phase offset of 0°
which is giving us the wave of -1 to +1V. We added 1 in it now it becomes Sine
wave from 0 to 2V. We create a local variable and gave it the name Q1.
Now create another While loop by right clicking on screen and gave it to logic false
for indefinitely running until stopped. Similarly again, we go to the FPGA Math and
then to generation module and select a block of sinusoidal waveform. We double
click it and set its properties with frequency 50Hz, amplitude 1bit and phase offset
of 120° which is giving us the wave of -1 to +1V but with 120° phase shift. We
added 1 in it now it becomes Sine wave from 0 to 2V. We create a local variable and
gave it the name Q3.
Now create another While loop by right clicking on screen and gave it to logic false
for indefinitely running until stopped. Similarly again, we go to the FPGA Math and
then to generation module and select a block of sinusoidal waveform. We double
click it and set its properties with frequency 50Hz, amplitude 1bit and phase offset
of 240° which is giving us the wave of -1 to +1V but with 240° phase shift. We
added 1 in it now it becomes Sine wave from 0 to 2V. We create a local variable and
gave it the name Q5.
We created a fourth while loop and where we compare unipolar sinusoidal wave
forms with unipolar triangular wave and if unipolar sinusoidal is greater than
unipolar triangular we get logic high otherwise logic low. Greater than block is found
from Comparison section. In this way we have generated a sinusoidal PWM
throughout. The wave thus generated is available to us on digital I/O pin 11 of the
controller.
We again compare unipolar sinusoidal wave form (with 120° phase shift) with
unipolar triangular wave and if unipolar sinusoidal wave forms (with 120° phase
shift) is greater than unipolar triangular we get logic high otherwise logic low.
Greater than block is found from Comparison section. In this way we have generated
a sinusoidal PWM throughout but with 120° out of phase as compared to the other
wave available at pin [Link] waveform thus generated is made available on digital
I/O pin 15 of the controller. We again compare unipolar sinusoidal wave form (with
240° phase shift) with unipolar triangular wave and if unipolar sinusoidal wave
forms (with 240° phase shift) is greater than unipolar triangular we get logic high
otherwise logic low. Greater than block is found from Comparison section. In this
way we have generated a sinusoidal PWM throughout but with 240° out of phase as
compared to the other wave available at pin [Link] waveform thus generated is made
available on digital I/O pin 19 of the controller. Similarly the Not of these 3 SPWMs
are made available at pins 13, 17 and 21 of MyRIO. The VI is then played and and
after compilation the desired waveforms are available on the desired pins on MyRIO.
The VI in NI Lab View MyRIO 2014 is given below:
Figure19: Sine PWM for three phase inverter VI
 Simulations on NI MULTISIM
1-Three phase inverter with resistive and inductive Y-connected load with
180° square wave operation
Part a: Three Phase Square Wave Inverter with 180° conduction for Resistive
Load with MOSFETs

Figure 20: Circuit Diagram

Figure 21: Line to Neutral Voltage Output of Three phases

Figure 22: Line to Line Voltages

Part b: Three Phase Square Wave Inverter with 180° conduction for
Inductive Load with MOSFETs

Figure 23: Circuit Diagram

 Figure 24: Line to Neutral Voltages across Resistors

Figure 25: Line to Neutral Voltages across Inductor plus Resistor

Figure 26: Line to Line Voltages
Part c: For Frequency = 1kHz

Figure 27: Line to neutral voltages

Figure 28: Line to line voltages

2-Three phase inverter with resistive and inductive Y-connected load with
180° with PWM operation (Variable duty-cycle of PWM waveform)

Figure 29: Circuit Diagram

Part a: 75% Duty cycle

Figure 30: Line to Neutral Voltages

Figure 31: Line to line Voltages

Part b: 25% duty Cycle

Figure 32: Line to neutral Voltages

Figure 33: Line to line Voltages

3-Three phase inverter with resistive and inductive Y-connected load with
120° square wave operation (50 Hz output)
Part a: Three Phase Square Wave Inverter with 120° conduction for Resistive
Load MOSFETs

Figure 34: Circuit Diagram

Figure 35: Line to neutral voltages

Figure 36: line to line voltages

Part b: Three Phase Square Wave Inverter with 120° conduction for
Inductive Load MOSFETs

Figure 37: Circuit diagram

 Figure 38: Line to line voltages

Figure 39: line to neutral voltages

4-Three phase inverter with resistive and inductive Y-connected load with
Sinusoidal PWM operation (controllable modulation index and frequency)

Part a: Sinusoidal 3 phase inverter for 180° conduction for Resistive Load

Figure 40: Circuit Diagram

Figure 41: line to neutral oltages

Figure 42: line to line voltages

Part b; Sinusoidal 3 phase inverter for 180° conduction for Inductive load

Figure 43: Circuit diagram

Figure 44: Line to neutral voltages
Part c: Sinusoidal 3 phase inverter for 180° conduction for Resistive Load
with Comparator

Figure 45: Circuit Diagram

Figure 46: Line to Neutral Voltages across all the Branches of Y load

Figure 47: Line to Neutral Voltage across one branch

Figure 48: Line to line Voltages
 Actual Hardware Waveform Results on Oscilloscope
Applied Voltage Vs=12V
Load Resistive (3.3k) Balanced
For 180° Conduction
Line to neutral Voltage

Line to Line Voltage

 For 120° Conduction
Line to neutral Voltage

Line to Line Voltage

 For 180° Conduction Sine PWM
Line to neutral Voltage

Line to Line Voltage

References:
 Power Electronics Circuits, Devices and Applications (4th Edition) By
Muhammad H. Rashid.
 NImyRIO Project Essentials Guide By Ed Doering Electrical and Computer
Engineering Department Rose Hulman Institute of Technology
 Opto-Coupler TLP250 Datasheet
[Link]
[Link]/info/[Link]?pid=TLP250&lang=en&type=datasheet
 Gate Driver IR2101 Datasheet
[Link]
 MOSFET IRF3710 Datasheet
[Link]