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VLSI Design Phase Margin Calculations

The document contains a series of exercises related to Analog and Digital VLSI Design, focusing on amplifier gain, phase margin calculations, and feedback loops. It includes specific problems involving gain values, pole frequencies, and circuit parameters to determine phase margins in various configurations. Each exercise requires applying principles of feedback and stability in amplifier design.

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26 views16 pages

VLSI Design Phase Margin Calculations

The document contains a series of exercises related to Analog and Digital VLSI Design, focusing on amplifier gain, phase margin calculations, and feedback loops. It includes specific problems involving gain values, pole frequencies, and circuit parameters to determine phase margins in various configurations. Each exercise requires applying principles of feedback and stability in amplifier design.

Uploaded by

foyafox319
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI - K. K.

BIRLA GOA CAMPUS


Analog & Digital VLSI Design Tutorial 4

Use VDD = 3 V if not specified in problem


Analog & Digital VLSI Design (EEE F313/INSTR F313) Page 2 of 2
Ex 1: An amplifier with a forward gain of A0 and two poles at 10 MHz and 500 MHz is placed in a
unity-gain feedback loop. Calculate A0 for a phase margin of 60◦ .

Ex 2: An amplifier with a forward gain of A0 has two coincident poles at ω p . Calculate the
maximum value of A0 for a 60◦ phase margin with a closed-loop gain of (a) unity and (b) 4.

Ex 3: An amplifier has a forward gain of A0 =1000 and two poles at ω p1 and ω p2 . For ω p1 = 1 MHz,
calculate the phase margin of a unity-gain feedback loop if (a) ω p2 = 2ω p1 and (b) ω p2 = 4ω p1 .

Ex 4: A unity-gain closed-loop amplifier exhibits a frequency peaking of 50% in the vicinity of the
gain crossover. What is the phase margin?

Ex 5: Consider the transimpedance amplifier shown in figure below, where RD =1kΩ, RF =10kΩ,
gm1 =gm2 =1/(100Ω), and CA =CX =CY =100 fF. Neglecting all other capacitances and assuming that
λ =γ=0, compute the phase margin of the circuit. (Hint: break the loop at node X.)

Ex 6: If the phase margin required of the amplifier of Ex 5 is 45◦ , what is the maximum value of
(a) CY , (b) CA , and (c) CX while the other two capacitances remain constant?

Ex 7: Consider the amplifier of figure below, where (W/L)1−4 = 50/0.5 and ISS =I1 =0.5 mA.
(a) Estimate the poles at nodes X and Y by multiplying the small-signal resistance and capacitance
to ground. Assume that CX =CY =0.5 pF. What is the phase margin for unity-gain feedback?

(b) If CX =0.5 pF, what is the maximum tolerable value of CY that yields a phase margin of 60◦
for unity-gain feedback?

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