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VLSI Delay Analysis and Stick Diagrams

The document contains a tutorial on Analog & Digital VLSI Design with exercises focused on the design and analysis of NOR and AND-OR-INVERT gates using the Elmore delay model. It includes tasks such as sketching diagrams, computing propagation delays, estimating capacitance, and evaluating logical effort and drive strengths of various gate configurations. The exercises aim to enhance understanding of VLSI design principles and delay calculations.

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100 views15 pages

VLSI Delay Analysis and Stick Diagrams

The document contains a tutorial on Analog & Digital VLSI Design with exercises focused on the design and analysis of NOR and AND-OR-INVERT gates using the Elmore delay model. It includes tasks such as sketching diagrams, computing propagation delays, estimating capacitance, and evaluating logical effort and drive strengths of various gate configurations. The exercises aim to enhance understanding of VLSI design principles and delay calculations.

Uploaded by

foyafox319
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI - K. K.

BIRLA GOA CAMPUS


Analog & Digital VLSI Design Tutorial 8

Ex 1: Sketch a 2-input NOR gate with transistor widths chosen to achieve effective rise and fall
resistances equal to a unit inverter. Compute the rising and falling propagation delays of the NOR
gate driving h identical NOR gates using the Elmore delay model. Assume that every source or
drain has fully contacted diffusion when making your estimate of capacitance.

Ex 2: Sketch a stick diagram for the 2-input NOR. Compute the rising and falling propagation
delays of the NOR gate driving h identical NOR gates using the Elmore delay model with better
capacitance estimates. In particular, if a diffusion node is shared between two parallel transistors,
only budget its capacitance once. If a diffusion node is between two series transistors and
requires no contacts, only budget one capacitance because of the smaller diffusion area.

Ex 3: Find the rising and falling propagation delays of an unloaded AND-OR-INVERT gate using
the Elmore delay model. Estimate the diffusion capacitance based on a stick diagram of the
layout.

Ex 4: Find the worst-case Elmore parasitic delay of an n-input NOR gate.

Ex 5: Let a 4x inverter have transistors four times as wide as those of a unit inverter. If a
unit inverter has three units of input capacitance and parasitic delay of pinv , what is the input
capacitance of a 4x inverter? What is the logical effort? What is the parasitic delay?

Ex 6: A 3-stage logic path is designed so that the effort borne by each stage is 12, 6, and 9 delay
units, respectively. Can this design be improved? Why? What is the best number of stages for
this path? What changes do you recommend to the existing design?

Ex 7: Suppose a unit inverter with three units of input capacitance has unit drive. a) What is
the drive of a 4x inverter? b) What is the drive of a 2-input NAND gate with three units of input
capacitance?

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