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Basic Computer
Organization and Design
Computer Organization & Architecture - MODULE 3
PART 1
Instruction Codes
 Instruction Codes

● The organization of the computer is defined by its internal registers, the timing and control
structure, and the set of instructions that it uses.
● A computer instruction is a binary code that specifies a sequence of microoperations for
the computer.
● An instruction code is a group of bits that instruct the computer to perform a specific
operation.
● Instruction code is usually divided into two parts.
○ Operation part - Group of bits that define such operations as add, subtract, multiply,
shift, and complement.
○ Address part - Contains registers or memory words where the address of operand is
found or the result is to be stored.
● Each computer has its own instruction code format.
 Operation Code

● The operation code(op-code) of an instruction is a group of bits that define such operations as
add, subtract, multiply, shift, and complement.
● The number of bits required for the operation code of an instruction depends on the total
number of operations available in the computer.(n bits for 2n operations)
● An operation code is sometimes called a macro-operation because it specifies a set of
micro-operations.
 Stored Program Organization

● Simplest way to organize computer is to have one processor register(Accumulator AC) and an
instruction code format with two parts.
○ First-Operation to be performed
○ Second – Address
● The memory address tells the control where to find an operand in memory.
● This operand is read from memory and used as the data to be operated on together with the
data stored in the processor register.
● Instructions are stored in one section of
the memory and data in another.
● For a memory unit with 4096 words we
need 12 bits to specify an address since
212=4096.
● 4 bits are available for opcode to specify
one out of 16 possible operations.
 Steps

● The control reads a 16-bit instruction from the program portion of memory.
● It uses the 12-bit address part of the instruction to read a 16-bit operand from the data portion
of memory.
● It then executes the operation specified by the operation code.
● The operation is performed with the memory operand and the content of AC.
 Direct & Indirect Addressing Modes

● Following Addressing Modes are used for address portion of the instruction code.
○ Immediate- The address part specifies an operand.
Eg: ADD 5
○ Direct- The address part specifies the address of an operand.
○ Indirect- The address part specifies a pointer(another address) where the address of the
operand can be found.
● One bit of the instruction code(I) can be used to distinguish between a direct and an indirect
address.
 Effective Address

It is the address of the operand in a

computation-type instruction or the target
address in a branch-type instruction.

The effective address in the instruction of Fig.(b)

is 457 and in the instruction of Fig(c) is 1350.
Computer Registers
 Computer Registers

Need of Registers?
● Computer instructions are normally stored in consecutive memory locations and are executed
sequentially one at a time.
● The control reads an instruction from a specific address in memory and executes it. It then
continues by reading the next instruction in sequence and executes it, and so on.
● This type of instruction sequencing needs a counter to calculate the address of the next
instruction after execution of the current instruction is completed.
● It is also necessary to provide a register in the control unit for storing the instruction code
after it is read from memory.
● The computer needs processor registers for manipulating data and a register for holding a
memory address.
 List of basic Registers

Code Bits Name Purpose

DR 16 Data Register Holds memory operand

AR 12 Address register Holds address for memory

AC 16 Accumulator Processor register

IR 16 Instruction register Holds instruction code

PC 12 Program counter Holds address of instruction

TR 16 Temporary register Holds temporary data

INPR 8 Input register Holds input character

OUTR 8 Output register Holds output character

 Common Bus System

Need of Common Bus System ?

● The basic computer has eight registers, a memory unit, and a control unit.
● Paths must be provided to transfer information from one register to another and between
memory and registers.
● The number of wires will be excessive if connections are made between the outputs of each
register and the inputs of the other registers.
● Hence more efficient scheme with a common bus is used.
● The outputs of seven registers and
memory are connected to the
common bus.
● The specific output that is selected
for the bus lines at any given time is
determined from the binary value of
the selection variables S2, S1, and S0.
● The number along each output
shows the decimal equivalent of the
required binary selection.
● For example, the number along the
output of DR is 3. The 16-bit outputs
of DR are placed on the bus lines
when S2S1S0 =011 since this is the
binary value of decimal 3.
● The lines from the common bus are
connected to the inputs of each
register and the data inputs of the
memory.
● The particular register whose LD
(load) input is enabled receives the
data from the bus during the next
clock pulse transition.
● The memory receives the contents of
the bus when its write input is
activated.
● The memory places its 16-bit output
onto the bus when the read input is
activated and S2S1S0 =111.
● INPR is connected to provide
information to the bus but OUTR can
only receive information from the
bus.
● This is because INPR receives a
character from an input device which
is then transferred to AC.
● OUTR receives a character from AC
and delivers it to an output device.
● There is no transfer from OUTR to
any of the other registers.
● The inputs of AC come from an adder
and logic circuit.
● This circuit has three sets of inputs.
● One set of 16-bit inputs come from
the outputs of AC. They are used to
implement register micro-operations
such as complement AC and shift AC.
● Another set of 16-bit inputs come
from the data regisler DR. The inputs
from DR and AC are used for
arithmetic and logic
microoperations.
● A third set of 8-bit inputs come from
the input register INPR.
Computer Instructions
 Instruction Format

● The basic computer has three instruction code formats each having 16 bits
○ Memory reference instructions
○ Register reference instructions
○ I/O instructions
● The opcode part of the instruction contains three bits and the meaning of the remaining 13
bits depends on the operation code encountered.
 Memory reference instructions

● Bits 0-11 for specifying address.

● Bits 12-14 for specifying address.
● 15th bit specifies addressing modes. (0 for direct and 1 for indirect)

● Opcode=000 through 110

● I=0 or 1
● Eg:
○ AND - 0xxx(direct) or 8xxx(indirect)
○ ADD - 1xxx or 9xxx
 Register reference instructions

● Recognized by the operation code 111 with a 0 in the 15th bit of the instruction.
● Specifies an operation on or a test of the AC register.
● An operand from memory is not needed.
● Therefore the 12 bits are used to specify the operation to be executed.

● Eg:
○ CLA - 7800 : Clear AC
○ CLE - 7400 : Clear E
 I/O instructions

● These instructions are needed for transfering informations to and from AC register.
● Recognized by the opcode 111 and a 1 in the 15th bit.
● Bits 0-11 specify the type of I/O Operation performed.

● Eg:
○ INP - F800 : Input characters to AC
○ OUT - F400 : Output characters from AC
 Instruction Set Completeness

● The set of instructions are said to be complete if the computer includes a sufficient number of
instructions in each of the following categories
a. Arithmetic, logical, and shift instructions
b. Instructions for moving information to and from memory and processor registers
c. Program control instructions
d. Input and output instructions
Timing and Control
 Timing and Control

● The timing for all registers in the basic computer is controlled by a master clock generator.
● The clock pulses are applied to all flip-flops and registers.
● The clock pulses do not change the state of a register unless the register is enabled by a
control signal.
● Two major types of control organization:
○ hardwired control
○ microprogrammed control.
 Hardwired Control Microprogrammed Control

● The control logic is implemented with ● The control information is stored in a

gates, flip-flops, decoders, and other control memory.
digital circuits. ● The control memory is programmed
● It can be optimized to produce a fast to initiate the required sequence of
mode of operation. microoperations.
● Requires changes in the wiring among ● Required changes or modifications
the various components if the design can be done by updating the
has to be modified or changed. microprogram in control memory.
 Hardwired control unit

● Consists of two decoders, a sequence counter,

and a number of control logic gates.
● An instruction read from memory is placed in
the instruction register(IR).
● The IR is divided into three parts:
○ I bit, opcode, and Address bits.
● Op-code in 12-14 bits are decoded with a 3x8
decoder.
● 8 outputs of the decoder are designated by the
symbols D0 through D7.
● Bit 15 is transferred to a flip-flop I.
● Bits 0-11 are applied to the control logic gates.
 Hardwired control unit

● The 4-bit sequence counter can count in binary

from 0-15.
● The outputs of the counter are decoded into 16
timing signals T0-T15.
● The sequence counter SC can be incremented
or cleared synchronously.
● Mostly,SC is incremented to provide the
sequence of timing signals(T1,T2,...,T15)
● Once in a while, the counter is cleared to 0,
causing the next active timing signal to be T0.
● Eg: Suppose,at time T4, SC is cleared to 0 if
decoder output D3 is active. D3T4: SC ← 0.
 Hardwired control unit

● The SC responds to the positive transition of

the clock.
● Initially, the CLR input of SC is active.
● Hence it clears SC to 0, giving the timing signal
T0 out of the decoder.
● T0 is active during one clock cycle and will
trigger only those registers whose control
inputs are connected to timing signal T0.
● SC is incremented with every positive clock
transition, unless its CLR input is active.
● This produces the sequence of timing signals
T0, T1, T2, T3, T4 up to T15 and back to T0.
[Link]

Basic Computer
Organization and Design
Computer Organization & Architecture - MODULE 3
PART 2
Instruction Cycle
 Instruction Cycle

● A program consists of a sequence of instructions is executed in the computer by going through

a cycle for each instruction.
● Each instruction cycle in turn is subdivided into a sequence of subcycles or phases
● They are
a. Fetch an instruction from memory.
b. Decode the instruction.
c. Read the effective address from memory if the instruction has an indirect address.
d. Execute the instruction.
● Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute
the next instruction.
● This process continues indefinitely unless a HALT instruction is encountered.
 Fetch & Decode

● Initially, the program counter PC is loaded with the address of the first instruction in the
program.
● SC is cleared to 0, providing a decoded timing signal T0.
● After each clock pulse, SC is incremented by one, so that the timing signals go through a
sequence T0, T1, T2, and so on.
● The microoperations for the fetch and decode phases are
○ T0: AR ← PC
○ T1: IR ← M [AR], PC ← PC+1
○ T2: D0,. . . , D7 ← Decode IR(12–14), AR ← IR(0-11), I ← IR(15)
 Fetch & Decode

● During T0 the address is transferred from PC to AR.

● At T1 The instruction read from memory is placed in the instruction register IR and PC is
incremented by one to prepare it for the address of the next instruction.
● At time T2, the op-code in IR is decoded, the indirect bit is transferred to flip-flop I, and the
address part of the instruction is transferred to AR.
● Note that SC is incremented after each clock pulse to produce the sequence T0, T1, and T2.
 Determine the Type of Instruction

● During time T3, the control unit determines the type of instruction that was just read from
memory.
● Memory Reference Instructions
○ If D7=0, the op-code will be 000 through 110
○ If D7 =0 and I =1 - memory reference instruction with an indirect address.
○ The micro-operation for the indirect address condition can be symbolized by
AR ← M [AR].
● Register Reference or I/O Instructions
○ If D7 =1 and I=0 - Register Reference Instruction.
○ If D7 =1 and I=1 - I/O Instruction.
● The three instruction types are subdivided into four separate paths.
● The selected operation is activated with T3.
○ D7’ IT3 : AR ← M[AR].
○ D7’ IT3 : Nothing.
○ D7 I’T3 : Execute a register-reference instruction.
○ D7 IT3 : Execute an input–output instruction.
Memory Reference Instruction
 Memory Reference Instruction

● Memory reference instructions performs operation with memory operand.

● Execution of memory reference instruction starts with timing signal T4.

● There are 7 memory instruction.
 AND to AC ADD to AC

● Performs AND logic operation on pairs ● Adds the content of the memory word
of bits in AC and the memory word specified by the effective address to
specified by effective address. the value of AC.
● The result of operation is transferred to ● Sum is transferred to AC and output
AC. carry Cout is transferred into E
(Extended accumulator flipflop)
● D0T4: DR ← M [AR]
D0T5: AC ← AC ^ DR, SC ← 0 ● D1T4: DR ← M [AR]
D1T5: AC ← AC ^ DR, E ← Cout, SC ← 0
 LDA : Load to AC STA : Store to AC

● Transfers the memory word specified ● Stores the content of AC into the
by the effective address to AC. memory word specified by the
● D2T4: DR ← M [AR] effective address.
D2T5: AC ← DR, SC ← 0 ● D3T4: M [AR] ← AC, SC ← 0
 ISZ: Increment and Skip if
Zero
BUN : Branch
● Increments the word specified by the
Unconditionally
effective address, and if the
incremented value is equal to 0, PC is
● Transfers the program to the
incremented by 1 in order to skip the
instruction specified by the effective
next instruction in the program.
address.

● D6T4: DR ← M [AR]
● D4T4: PC ← AR, SC ← 0
D6T5: DR ← DR+1
D6T6: M [AR] ← DR, if (DR 0) then (PC
← PC 1), SC ← 0
 BSA : Branch and Save Return Address

● Used for branching to a portion of the

program called a subroutine or procedure.
● It stores the address of the next
instruction into a memory location
specified by the effective address.
● The effective address plus one is
transferred to PC to serve as the address
of the first instruction in the subroutine.

● D5T4: M [AR] ← PC, AR ← AR + 1

D5T5: PC ← AR, SC ← 0
Register Reference Instructions
 Register Reference Instructions

● It specifies an operation on or test of the Accumulator.

● An operand from memory is not needed.
● So bits 0-11 bits the operation to be executed.
● They are recognized by the control when D7 = 1 and I = 0.
● Execution start with the timing signal T3.
● Each control function needs the Boolean relation D7IT3 and is represented by the symbol r.
● By assigning the symbol B, to bit i of IR(0-11), all control functions can be simply denoted by
rBi.
Input and Output
Communication
 Input–Output Communication

● A computer can serve no useful purpose unless it communicates with the external
environment.
● Instructions and data stored in memory must come from some input device.
● Computational results must be transmitted to the user through some output device.
● To demonstrate the most basic requirements for input and output communication, we will use
as an illustration a terminal unit with a keyboard and printer.
 Input-Output Configuration

● Terminal sends and receives information

(eight bits of an alphanumeric code).
● The serial information from the keyboard is
shifted into the input register INPR.
● The serial information for the printer is
stored in the output register OUTR.
● Both INPR and OUTR consists of eight bits.
 Input-Output Configuration

● INPR and OUTR communicate with a

communication interface serially and with
the AC in parallel.
● The transmitter interface receives serial
information from the keyboard and
transmits it to INPR.
● The receiver interface receives information
from OUTR and sends it to the printer.
 Input-Output Configuration
● The 1-bit input flag FGI is a control flip-flop.
● The flag bit is set to 1 when new
information is available in the input device
and is cleared to 0 when the information is
accepted by the computer.
● Initially, the input flag FGI is cleared to 0.
● When a key is struck, an 8-bit code is
shifted into INPR and FGI is set to 1.
● When another key is striked, the computer
checks the flag bit; if it is 1, the information
from INPR is transferred to AC and FGI is
cleared to 0.
 Input-Output Configuration

● Initially, the output flag FGO is set to 1.

● The computer checks the flag bit; if it is 1,
the information from AC is transferred in
parallel to OUTR and FGO is cleared to 0.
● The output device accepts information,
prints the corresponding character, and
when the operation is completed, it sets
FGO to 1.
● The computer does not load a new
character into OUTR when FGO is 0. (Busy
printing)
 Input-Output Instructions

● Needed for
○ transferring information to and from AC register.
○ for checking the flag bits.
○ for controlling the interrupt facility.
● Recognized by the control when D7 =1 and I =1.
● The remaining bits(0-11) of the instruction specify the particular operation.
● Executed with the clock transition associated with timing signal T3.
● Each control function needs a Boolean relation D7IT3, and is represented by the symbol p.
● By assigning the symbol Bi to bit i of IR, all control functions can be denoted by pBi for i = 6
through 11.
Input-Output Instructions
Program Interrupt
 Need for Interrupt

● In basic case (Programmed control transfer), the computer keeps checking the flag bit, and
when it finds it set, it initiates an information transfer.
● This type of transfer is inefficient because of the difference of information flow rate between
the computer and that of the input–output device.
● The computer is wasting time while checking the flag instead of doing some other useful
processing task.
 Program Interrupt

● An alternative to the programmed controlled procedure is to let the external device inform the
computer when it is ready for the transfer.
● In the meantime the computer can be busy with other tasks.
● This type of transfer uses the interrupt facility.
● While the computer is running a program, it does not check the flags.
● When a flag is set, the computer is interrupted from proceeding with the current program.
● The computer stops what it is doing to take care of the input or output transfer.
● It then returns to the current program to continue what it was doing before the interrupt
 Program Interrupt

● The interrupt facility can be enabled or disabled by a flip-flop IEN.

● The interrupt enable flip-flop IEN can be set and cleared with two instructions (IOF, ION).
○ When IEN is cleared to 0 (with the IOF instruction), the flags cannot interrupt the
computer.
○ When IEN is set to 1 (with the ION instruction), the computer can be interrupted.
● An interrupt flip-flop R is included in the computer to decide when to go through the interrupt
cycle.
● So the computer is either in an instruction cycle or in an interrupt cycle.
 Interrupt Cycle

● When R = 0, the computer goes through an

instruction cycle.
● During the execute phase IEN is checked. If it
is 0, control continues with the next
instruction cycle.
● If IEN = 1, control checks the flag bits. If both
flags are 0, control continues with the next
instruction cycle.
● If either flag is set to 1 while IEN = 1, R is set
to 1 and control goes to an interrupt cycle.
 Interrupt Cycle
● The interrupt cycle is a hardware
implementation of a branch and save return
address operation.
● The return address in PC is stored in a specific
location. (Here address 0)
● Control then inserts address 1 into PC and
clears IEN and R so that no more interruptions
can occur until the interrupt request serviced
and flag has been set.
● Micro-operations
○ RT0: AR ← 0, TR ← PC
○ RT1: M [AR] ← TR, PC ← 0
○ RT2: PC ← PC 1, IEN ← 0, R ← 0, SC ← 0
Design of Basic Computer
 Design of Basic Computer

The basic computer consists of the following hardware components:

1. A memory unit with 4096 words of 16 bits each.

2. Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC.
3. Seven flip-flops: I, S, E, R, IEN, FGI, and FGO.
4. Two decoders: a 3x8 operation decoder and a 4x16 timing decoder.
5. A 16-bit common bus.
6. Control logic gates.
7. Adder and logic circuit connected to the input of AC.
Design of Basic Computer
 Control Logic Gates

● The inputs to this circuit come from ● The outputs of the control logic circuit are
○ two decoders ○ Signals to control the inputs of the
○ I flip-flop nine registers
○ bits 0 through 11 of IR. ○ Signals to control the read and write
● The other inputs to the control logic are inputs of memory
○ AC bits 0 through 15 to check if AC =0 ○ Signals to set, clear, or complement
and to detect the sign bit in AC(15) the flip-flops
○ DR bits 0 through 15 to check if DR= 0 ○ Signals for S2, S1, and S0 to select a
○ The values of the seven flip-flops. register for the bus
○ Signals to control the AC adder and
logic circuit
 Control of Registers and Memory

● The control inputs of the registers are LD (load), INR (increment), and CLR (clear).
● Eg: To derive the gate structure associated with the control inputs of AR.
Find all the statements that change the content of AR
R’T0: AR ← PC
R’T2: AR ← IR(0–11)
D7’IT3: AR ← M [AR]
RT0: AR ← 0
D5T4: AR ← AR + 1
● The control functions can be combined into three Boolean expressions as follows
LD(AR) = R’T0 + R’T2 + D7’IT3
CLR(AR) = RT0
INR(AR) = D5T4
 Control of Common Bus

● The 16-bit common bus is controlled by the selection inputs S2, S1, and S0.
● The decimal number shown with each bus input specifies the equivalent binary number that
must be applied to the selection inputs in order to select the corresponding register.
● For example, when x1 = 1, the value of S2S1S0 must be 001 and the output of AR will be
selected for the bus.
 Control of Common Bus

● The Boolean functions for the encoder are

S0 = x1 + x3 + x5 + x7
S1 = x2 + x3 + x6 + x7
S2 = x4 + x5 + x6 + x7
● To determine the logic for each encoder input, it is necessary to find the control functions that
place the corresponding register onto the bus.
● For example, to find the logic that makes x1 = 1, we scan all register transfer statements in and
extract those statements that have AR as a source.
D4T4: PC ← AR
D5T5: PC ← AR
Therefore, the Boolean function for x1 is, x1 = D4T4 D5T5
● In a similar manner we can determine the gate logic for the other registers.
Design of Accumulator Logic
 Design of Accumulator Logic

● The adder and logic circuit has three sets of inputs.

○ 16 inputs comes from the outputs of AC.
○ 16 inputs comes from the data register DR.
○ eight inputs comes from the input register INPR.
● The outputs of the adder and logic circuit provide the data inputs for the register.
 Design of Accumulator Logic

● In order to design the logic associated with AC, extract all the statements that change the
content of AC.
D0T5: AC ← AC ^ DR
D1T5: AC ← AC + DR
D2T5: AC ← DR
pB11: AC(07) ← INPR
rB9: AC ← AC
rB7: AC ← shr AC, AC(15) ← E
rB6: AC ← shl AC, AC(0) ← E
rB11: AC ← 0
rB5: AC ← AC + 1
● From this list we can derive the control logic gates and the adder and Logic circuit.