CSCI 2406 Computer Org.
&
Architecture
Signed and Unsigned Numbers / Program Status
Two's Complement
How to represent negative numbers
Negative Numbers
● There have been many theories about how best to
represent negative numbers in computer systems.
● One idea - dedicate the MSB to represent the sign
● So in a 5-bit architecture, the number 3 would be
○ 00011 = 310
○ 10011 = -310
● this scheme fails in a few places
○ it allows us to represent 0 and negative 0 (00000 and
10000)
Addition … fail
00011
+ 10011
--------
10110
● So this is -610 which is wrong - it should be 0
● So we would need special hardware to deal with
negative numbers
Special Hardware
● Special additional hardware for add/mul/sub is highly
undesirable
● So what we need is a scheme for representing negative
numbers with the following property
● No special/additional hardware required for
add/mul/sub
● No contradictory positive and negative 0
● Normal performance / cycle speeds
Solution - two's complement
Steps:
● Take the binary representation of the positive number
and invert all the bits (eg, 910)
01001 => 10110
● Add one
○ 10110 => 10111
Does it work?
Lets try -910 + 610
But is 11101
10111 correct for
+ 00110 -3?
--------
Let's check …
11101 & tell me what
you get
Addition of -3+3 … try again
00011 (3)
+ 11101 (-3)
--------
00000
● Now the result is correct using two's complement
● No special hardware required, just add the numbers
● Notice, this results in a carry-out , which we will discuss
next
9 Condition Flags
NZCV
Condition Flags
● ARM maintains program status condition flags as your
code runs.
● These flags are used to capture dynamic state of the
code in execution.
● There are 4 flags, as follows:
Set by the ALU
● Condition flags are set by the ALU
○ and are held in the top 4 bits of the 32-bit Current
Program Status Register (CPSR/APSR)
● Some instructions execute conditionally ,
○ depending on the state of those condition flags
● The four bits are abbreviated to NZCV
● And have an associated bit pattern, eg, 1000
Set and cleared
● Flags are set and cleared based on instructions that
are specifically used for setting and clearing flags
○ eg, TST or CMP
● Other instruction can be told to set the flags by
appending an “S” to their mnemonic.
● For example
○ SUBS R3, R7 //R2=R3-R7 and set condition flags
○ EORS would perform an exclusive OR operation and set
the flags afterward
Instructions that affect condition flags
Note: when an S is appended to the instruction mnemonic,
the condition flags are changed as appropriate
Example: CMP
● CMP – the compare instruction
● It subtracts the 2nd source operand from the 1st
and sets the condition flags based on the result
● If the numbers are equal
○ the result is zero
○ so the Z flag is set to 1
● if op1 < op2
○ the result is negative and N is set to 1
NZCV duration?
How long does the NZVC flags remain after being set?
mov r2, #5
mov r3, #10
cmp r2, r3
NZCV = 1000
● The NZCV pattern (1000) will continue through the
program until such time as some operation changes it
● It does not get "reset" after the CMP
TST instruction
TST (test) ANDs the source operands doesn't affect the V
flag:
MOV R1, #6
TST R1, #1 // is R1 odd?
Here the Z flag is set to 1 because 0001 AND 0110 =
0000
Mnemonic and Condition
The instruction mnemonic is followed by a
condition mnemonic that indicates when
to execute.
CMP R4, R5
ADDEQ R1, R2, R3
● The CMP sets the Z flag if R4 and R5
are equal
● The ADDEQ executes only if the Z flag
is set.
Question
18
Which instruction can change the NZVC here? What is the
state of NZCV after it? What happens to R1?
MOV R1, #0
MOV R2, #5
MOV R3, #6
MOV R4, #4
MOV R5, #4
CMP R4, R5
ADDEQ R1, R2, R3
A note on MOV versus LDR
● MOV is a register-register or immediate to register
operation
● LDR is a memory to register operation
● Sometimes you may see this syntax
LDR R2, =10
The assembler converts this into
MOV R2, #10
N flag
● This flag is useful when checking for a negative result.
● A two’s complement number is considered to be
negative if the most significant bit is set.
● EG -1 -2 = -3
MOV R3, #-1
MOV R4, #-2
ADDS R3, #1
N flag
The addends are positive in two’s complement notation,
but the sum is negative,
MOV r3, #0x7B000000
MOV r4, #0x30000000
ADDS r5, r4, r3 NZCV = 1001
Since the most significant bit is now set, this forces the N bit to be set The
result indicates that this positive sum cannot be represented in 32 bits, so
the result effectively overflowed the precision we had available.
Z Flag
The Z flag tells us is that the result of an operation
produces zero.
● All 32 bits must be zero.
● Add #0xFFFFFFFF and #0x00000001
○ The result is 0 NZCV = 0110
● Subtract #0xFFFFFFFF and #0xFFFFFFFF
○ The result is 0, NZCV = 0110
Carry Flag
The Carry flag is set if the result of an addition is ≥ 232
LDR r3, =0x7B000000
LDR r7, =0xF0000000
ADDS r4,r7,r3 //value exceeds 32 bits
NZCV = 0010
Carry Flag
● The carry flag will also be set in the event of a
subtraction that yields a positive number, for example:
MOV r0, #5
MOV r2, #10
SUBS r4, r2, r0
NZCV = 0010
V Flag
● The V flag indicates an overflow in adding when the numbers
are interpreted as 2's complement (signed) numbers.
● Signed overflow:
○ if the two numbers being added have opposite signs then
overflow is impossible
■ why?
○ if the two number have the same signs but the result has
the opposite sign from the operands then overflow has
occurred.
■ No need to look at the carry.
V flag, example
1010 0001 0010 0011 0100 0101 0110 0111 (2,703,443,303 = -1,591,523,993)
+ 1011 0000 0000 0000 0000 0000 0000 0000 (2,952,790,016 = -1,342,177,280)
0001 0101 0001 0010 0011 0100 0101 0110 0111 (5,656,233,319)
The two numbers of the same sign are added and their
sign inverts. This is an overflow .
NZCV = 0011
A note on SUB and NZCV
In fact, a SUB operation can have a number of condition
flag (NZCV) outputs.
Consider SUBS R0, RX, RY, and NZCV values:
● 0010
● 0110
● 1000
Give some sample values for RX and RY that might yield
this configuration
28 Supervisor Calls
SVC
Supervisor Calls(SVC)
29
● Sometimes there is a need to communicate with the
operating system to implement special functions such as
○ Input and Output (I/O).
● This is done using predefined SuperVisor Calls, e.g: SVC 2
● The parameter can be used to define the function and,
often, other values are passed in registers.
● These actions depend on software – they are not a
function of the ARM processor itself.
Supervisor Calls
30
● An ARM’s true execution mechanism of the SVC depends
on more complications than we want in this module.
● You will not see the SVC code
● You can treat these as ‘magic’ for now