Cadence Tutorial

(VPN Setup and SSH Setup tutorials are for remote access)

Wenpu (Warren) Xia

Prof. Hamed Rahmani
ECE-GY 9423 Comm. Circuits & Components

1. NYU VPN Setup:

Download CISCO AnyConnect Software Client from:

[Link]

Follow the steps given in the above link specific to your system to download CISCO
AnyConnect and establish a new NYU VPN connection.

Open the CISCO Secure Client and the following prompt should show up:

Click “Connect” and redirect to the NYU account login page. After entering your NetID and
Password and passing the Duo Mobile Verification, the status of the CISCO Secure Client will
change to connected:

2. SSH Setup: FastX3 Client:

Download FastX3 client from: [Link] and select the

package that best suits your system’s environment (Mac, Linux, or Windows)

After the installation, you can run the FastX3 Client application and an application window
will pop up (with VPN connected). If you did not have any sessions running before, you will
be shown an empty window like below. To create a new session, click on the “+” icon:

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In the new pop-up window, fill out the name for the connection, which is the hostname
(NOTE: the available ecs node is only [Link]), and username (your NetID).

NOTE: All Fastx3 nodes are clustered, so Fastx3 will always assign students to the least
utilized server! User data will always be available across nodes.

Please see below for example:

1. Enter Host: [Link]
2. Enter User: Your NetID

Press OK to save it. After saving the connection, double-click on the entry and a window
should pop up asking for your password to the machine. Please enter your N NUMBER (most
likely):

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And please don't use copy -paste for your password input. It may cause login failure.

If this isn’t the first session relative to this machine, you may see some previous existing
sessions related to this machine. Please remember to exit/logout of the other sessions when
you finish your work. Many existing sessions will affect system performance.

If there are no previous sessions, you can start a new session by clicking on the “+” button (in
the upper left corner). You'll be presented with the option to start a GNOME or xterm session:

The interface for GNOME is shown below:

To launch Terminal in Gnome:

1. Click Activities on top-left
2. Click On Terminal icon or search for terminal from the top
3. Terminal window pops up

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 NOTE:
1. Please remember to type exit in the terminal to end your session, once your work is
completed.

2. Log Out from the drop-down menu on the right once you have completed your session.

3. Creating a New Library and Cell:

Cadence:
➢ Software location: /eda/cadence
➢ Environment file: /home/<netid>/tcshrc_cadence_local

(make sure that you are familiar with the Linux environment and some of its typical commands
for navigating)

I. Adding gpdk045 into [Link] for Virtuoso

Important: Open a FastX3 terminal session with your NetID credentials (with SSH
connection) to any ecs node, create a directory/folder where you want to save your work
using mkdir command. Then, use cd .. to get back to the main directory and type mkdir
ECS02 to create another directory/folder. In this folder, create the file
tcshrc_ic618_custom (attached with this tutorial). Make sure that every time when you
begin your work, direct to your working directory and type source
../ECS02/tcshrc_ic618_custom before typing virtuoso. The CIW window will then open:

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 Go to Tools → Library Path Editor from the CIW, and you will see several libraries
already defined. You will need to include the GPDK with the process-specific (45 nm)
components.

Exit the virtuoso and open the [Link] file. Make sure these lines are included:

UNDEFINE gpdk045
DEFINE gpdk045 /ALL_PDK/gpdk045_v_6_0/gpdk045

Save the file and reopen Cadence, in Tools → Library Manager, you should be able to
see the gpdk045 library:

II. Creating a New Library and Cell

In the Library Manager, go to File → New → Library. Select the path of your object and
enter a name in the NAME field (myinv in this example). Click OK:

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 The Technology File for New Library form will open, select Reference existing
technology libraries option and click OK:

The Referencing Existing Technology Libraries form will open. Select gpdk045 library
and click the right arrow icon to include it in the Reference Technology Libraries box and
click OK:

This ensures the new library uses the technology of the GPDK. The new library will now
appear in the Library Manager.

Click on myinv in the Library Manager. Go to File → New → Cell View; this will open
the New File form. In this form, enter inv (or other names as you want) as the Cell and
leave the other entries as-is (make sure the Library is what we have created earlier). Click
OK:

This will create a new cell named “inv” in the myinv library and a new view of that cell
named schematic. The schematic cellview is automatically opened.

4. Inverter Schematic Design and Simulation:

I. Schematic Creation Using Virtuoso Schematic Editor

On the schematic canvas, press I to open the Add Instance form. Fill in the form, as shown
below, to place a four terminal nomos device (1v stands for 1V supply voltage) from the
gpdk045 library:
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(In the lower part of the form, you will see the default parameters for this component.)

Press Hide on the form, then place another pmos device (pmos1v) following the same
procedure and place them the way shown below:

Press W to invoke the ‘wiring’ command. To create connections, click where you want the
wire to start. Now click again in free space to create an intermediate point OR on a device
terminal OR another wire to end the command. Double-click or press Enter to complete
the connection that ends in free space. You can also click-drag from one terminal and
release it on the terminal where the connection ends. The final view should be like this:

Make sure that you connect the body terminals of the two transistors (pmos’s to vdd and
nmos’s to gnd). To delete a net or any other component, press Delete and select the
component.

After you finish routing, press Esc. Then, press P to add pins. Fill in the Names field, as
shown below, to create pins for this design:

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 The Direction fields are specified as: input for IN, output for OUT, and inputOutput for
VDD and GND. Press Esc after you finish. The correct pin placement is shown below:

To achieve equal strength, the ratio of PMOS width to NMOS width in an inverter is set to
2. Click the pmos and press Q to open the Edit Object Properties form. Change the finger
with to 240n and select OK. The schematic is now complete. Select the Check and Save
icon. The following information should appear on your CIW to inform you that everything
is correct:

If there are any issues, a Schematic Check window will open and markers will appear on
the canvas alerting you of any issues.

II. Schematic Creation Using Virtuoso Schematic Editor

In the Schematic Editor, select Create → Cellview → From Cellview. Leave the form
as-is and click OK. The Symbol Generation Options form will appear, which allows you to
specify the location for placing each pin. Fill in the form as shown below and click OK.

The symbol is generated with a rectangular shape:

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 To make it resemble a traditional inverter block, you need to edit the shape. Delete the
green rectangle shape and press Esc. Use the tools from the top left toolbar
to create your own shape. Once the editing is complete, click on the Check and Save icon.
If no other window pops up, the symbol is created correctly. A standard inverter symbol
should be like this:

III. Schematic Testbench Creation

Create a new cellview named inv_tb and add the created symbol. Also place instances for
cap, gnd, vdc, and vpulse from the analoglib library in the schematic. To duplicate an
instance, click on that instance and press C. Click again and drag the duplicated instance to
the place you want. Press Esc to exit the copy mode. Specify the properties of the instances
as shown below (cap instance is kept as default):

Make the connection as shown below:

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 Click on the Create Wire Name icon at the top of the toolbar and fill in the form as
shown below:

Press Hide and click on the wires in order to place each label. Press Esc after you finish.
This schematic testbench is now complete:

IV. Pre-layout Simulation

In the schematic, select Launch → ADE L and a new view will pop up:

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Right-click in the Design Variables region and select Copy From Cellview. The vss and
vdd variables that we have created earlier will show up. Fill in the values as shown below:

Click the symbol on the right row to create a new analysis. There are various analysis
types such as trans, ac, dc, etc… that you can explore by yourself. In this example, select
Transient and fill the form as shown below:

Before clicking OK, Press Options and enter 0.001u at the tab labeled step. The above
entries ask the circuit to perform transient simulation from 0 to 10 us, with a step size of
0.001 us: Don't forget to choose Enabled at the bottom of the screen. Click OK:

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Right-click in the Outputs region and select Edit. The Setting Outputs form will show
up. Select From Design and click on the input and output nets. The Table of Outputs will
get updated. Click OK:

Click to run the simulation (make sure that you check and save any changes made to
schematic before running the simulation). After the simulation is completed, an output
window will pop up, and in the spectre file generated, there should be no errors generated:

Try moving the bar on the top of the plot to adjust the viewing area. You can always go
back by pressing F. One of the zoom-in regions is shown below. The green waveform
shows the input to the inverter while the pink one shows the output, which as you can see is
delayed due to the finite capacitive loading:

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 Click to view the plots to see input and output trace in parallel:

Click Session → Save State to save the simulation setup file and Load State to invoke
them. This completes our pre-layout simulation.

5. Layout:

I. Layout Creation

Reopen the inverter schematic, click Launch → Layout XL, keep everything in Startup
Option and New File (pop out after Startup Option) as-is and click OK. If you see the
notification for failing to check license, click Always. The Layout Suite XL Editing
window will open:

Go to Options → Display and ensure the Display Options form looks like the image
below and click OK:

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Go to Connectivity → Generate → All From Source and ensure the Generate layout
form looks like the image below and click OK:

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Press Shift + F to display all layers. Your layout should look as follows:

Press S and left-click to move the edges of any objects.

Go to Place → Pin Placement and select Schematic in the Place As In option. Click on
VDD:VDD:VDD in the Pin Name field and press HRail in the Create field. Do the same
for GND:GND:GND:

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Now that you have placed all components, you need to make connections between them to
create an inverter. To create n-wells, select the pmos and press Q to open the Edit Instance
Properties form. Go to Parameter, change Bodytie Type to Detached and check the Top
Tap option. Click OK:

Do the same for nmos, but this time check the Bottom Tap option instead. The final view
should look like this:

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To make connections, press P and click an edge to begin your connection. The wire will be
automatically extended to the place where you want to end. Press Esc to exit the wiring
mode. We need to first connect the source of pmos to vdd, source of nmos to gnd, and drain
of pmos & nmos together to out. The complete connection is shown below:

Before connecting the gate of the two mos’s, select Poly as the Layer in the left vertical
palette, and go to Create → Shape → Path to create a path connecting the two gates.

Since the input pin is M1 layer and the gate connection is Poly layer, we need a via for
that. Press O to open the Create Via form and select M1_PO as the Via Definition. Rotate
if needed:

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 Then complete the rest of the connections. The final layout schematic should look like this:

II. DRC Tests

To make sure that your layout design follows the physical rules, you will use Design Rule
Checking (DRC) to check this issue.

Go to PVS → Run DRC. In the DRC Run Submission Form, enter run_drc into the
Run Directory field and choose Pegasus as the Use license. Then proceed to the Rules tab
(left side of the window):

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Press on the Technology mapping file row and use (twice) to navigate to and select
ALL_PDK → gpdk045_v_6_0 → [Link]. Choose the gpdk045_pvs technology from
the drop-down list. The form should look as shown below:

If there are more rules listed in the Rules pane, delete them.

Leave the rest of the setup as-is and press Submit. The run will start, and a log file will
appear. For illustration purposes, we remove the n-well implementations:

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 The following results should appear after the run is finished:

As you can see, 7 DRC errors are found. You can click on each error in the left pane and
scroll in the Description to see the source of errors. You can also double-click on the errors
in the right pane to see where each error is in the layout window. As you can see, the main
issue comes from the missing n-wells. A clean DRC results should look as shown below,
where there are no results in checks:

III. LVS (Layout Versus Schematic)

To run layout versus schematic check, go to PVS → Run LVS. Specify run_lvs as the
Run Directory and choose Pegasus as the Use license. Then proceed to the Rules tab and
do the same as in the DRC.

On the Input tab, change the Convert Pin to option to Geometry+Text and change the
Create CDL option to auCDL, as shown below:

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 This will make sure that all pins are correctly identified, even if they are not assigned using
explicit labels.

On the Output tab, enable the Create Quantus Input Data checkbox, as shown below:

You will use it for parasitic extraction later. Leave the rest as default and click Apply. After
the LVS run finishes, a LVS Run Status window should appear. Click Yes and the
following window should appear:

This means that your LVS is clean, and no errors are found in the comparison between your
layout view and your schematic view.

6. Post-Layout Simulation:

To be able to simulate with parasitics, you first need to extract parasitics from your layout. You
will use Quantus to create two parasitic formats: a Detailed Standard Parasitic Format (DSPF)
file and Smart View.

I. Using Quantus to Create a DSPF File

On the layout, go to Quantus → Run PVS - Quantus. Leave everything as-is for the
initiate form and click OK.

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 For the Setup tab in the Quantus (PVS) Parasitic Extraction Run Form, change the
RuleSet to rcx_worst. Scroll down on this tab and change Output to Transistor DSPF;
make sure that the Auto Accuracy Downgrade tab is unchecked.

Proceed to the Extraction tab and fill it in, as shown below:

Click Apply to start the extraction. When the Quantus Run is completed, the following
window should open:

If you check that path, you should be able to see the DSPF file generated.

II. Using Quantus to Create a Smart View:

Again open the Quantus (PVS) Parasitic Extraction Run Form, and for the Output
section in the Setup tab, change to Smart View and specify the View as sv_extracted.
Make sure again that the Auto Accuracy Downgrade tab is unchecked and the settings in
the Extraction tab are the same as in Section I. Click Apply to start the extraction. When
the Quantus Run is completed, the following window should open:

III. Creating a Config View Using Hierarchy Editor and Performing Post-layout
Simulation:

To simulate this file, open the Library Manager and choose the inv_tb cell. Select File →
New → Cell View. In the pop-out form, change the Type to be config and click OK. The
Virtuoso Hierarchy Editor and the New Configuration window will open.

For the New Configuration window, in the View field on the Top Cell section, choose
schematic.

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Click Use Template at the bottom of the dialog box and select spectre as the Name. Your
New Configuration form should be like this. Click OK:

The resulting config view should look as follows:

Right-click on the inv Cell row and select Set Cell View → sv_extracted:

Then click on the toolbar icon to update the changes. Press OK in the pop-up window.
Next, create a similar testbench from Launch → ADE L (You can load the state used for
the earlier testbench). Make sure that the suffix is specified as config in the ADE L
window.

Go to Setup → Simulator/Directory/Host, make sure the Simulator is spectre. Start the

simulation and the resultant waveform traces should look similar to the pre-layout
simulation, as shown below:
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Feel free to compare the two simulations (pre- and post-layout) by yourself and observe the
effects of the extracted parasitics on the rising and falling delay of the inverter.

This concludes our Cadence Tutorial!

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