ELECTRONIC SCIENCE UNIT-2

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 ELECTRONIC SCIENCE UNIT-2

Integrated circuit fabrication

Introduction

The starting material for integrated circuit (IC) fabrication is the single
crystal silicon wafer. The end product of fabrication is functioning chips
that are ready for packaging and final electrical testing before being
shipped to the customer. The intermediate steps are referred to as
wafer fabrication (including sort). Wafer fabrication refers to the set of
manufacturing processes used to create semiconductor devices and
circuits. Some common wafer terminology used are chip, die, device,
circuit, and microchip. These refer to patterns covering the wafer
surface that provide specific functionality. The terminology die and chip
are most commonly used and interchangeably refer to one standalone
unit on the wafer surface. Thus, a wafer can be said to be divided into
many dies or chips, as shown in figure 1.

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Figure 1: Schematic of wafer showing the division into individual dies. One
individual die with electrical contacts is also shown. Some of these dies are used
for testing. Dies at the edge dies are incomplete. Adapted from Microchip
fabrication - Peter van Zant.

Figure 2: Schematic of various components of a wafer. (1) Chip (2) Scribe line (3)
Test die (4) Edge chips (5) Wafer crystal plane (6) Flats/notches.

The area between the dies is called a scribe line. This is used for
separating the individual dies when the fabrication is complete. Scribe
lines can be blank but most often they consist of test structures that are
used for electrical testing (e-test) during fabrication. This helps in
identification of process issues during fabrication, without having to
wait for the entire chip to be made.

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Along with the regular ICs, test dies or engineering dies are also
fabricated. These dies are used for electrical testing at the end, for
process or quality control. There are also some partial or edge dies at
the corners of the wafers. These arise because the wafers are circular
while the dies are usually rectangular. Corner dies can be used for
making smaller testing circuits for process control.

The various elements described above are marked in figure 2. Larger

the wafer, more the number of chips that can be manufactured
(including edge chips). Consider the Intel i7 core processor (codename
Ivybridge) with a die area of 160 mm2 . For 300 mm wafers, this
translates to a total of 440 dies (including edge chips), while with 450
mm wafers, the total number of dies are 994 (area of wafer by area of
die calculation). To exclude edge chips, we can take the die to be a
square. This gives 281 dies for 300 mm wafers and 633 dies for the
larger 450 mm wafers.

Thus, it is more economical to manufacture on larger wafers, but there

will be initial tool costs associated with larger wafers. There are a
number of different steps in IC fabrication. Typically, a wafer can moves
from one processing step to another, similar to an assembly line
manufacturing. There are also inspection steps in the process flow to
check for quality. There are different schemes for classifying the
processing steps in IC fabrication. In one such scheme, the basic fab
operations (processing steps) are divided into four main categories.

1. Layering
2. Patterning
3. Doping
4. Heat treatment

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Layering

The layering step is used to add thin layers to the wafer surface. These
layers can be of a different material or a different microstructure or
composition of the same material (polycrystalline Si or silicon oxide).
Figure 3 shows the cross-section of a simple MOSFET, highlighting the
various thin layers that are part of the device. The different layers help
in defining the various components of the MOSFET and in obtaining a
functional device e.g. the passivation layer helps in electrically isolating
the metal contacts to the source, drain and gate. Layering can be of
many different types, though they can be broadly classified into two
main categories: grown and deposited. The various types of layering
operations are shown in figure 4.

In the case of grown layers, the underlying wafer material (typically Si)
is consumed. A classic example is the growth of the oxide layer, as
shown in the MOSFET structure in figure 3. This is formed by oxidation
of Si into SiO2 and is usually done in two ways.

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Figure 3: Cross section of a MOSFET showing the different layers. Poly Si is used as
gate with SiNx used as the interlayer dielectric. Layering is the process by which
all of these different materials are added to the MOSFET.

Figure 4: Different kinds of layering steps. All layering steps are classified into two
major types. Grown layers use the underlying silicon substrate to form new layers.

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Deposited layers do not consume the silicon but are added to the surface.
Adapted from Microchip fabrication - Peter van Zant.

Figure 5: CVD process for growth of Si. Polycrystalline Si is formed by reduction of

tetra chlorosilane by H2, which is deposited on the wafers. The poly Si can be
doped and is used as gate for the MOSFET.

In both cases, the SiO2 layer is formed on the surface by consuming the
underlying Si layer. For further oxidation, the oxidizing species (O2 or
H2O) has to diffuse through the oxide to reach the Si surface. Similarly,
nitrides can also be grown by consumption of Si.

In the case of deposited films, the underlying Si is not consumed but a

new layer is added on top. An example of this is the growth of epitaxial
layers by a chemical vapor deposition (CVD) process. The epitaxial layer
grown can be the same material as the substrate (homoepitaxy) or can
be a different material (heteroepitaxy). Si can be grown epitaxially on Si
wafers by reduction of tetra chlorosilane.

SiCl4 (g) + 2H2 (g) → Si (s) + 4HCl (g) (2)

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The process is shown in figure 5. The chemical reaction in CVD takes

places in the vapor phase. It is very useful for growing high aspect ratio
structures like trenches, where CVD provides conformal coatings.
Figure 6 shows an exzmple of CVD growth of CrB2 on deep trenches by
CVD.

Molecular beam epitaxy (MBE) is another growth technique where the

constituents of the epitaxial layer are evaporated from separate
sources (’molecular beam’) and then combine on the substrate to form
the epitaxial layer. It is also possible to introduce dopants in this
process by evaporating the dopant material separately. GaAs can be
grown by MBE by evaporating from Ga and As sources. To dope this p-
type, Be can also be evaporated in the required concentration along
with Ga and As.

Thermal evaporation and sputtering are other examples of layering

operations. These fall under physical vapor deposition techniques
where the material, in the final form, is deposited onto the wafer. This
can be used for

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Figure 6: Chromium boride coatings grown by CVD in deep trenches. The coatings
are highly conformal to the trench dimensions. This cannot be achieved by other
deposition techniques since the opening will be filled up before depositing in the
trench.

Metals, oxides, nitrides, and other types of layers. Electroplating is

another layering operation. This is mainly used for depositing copper,
which is used as interconnects in the IC.

Patterning

Patterning or lithography is one of the most important steps in wafer

fabrication. Patterning refers to a series of steps to selectively mask or
expose portions of the surface for deposition/doping/etching. It sets
the critical dimensions of the device. The drive to pack more devices in
a chip (smaller devices) is directly related to the ability to pattern
smaller regions in the wafer. The challenges in reduction of device size
in recent ICs is related to patterning. The process is highly defect
sensitive, especially at smaller sizes, as shown in figure 7. Presence of
defect particles in the pattern can affect the later steps like
deposition/doping/etching and can also affect pattering of other layers.

To make a pattern, reticle has to be first prepared. Reticle refers to the

hard copy of the design that is then transferred on to the chip. This
hard copy

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Figure 7: Effect of defect particles on patterning process. Defects that cause

damage to the ICs are called killer defects. Not all defects are killer defects, but
with reduction in size, more defects can turn into killer defects.

is generated by ‘writing’ the pattern, using a laser beam or electron

beam, and is usually done on chrome coated glass. The design is then
copied on to the chip using a suitable photoresist and UV exposure. The
pattern transfer can be 1 : 1 or the size can be reduced by a suitable
lens system. Either the pattern or its negative can be transferred by
suitable choice of photoresist and the process is summarized in figure
8.

Use of photoresists for patterning is an example of a soft mask since

the mask can be easily removed without damaging the underlying
substrate. Sometimes oxide or nitride layers are also used as masks for
pattern transfer. These are called hard masks, since these masks can
withstand high temperature while resists cannot and they also need
aggressive chemical procedures for removal. Thus, it is difficult to
combine lithography with deposition processes like CVD (where hard

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mask would be needed) but it can be used with processes like thermal
evaporation, sputtering, and e-beam deposition.

Doping

Doping refers to the process where specific amounts of electrically

active ’impurities’ are incorporated through openings on the wafer
surface. The dopant materials are typically p or n type impurities and
they are needed to form devices like diodes, transistors, conductors,
and other electronic devices

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Figure 8: Overview of the patterning process, showing both positive and negative
photoresists. Positive resists directly transfer the pattern from reticle to wafer,
while negative resists transfer the inverse of the pattern.

Figure 9: p or n type doped region in a wafer. An oxide layer is used as a hard

mask to control the region where doping occurs.

Typical p type impurities, for Si, include B while n type impurities can be
As, P, or Sb. The formation of a doped region in a section of the wafer is
shown in figure 9. There are two main techniques for doping

1. Thermal diffusion
2. Ion implantation

Both processes produce different dopant concentration profiles at and

below the surface, as shown in figure 10.

1. Thermal diffusion

As the name implies, in thermal diffusion, doping is carried out by

movement of the dopant material from the surface to the bulk, by a
thermally activated process. The diffusion can be initiated from dopants
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in a vapor, liquid, or a solid source. The wafer has to be heated to high

temperature, around 1000 ◦C, to speed up the diffusion process. Thus,
thermal diffusion cannot be used with soft lithography masks and a
hard mask like oxide or nitride is used. For n type doping in Si, some
typical dopant materials are Sb2O3 (s), As2O3 (s), AsH3 (g), POCl3 (l), P2O5
(s), and PH3 (g). For p type doping, typical materials are BBr3 (l), B2O3 (s)
and BCl3 (g). Thermal diffusion is an isotropic process (though diffusion
rates might be different in different directions). This leads to lateral
spread of the dopants, as seen in figure 10, at higher temperatures and
long times, and makes doping in small confined regions difficult. Also,
the high temperature means that thermal diffusion

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Figure 10: Schematic of the doping process and concentration profiles in (a)
thermal diffusion and (b) ion implantation. In thermal diffusion, the highest
concentration is at the surface while for ion implantation, the highest
concentration is below the surface.

cannot be used in the later stages of the fabrication process, since

there could be a number of layers that might not be able to withstand
the high temperature.

2. Ion implantation

For doping in specific regions, ion implantation is used. Here, the

dopant atoms are ionized and then made to impinge on the wafer
surface where they penetrate and get ‘implanted’ into the wafer. The
advantage of this process is that doping can be done at room
temperature so that soft masks can be used. This also enables doping in
small regions since lateral diffusion is minimized. Ion implantation
causes beam damage so there is a rapid annealing treatment post
implantation to repair the wafer and ‘activate’ the dopants.

Heat treatment

Heat treatment operations are usually part of the other three

operations i.e. layering, doping, and patterning. Some of the heat
treatment operations in these steps are summarized in table 1.

Table 1: Heat treatment operations in IC fabrication. The link with other

fabrication steps is tabulated.

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MOSFET fabrication

Consider the fabrication of a Si MOSFET device as an example to

illustrate the various types of fab processes. The various steps in
fabricating the device, starting from the bare wafer, are shown in figure
11. The process goes through various steps which fall under the
categories listed above. Starting from the bare wafer, the various steps
to get the finished MOSFET are listed below. The individual stages can
be followed using figure 11.

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Figure 11: An overview showing the various steps in MOSFET fabrication. (a)
Staring wafer is (b) oxidized and then (c) patterned to grow the field oxide. (d)
Poly Si is then deposited and (e) patterned to form the gate on top of the oxide.
(f) A further patterning and doping is done to define the source and drain and (g)
finally metallization is done to define the contacts.

1. Layering - the first step is the growth of an oxide layer (field oxide).
This is used as hard mask for patterning.
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2. Patterning - next an opening is created in the field oxide for growing

source, drain and the gate oxide. Patterning refers to the series of steps
that create this opening in the oxide.

3. Layering - the field oxide is removed (etched) and then the gate
oxide is grown. In early MOSFETs, this was just SiO2, but later devices
use oxy nitrides and high-k dielectrics.

4. Layering - a layer of poly-Si is deposited on top of the gate oxide. This

forms the gate electrode. Typically poly Si is grown by a CVD process.
Initially, the poly Si is deposited uniformly.

5. Patterning - two openings are then created in the gate oxide layer.
This is for making the source and drain. The gate region is masked and
the material (poly Si and SiO2) in the remaining regions are removed by
a process called etching (opposite of layering).

6. Doping - doping is used to create the n regions (source and drain).

This is when the base Si is a p-type Si.

7. Layering - an uniform oxide layer is now grown on top. This will be

used to insulate the source, drain, and gate, when electrical contacts
are made.

8. Patterning - openings are created in the oxide layer for making the
electrical contacts. The remaining oxide layer helps in electrical
insulation.

9. Layering - metal is deposited to make the electrical contacts. In the

earlier MOSFETs, Al was the metal of choice though now Cu is used
with a suitable barrier layer, typically tungsten nitride or silicide.

10. Patterning - the excess metal is removed from the device.

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11. Heat treatment - the MOSFET is annealed so that better electrical

contacts can be made. In some cases the Si reacts with the metal to
form silicides, which form Ohmic contacts with Si.

12. Layering - oxide layers are grown on top to form a passivation layer.
This also acts as a protection layer for the device.

13. Patterning - the last step is a patterning step to creates holes in the
passivation layer for the electrical contacts to the external circuits. This
step and the one above it are not shown in figure 11.

This 13-step process illustrates the various steps to make a MOSFET

from Si. Similarly, there are steps for making other device components.
All of these are integrated to make the final IC circuit. Along with
processing, there are inspection steps at various stages and electrical
testing at the end. This is to make sure that device specifications are
correctly implemented. This includes the physical dimensions of the
various components (width and height) and the electrical properties (I-
V characteristics).

Crystal Growth

Crystal Growth Before the fabrication of the integrated circuit, the

preparation of silicon or gallium arsenide wafer is required. The
preparation of wafer involves several process steps. They are
distillation and reduction/synthesis, crystal growth, grind/saw/polish,
and electrical and mechanical characterizations.

The starting material is silicon dioxide for making silicon wafer. It is

chemically processed to form a high-purity crystal polycrystalline
semiconductor for which single crystal is formed. The single crystal
ingot is shaped to define diameter and is sawed into wafer. The wafer is
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then etched and polished to provide smooth, specular surface where

device is fabricated.

Pure form of sand SiO2 called quartzile is placed in high temperature

furnace with various forms of carbon like coke, coal, and even wood
chip. Owing silicon dioxide is very stable, carbon is used to replace
silicon to form carbon dioxide at reduce temperature. Although there
are numbers of reaction take place and the overall reaction follows
equation (2.1).

SiO2 + 2C → Si + 2CO↑ (2.1)

This process generates polycrystalline silicon with about 98% to 99%

purity called crude silicon or metallurgical-grade silicon MGS.

In next process step is the silicon purification step. Silicon is pulverized

and treated with hydrochloric acid gas HCl at temperature 3000C to
form trichlorosilane SiHCl3 vapor. The chemical reaction follows
equation (2.2).

Trichlorosilane TCS vapor is then gone to fractional distillation to

remove unwanted impurities through a series of filters, condensers
(boiling point 320C), and purifiers to finally get an ultra high purity liquid
of purity higher than 99.9999999% at room temperature. The high-
purity TCS is then used in the hydrogen reduction reaction at
temperature 1,1000C to produce the electronic grade silicon EGS.

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The reaction takes place in a reactor containing resistance heated

silicon rod, which serves as the nucleation point for deposition of EGS in
polycrystalline form of high purity. This is the raw material used to
prepare device quality single crystal. Pure EGS has impurity
concentration generally in part per billion.

The pure EGS is then ready to be pulled into silicon ingot for making
wafer for integrated circuit fabrication. There are a number of methods
used to grow silicon crystalline ingot. We shall discuss two methods
here namely Czochralski and Float-zone methods. Other methods such
as horizontal zone furnace, which are BridgemanStockbarger technique,
liquid encapsulated Czochralski LEC are not discussed here.

1. Czochralski Crystal Growth Method

The polycrystalline silicon is melt at temperature 1,4150C just above the

melting point temperature of silicon, which is 1,4150C, in the argon Ar
atmosphere in quartz crucible by radio frequency RF or resistive
heating coil. Right type and the amount of dopant are then added. With
the aid of “seed”, silicon rod of right diameter is formed by rotation and
pulling in Czochralski CZ puller as shown in Fig. 2.1. Figure 2.1(a) shows
the photograph of a modern computer-controlled Czochralski crystal
puller. Figure 2.1(b) is the schematic drawing showing the components
of the puller.

Once thermal equilibrium is established, the temperature at the vicinity

of the seed is reduced and the molten silicon begins to freeze out onto
the seed crystal. Subsequently, the seed is slowly rotated and
withdrawn at the rate of a few millimeter per minute to form a
cylindrically shaped single crystal of silicon, which is known as ingot.

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The diameter of the crystal in CZ method can be controlled by

temperature and pulling rate using automatic diameter control system.
Typically, 4 to 6 inch diameter and 1 to 2 meter in length type of ingot
can be formed. In today’s process, ingot of diameter as large as 12
inches is commonly produced to save cost and improve productivity.
However, for large ingot as large as 12 inches in diameter, an external
magnetic field is applied around the crucible and it is used to control
the concentration of defects, impurities, and oxygen.

I. Impurity of Czochralski Process

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The crystal ingot growth by Czochralski method always has trace

impurities of oxygen and carbon, which come from silica and graphite
crucible materials. Silica is silicon dioxide is the source of oxygen. Silica
will react with graphite to form carbon monoxide, which is the source
of carbon. The equation of chemical reaction is in equation (2.4).

SiO2 + 3CSiC + 2CO (2.4)

Concentration of Czochralski Process In the crystal growth process, the

most common dopants is boron and phosphorus, which are used to
make p- and n-type semiconductor materials respectively. As the
crystal is pulled from the molten silicon, the doping concentration
incorporated into the crystal is usually different from the doping
concentration of the molten silicon at the interface. The ratio of these
two concentrations is defined as the equilibrium segregation coefficient
k0, which is defined in equation (2.5).

(2.5)

where CS and CI are respectively the equilibrium concentration of the

dopant in the solid and liquid near interface. Figure 2.2 shows the
equilibrium segregation coefficient for common dopants used for
silicon. The value below one means that during the growth the dopants

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are rejected into the molten silicon. As the result, the dopant
concentration of molten silicon becomes higher as time lapsed.

Consider a crystal being growth from the initial molten silicon of weight
Mo with an initial doping concentration CO (the weight of dopant per 1g
of molten silicon) in the molten silicon. At a given time, a crystal of
weight M has been grown, the amount of the dopant remaining in the
molten silicon by weight is S. For an incremental amount of the crystal
with weight dM, the corresponding reduction of the dopant -dS from
the molten is CSdM, where CS is the doping concentration in the crystal
by weight.

(2.6)

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Solving equation (2.9) and combining equation (2.7), it yields equation

(2.10)

(2.10)

During the growth of silicon ingot, dopant is constantly being rejected

into the molten silicon. If the rejection rate is higher than the rate at
which the dopant can be transported away by diffusion or stirring, then
a concentration gradient will develop at the interface as shown in Fig.
2.3. The equilibrium segregation coefficient is k0 = CS/CI(0). We can
define an effective segregation coefficient ke , which is the ratio of CS
and the impurity concentration far away from the interface.

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(2.14)

Pull Rate of Czochralski Process

Pertaining pull rate of Czochralski crystal growth, one expects the pull
rate should be slower for larger diameter ingot. Indeed the pull rate is
inversely proportional to the square root of diameter of ingot. It can be
derived based on the first order heat balance equation, which
represents the dominant heat fluxes present during freezing process.
Reference to Fig. 2.4, x1 is a constant temperature surface, which is
isotherm just inside the liquid. X2 is an isotherm just inside the solid.
During freezing process, which occurs between these isotherms, heat is
released to allow the silicon to transform from liquid to solid state,
which is heat of fusion. This heat must be removed from freezing
interface. It is a primary process of heat transfer by conduction up to
the solid ingot. Thus, one can write equation (2.16).

where L is the latent heat of fusion, dm/dt is the amount of silicon

freezing per unit time, kL is the thermal conductivity of liquid, dT/dx1 is
the temperature gradient across the isotherm x1, ks is the thermal

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conductivity of the solid. dT/dx2 is the temperature gradient across the

isotherm x2, and A1 and A2 are respectively the cross sectional areas.

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Equation (2.26) has clearly shown that the maximum pull rate VpMAX is
proportional to square root of the ingot’s radius.

Float-Zone Crystal Growth Method

The float-zone crystal growth method is illustrated conceptually in Fig.

2.5. The crystal is not grown in the crucible that it has markedly
reduced the impurity level particularly the level of oxygen and carbon.
It is grown in sealed furnace with argon Ar gas. This method is used
today for fabricating device that requires high resistivity and low
oxygen content in the power device and detector device.

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In the float-zone process, a polysilicon rod of EGS is clamped at both

ends, with bottom in contact with a single-crystal seed. A small RF coil
provides large current in silicon that locally melts the silicon. The
molten zone is usually 2.0cm long. The liquid phase silicon is then
bonded to the atomic plane of the seed plane by plane as the zone is
slowly moved up. Doping of the crystal can be achieved by either
starting with a doped polysilicon rod, a doped seed, or maintaining a
gas ambient during the process that contains a dilute concentration of
the desired dopant.

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Segregation effect also plays an important role in the float-zone process

just as it did in Czochralski method. It is illustrated from derivation of
concentration of solid silicon CS(x) formed as it moves from molten
state at the bottom to the top.

Figure 2.6 shows the idealized geometry of zone length L. The rod has
initial concentration of C0.

Figure 2.6: Float-zone crystal growth process from liquid zone at the bottom
moving to top

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(2.29)

As compared to Czochralski method, float-zone method has a greater

resistivity variation. Thus, Czochralski method is still the dominant
method for large diameter silicon crystal. The melt-crystal interface is
very complex for floatzone method, so it is difficult to get dislocation
free crystal. Unlike Czochralski method, it needs a high-purity
polysilicon to begin.

Epitaxy

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A method for growing or depositing mono crystalline films on a

substrate.

Epitaxy is a method to grow or deposit monocrystalline films on a

structure or surface. There are two types of epitaxy-homoepitaxy and
heteroepitaxy. Homoepitaxy is a process in which a film is grown on a
substrate of the same composition. Heteroepitaxy is a film that is
grown on a substrate, which has a different composition.

Epitaxial silicon is grown using vapor-phase epitaxy (VPE). This is a

modification of chemical vapor deposition (CVD). Another technology,
molecular-beam epitaxy (MBE), is mainly for compound
semiconductors. MBE is a slow, line-of-sight technique, not suitable for
filling trenches and other three-dimensional structures.

For silicon processes, epitaxy is used in source-drain and strain

engineering techniques. They are also playing a big role in the channel
in chip designs.

The big change in the channel took place at 90nm, when the industry
introduced strain engineering in the region. Using a blanket epitaxial
process, chipmakers integrated silicon-germanium (SiGe) stressors, or
distortions in the crystal lattice, in PMOS transistors. This, in turn,
boosted hole mobility and drive current.

Using the same epi process, chipmakers are moving towards strain
engineering for the NMOS starting at 20nm. The NMOS transistors
require a tensile strain, enabling a boost in drive current.

Still, today’s strained-silicon technology is under stress. So, chipmakers

may need to make a materials change in the channels at 10nm or 7nm.
At one time, the leading candidate was germanium (Ge) for PMOS and
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indium-gallium-arsenide (InGaAs) for NMOS. (Ge has an electron

mobility of 3,900cm-square-over-Vs, compared to 1,500cm-square-
over-Vs for silicon. InGaAs has an electron mobility of 40,000cm-
square-over-Vs.)

Ge and III-V are fast but difficult to implement due to the lattice
mismatch with silicon. Now, the industry is looking at a simpler
approach. Chipmakers will likely use SiGe for PMOS at 10nm or 7nm,
depending on the company and requirements. For NMOS, the industry
may stick with tensile silicon.

In any case, there are two main approaches in terms of depositing Ge,
SiGe or III-V materials in the channels–blanket and selective epi. The
blanket approach calls for the epi materials to be grown everywhere on
the surface. In selective, the epi materials are only grown on a select
part of the surface.

At present, some prefer the traditional blanket approach. The blanket

approach has some drawbacks, however. With blanket epi, a chipmaker
may end up depositing materials on unwanted regions. In that case, the
IC vendor must etch away those materials. All told, blanket epi may
have more process steps, possibly making it more expensive.

For that reason, selective epi is also viable. In selective, a tool can mix
and match materials with other types of materials. But in some
respects, it is far more complex than blanket epi.

Imec, for one, has demonstrated a selective growth process, depositing

germanium and InGaAs pillars into patterned oxide trenches to make a
“virtual substrate” for device fabrication. Using this technique, Imec

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demonstrated what it believes to be the first III-V finFETs integrated

epitaxially on 300mm silicon wafers.

Imec’s process starts by using standard shallow trench isolation

processes to create a template, with pillars of silicon surrounded by
silicon dioxide. Then, a silicon dioxide cap is deposited over the areas
where InGaAs will ultimately go. In the uncapped regions, the silicon
pillars are etched away, and the exposed trenches filled with
germanium. Next, the germanium is capped with silicon dioxide and the
InGaAs areas are exposed.

InGaAs pillar formation begins by etching out the silicon pillars to

create a concave bottom surface, slightly wider than the ultimate
trench width. Successive depositions of germanium, InP, and InGaAs
follow, gradually accommodating the lattice mismatch between silicon
and InGaAs. The narrow trenches are key to this process: because of
the rounded bottom surface, dislocations tend to form at an angle to
the sides of the trench, and are trapped against the sidewalls rather
than propagating through the InP and InGaAs bulk. An active layer with
acceptable quality is achieved with a thinner, less time-consuming
deposition. Moreover, with selective deposition there is no need to
etch InGaAs, or to dispose of toxic arsenic-based etch by-products.

Epitaxy, the process of growing a crystal of a particular orientation on

top of another crystal, where the orientation is determined by the
underlying crystal. The creation of various layers
in semiconductor wafers, such as those used in integrated circuits, is a
typical application for the process. In addition, epitaxy is often used to
fabricate optoelectronic devices.

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The word epitaxy derives from the Greek prefix epi meaning “upon” or
“over” and taxis meaning “arrangement” or “order.” The atoms in an
epitaxial layer have a particular registry (or location) relative to the
underlying crystal. The process results in the formation of crystalline
thin films that may be of the same or different
chemical composition and structure as the substrate and may be
composed of only one or, through repeated depositions, many distinct
layers. In homoepitaxy the growth layers are made up of the same
material as the substrate, while in heteroepitaxy the growth layers are
of a material different from the substrate. The commercial importance
of epitaxy comes mostly from its use in the growth of semiconductor
materials for forming layers and quantum wells in electronic and
photonic devices—for example, in computer, video display, and
telecommunications applications. The process of epitaxy is general,
however, and so can occur for other classes of materials, such as metals
and oxides, which have been used since the 1980s to create materials
that display giant magnetoresistance (a property that has been used to
produce higher-density digital storage devices).

In vapour phase epitaxy the deposition atoms come from a vapour, so

that growth occurs at the interface between gaseous and solid phases
of matter. Examples include growth from thermally vaporized material
such as silicon or from gases such as silane (SiH4), which reacts with a
hot surface to leave behind the silicon atoms and to release
the hydrogen back into the gaseous phase. In liquid phase
epitaxy layers grow from a liquid source (such as silicon doped with
small amounts of another element) at a liquid-solid interface. In solid
phase epitaxy a thin amorphous (noncrystalline) film layer is first
deposited on a crystalline substrate, which is then heated to convert
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the film into a crystalline layer. The epitaxial growth then proceeds by a
layer-by-layer process in the solid phase through atomic motion during
the recrystallization at the crystal-amorphous interface.

There are a number of approaches to vapour phase epitaxy, which is

the most common process for epitaxial layer growth. Molecular beam
epitaxy provides a pure stream of atomic vapour by thermally heating
the constituent source materials. For example, silicon can be placed in
a crucible or cell for silicon epitaxy, or gallium and arsenic can be placed
in separate cells for gallium arsenide epitaxy. In chemical vapour
deposition the atoms for epitaxial growth are supplied from
a precursor gas source (e.g., silane). Metal-organic chemical vapour
deposition is similar, except that it uses metal-organic species such
as trimethyl gallium (which are usually liquid at room temperature) as a
source for one of the elements. For example, trimethyl gallium
and arsine are often used for epitaxial gallium arsenide
growth. Chemical beam epitaxy uses a gas as one of its sources in a
system similar to molecular beam epitaxy. Atomic layer epitaxy is based
on introducing one gas that will absorb only a single atomic layer on the
surface and following it with another gas that reacts with the preceding
layer.

Epitaxial Growth

 Epitaxy means the growth of a single crystal film on top of a

crystalline substrate.
 For most thin film applications (hard and soft coatings, optical
coatings, protective coatings) it is of little importance.
 However, for semiconductor thin film technology it is crucial.

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Epitaxial growth process

 Epitaxial growth is the process used to grow a thin crystalline

layer on a crystalline surface (substrate).
 The substrate wafer acts as seed crystal.
 In this process , crystal is grown below melting point , which uses
an evaporation method.

Types of Epitaxy

Homoepitaxy

– The film and the substrate are the same material.

– Often used in Si on Si growth.
– Epitaxially grown layers are purer than the substrate and can be
doped independently of it.

Heteroepitaxy

– Film and substrate are different materials.

– Eg: AlAs on GaAs growth
– Allows for optoelectronic structures and band gap engineered
devices.

Homotopotaxy

Homotopotaxy is a process similar to homoepitaxy except that the thin-

film growth is not limited to two-dimensional growth. Here the
substrate is the thin-film material.

Heterotopotaxy

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Heterotopotaxy is a process similar to heteroepitaxy except that thin-

film growth is not limited to two-dimensional growth; the substrate is
similar only in structure to the thin-film material.

Pendeo-epitaxy

Pendeo-epitaxy is a process in which the heteroepitaxial film is growing

vertically and laterally at the same time. In 2D crystal heterostructure,
graphene nanoribbons embedded in hexagonal boron nitride give an
example of pendeo-epitaxy.

Epitaxy is used in silicon-based manufacturing processes for bipolar

junction transistors (BJTs) and modern complementary metal–oxide–
semiconductors (CMOS), but it is particularly important for compound
semiconductors such as gallium arsenide. Manufacturing issues include
control of the amount and uniformity of the deposition's resistivity and
thickness, the cleanliness and purity of the surface and the chamber
atmosphere, the prevention of the typically much more highly doped
substrate wafer's diffusion of dopant to the new layers, imperfections
of the growth process, and protecting the surfaces during manufacture
and handling.

Heteroepitaxy

 Trying to grow a layer of a different material on top of a substrate

leads to unmatched lattice parameters.
 This will cause strained or relaxed growth and can lead to
interfacial defects.
 Such deviations from normal would lead to changes in the
electronic, optic, thermal and mechanical properties of the films.

Lattice Strains
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 For many applications nearly matched lattices are desired to

minimize defects and increase electron mobility.
 As the mismatch gets larger, the film material may strain to
accommodate the lattice structure of the substrate. This is the
case during the early stages of film formation (pseudomorphic
growth) and with materials of the same lattice structure. The Si-
Ge system is an example.
 If strain accommodation is not possible then dislocation defects at
the interface may form leading to relaxed epitaxy and the film
returns to its original lattice structure above the interface.
 Lattice misfit is defined as:

Metal-Semiconductor Heteroepitaxy

 Metal-semiconductor structures are used for contact applications.

 While not essential, epitaxial growth allows increased electron
mobility through a junction.
 Examples:
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– CoSi 2 or NiSi 2 on Si. Since the lattice mismatch is small (all

around 5.4 Ǻ) and the crystal structures are similar,
interfaces are remarkably defect free.
– Fe on GaAs is similarly possible since the lattice size of Fe is
about half of GaAs.
– The lattice constants of Al and Ag are ~1/ √2 of GaAs. In this
case the crystal orientation of the film is rotated with
respect to the substrate. A few layers of intervening metal
(such as Fe or Ga) can be deposited to foster epitaxy.

There are three techniques used in Epitaxial process :

 Chemical vapour Deposition (CVD)

 Molecular Beam Epitaxy (MBE)
 Liquid Phase Epitaxy (LPE)

Epitaxial processes are used to add varying proportions of donor or

acceptor impurities as per requirement.

Four silicon sources are used for growing Epitaxial silicon :

 Silicon tetrachloride
 Silane
 Di-chlorosilane
 Tri-chlorosilane

The three major epitaxial growth processes used to produce layers of

material for electronic, optical, optoelectronic and magneto-optical
applications. These are liquid-phase epitaxy (LPE), metal organic
chemical vapor deposition (MOCVD), and molecular beam epitaxy
(MBE) and their main variants.

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Liquid Phase Epitaxy

Liquid phase epitaxy (LPE) is the deposition from a liquid phase (a

solution or melt) of a thin single crystalline layer isostructural with the
substrate crystal. Usually LPE is performed using a solution as the liquid
phase, because this is advantageous against the cases when a melt is
used. In comparison to the growth from melts, growth from solutions:
LPE involves the precipitation of a crystalline film from a supersaturated
melt on to a substrate. The temperature is increased until a phase
transition occurs and then reduced for precipitation. By controlling
cooling rates the kinetics of layer growth can be controlled. Once can
have either continuous reduction with the substrate (equilibrium
cooling) or separate reduction in increments followed by contact with
the substrate (step cooling). It is a low cost method yielding films of
controlled composition, thickness and lower dislocation densities.
Disadvantages are rough surfaces and poor thickness uniformity.

(i) allows for epitaxy at lower temperatures,

(ii) enables better control of the amount of the crystalline
phase grown or removed by dissolution,
(iii) leads to crystallization oflayers with lower densities of
defects, whether intrinsic (point defects) or extrinsic (e.g.,
impurities dissolved from crucible material),
(iv) makes it possible to grow layers sequentially from a series
of solutions of differing composition, but with very similar
and readily controlled liquidus temperature (liquidus is
the border-line on the "temperatureconcentration
(composition)" phase diagram between the pure liquid
region and the solid-liquid co-existence region (see Sect.
11.3)), and last but not least,
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(v) allows for considerable reduction of the vapor pressure of

volatile components of the compounds (e.g., P in the case
of InP and As in the case of GaAs) by working at
temperatures far below the melting point.

It is worth emphasizing that LPE operates near thermodynamic

equilibrium, which results in low nutrient fluxes and makes mass
transport and diffusion effects more important, while diminishing the
importance of surface reaction and incorporation phenomena.

There are essentially two ways of promoting growth from a liquid

solution on the solid substrate crystal: either the substrate may be
immersed in the supersaturated solution, or this solution may be
transported into the region of the crucible in which the substrate is
located. There are, however, many variations of these basic processes
differing more or less in the details. The thermodynamic driving force
for LPE is normally generated by cooling the substrate below the
liquidus temperature on the relevant phase diagram. An LPE procedure
consists, thus, of providing mechanisms for:

(a) creating supersaturation of the solution,

(b) introduction of the substrate platelet upon which the
precipitation of the solid film from the solution will occur,
(c) controlling the morphology, uniformity and perfection of the
epilayer, and
(d) removing from the melt the substrate with the epilayer grown on
it. Steps (b - d) are repeated for multiple layer growth, where
layers of different composition and/or doping are grown
sequentially on the same substrate.

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Furnaces for Liquid Phase Epitaxy - LPE

Liquid phase epitaxy (LPE) is a method to grow semiconductor crystal

layers from the melt on solid substrates. This happens at temperatures
well below the melting point of the deposited semiconductor. The
semiconductor is dissolved in the melt of another material. At
conditions that are close to the equilibrium between dissolution and
deposition the deposition of the semiconductor crystal on the substrate
is slowly and uniform. The equilibrium conditions depend very much on
the temperature and on the concentration of the dissolved
semiconductor in the melt. The growth of the layer from the liquid
phase can be controlled by a forced cooling of the melt. Impurity
introduction can be strongly reduced. Doping can be achieved by the
addition of dopants.

The method is mainly used for the growth of compound

semiconductors. Very thin, uniform and high quality layers can be
produced.

A typical example for the liquid phase epitaxy method is the growth of
ternery and quarternery III-V compounds on Galliumarsenid GaAs
substrates. As a solvent quite often Gallium is used in this case. Another

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frequently used substrate is Indiumphosphide InP. However also other

substrates like glass or ceramic can be applied for special applications.
To facilitate nucleation, and to avoid tension in the grown layer the
thermal expansion coefficient of substrate and grown layer should be
similar.

In the case of a horizontal tool for liquid phase epitaxy the melt or the
melts are brought in contact with the substrate(s) by a sliding boat
system. When the dedicated process is finished the next melt can be
brought in contact with the next substrate. This way, it is possible to
grow multi-layer stacks in an easy way. Depending on the set-up of the
system one or several wafer can be processed at the same time. The
melt volume to substrate surface area ratio is small, and the melt needs
to be refreshed after each growth experiment.

A vertical system can be used in combination with a dipping system for

the liquid phase epitaxy growth. The samples are lowered into the melt
with the aid of a pull-rod. In this system the melt volume to substrate
surface area is much higher, giving the opportunity to grow thicker
layers at a relatively high rate.
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CVD Epitaxy (MOCVD)

• The CVD process is carried out a pressure around 0.5 –

760 torr and at temperatures hundreds of degrees lower
than the substrate melt temperature.
• The precursors are metalorganic. The reactions can
produce high quality epitaxial layers of III-V
semiconductors with very good thickness control allowing
quantum well structures to be manufactured.

• Examples:

– TMGa + AsH 3 at 650

– 750 °C for GaAs.
– TMGa + NH 3 at 800 °C for GaN.
– TEIn + PH 3 at 725 °C for InP.

Molecular Beam Epitaxy (MBE)

• The environment is highly controlled (P ~ 10-10 torr).

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• One or more evaporated beams of atoms react with the

substrate to yield a film.
• For epitaxial growth the surface diffusion-incorporation
time has to be less than one layer’s deposition time. This
limits the technique to being a low temperature one.
• Semiconductor and dopant sources are arrayed around
the substrate. Each source and the substrate can be
individually heated. Shutters control exposure to each
species.
• The sources can be solid source (for arsenide compounds)
or gas source (for phosphorus compounds).

MBE vs. MOCVD

• Both techniques can produce highly epitaxial films with

excellent abruptness, allowing thin layers to be formed.
• The UHV of MBE allows for better in situ diagnostic
techniques to be employed.

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• Substrate temperatures are lower in MBE.

• MBE is relatively safer.
• MOCVD has a higher growth rate and less downtime.
• It also has no issues regarding phosphor deposition.

Methods

Epitaxial silicon is usually grown using vapor-phase epitaxy (VPE), a

modification of chemical vapor deposition. Molecular-beam and liquid-
phase epitaxy (MBE and LPE) are also used, mainly for compound
semiconductors. Solid-phase epitaxy is used primarily for crystal-
damage healing.

Vapor-phase

Silicon is most commonly deposited by doping with silicon

tetrachloride and hydrogen at approximately 1200 to 1250 °C:

SiCl4(g) + 2H2(g) ↔ Si(s) + 4HCl(g)

This reaction is reversible, and the growth rate depends strongly upon
the proportion of the two source gases. Growth rates above 2
micrometres per minute produce polycrystalline silicon, and negative
growth rates (etching) may occur if too much hydrogen
chloride byproduct is present. (In fact, hydrogen chloride may be added
intentionally to etch the wafer.) An additional etching reaction
competes with the deposition reaction:

SiCl4(g) + Si(s) ↔ 2SiCl2(g)

Silicon VPE may also use silane, dichlorosilane,

and trichlorosilane source gases. For instance, the silane reaction
occurs at 650 °C in this way:
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SiH4 → Si + 2H2

This reaction does not inadvertently etch the wafer, and takes place at
lower temperatures than deposition from silicon tetrachloride.
However, it will form a polycrystalline film unless tightly controlled, and
it allows oxidizing species that leak into the reactor to contaminate the
epitaxial layer with unwanted compounds such as silicon dioxide.

VPE is sometimes classified by the chemistry of the source gases, such

as hydride VPE and metalorganic VPE.

Liquid-phase

Liquid-phase epitaxy (LPE) is a method to grow semiconductor crystal

layers from the melt on solid substrates. This happens at temperatures
well below the melting point of the deposited semiconductor. The
semiconductor is dissolved in the melt of another material. At
conditions that are close to the equilibrium between dissolution and
deposition, the deposition of the semiconductor crystal on the
substrate is relatively fast and uniform. The most used substrate is
indium phosphide (InP). Other substrates like glass or ceramic can be
applied for special applications. To facilitate nucleation, and to avoid
tension in the grown layer the thermal expansion coefficient of
substrate and grown layer should be similar.

Centrifugal liquid-phase epitaxy is used commercially to make thin

layers of silicon, germanium, and gallium arsenide. Centrifugally formed
film growth is a process used to form thin layers of materials by using
a centrifuge. The process has been used to create silicon for thin-film
solar cells and far-infrared photodetectors. Temperature and centrifuge
spin rate are used to control layer growth. Centrifugal LPE has the

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capability to create dopant concentration gradients while the solution

is held at constant temperature.

Solid-phase

Solid-phase epitaxy (SPE) is a transition between the amorphous and

crystalline phases of a material. It is usually done by first depositing a
film of amorphous material on a crystalline substrate. The substrate is
then heated to crystallize the film. The single crystal substrate serves as
a template for crystal growth. The annealing step used to recrystallize
or heal silicon layers amorphized during ion implantation is also
considered one type of Solid Phase Epitaxy. The Impurity segregation
and redistribution at the growing crystal-amorphous layer interface
during this process is used to incorporate low-solubility dopants in
metals and Silicon.

Epitaxial Deposition

Epitaxy is referred to as an arrangement of atoms in a crystal form

upon a crystal substrate, so that the resulting added layer structure is
an exact extension of the substrate crystal structure. In other words,
deposited atoms arrange themselves along existing planes of the
crystalline substrate material. This will cause the deposited atoms to
bond to the parent atoms to form an unbroken chain of the crystal
structure. The structure of the grown epitaxial layer is thus a
continuation of that single-crystal substrate.

Epitaxy and Crystal Growing

There is no difference between epitaxy and crystal growing technique.

But where, in epitaxy a thin film of single crystal silicon is grown from a
vapor phase upon a existing single crystal of the same material, in
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crystal growing, a single crystal is grown from the liquid phase, in

contrast to the growth technique in epitaxy. Furthermore, epitaxial
process involves no portion of the system at a temperature anywhere
near the melting point of the material.

Uses of Epitaxy

Epitaxy was first developed so as to improve the performance of

discrete bipolar transistors. The breakdown voltage of the collector
was determined by fabricating the devices in bulk wafers using the
wafer’s resistivity to determine the breakdown voltage of the collector.
However, high breakdown voltages need high-resistivity material. This
requirement, coupled with the thickness of the wafer, results in
excessive collector resistance that limits high-frequency response and
increases power dissipation. Epitaxial growth of a high resistivity layer
on a low-resistivity substrate solves this problem.

Epitaxy is also used to improve the performance of dynamic random-

access memory devices and CMOS ICs.

Epitaxial wafers have two basic advantages over bulk wafers:

 Epitaxial layers make it possible to control the doping profile in

a device structure that available with diffusion or ion
implantation.
 The physical properties of lire epi-layer differ from those of
bulk material. For example, epi -layers are generally oxygen
and carbon free, a situation not obtained with the crystal
grown silicon.

The most common example of epitaxy is the deposition of silicon

epitaxial layer on a single-crystal silicon substrate. In this case the
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substrate and layer materials are the same, and this is called
homoepitaxy. Here the epi-layer becomes a crystallographic
continuation of the substrate.

The CVD of single-crystal silicon is usually performed in a reader

consisting of a quartz reaction chamber into which a susceptor is
placed. The susceptor provides physical support for the substrate
wafers and provides a more uniform thermal environment. Deposition
occurs at a high temperature at which several chemical reactions take
place when process gases flow into the chamber.

Epitaxial Growth of Silicon

There are a number of different chemical reactions that can be used for
the deposition of epitaxial layers. Four silicon sources have been used
for growing epitaxial silicon. These are silicon tetrachloride [SiCl4],
dichlorosilane [SiH2Cl2], trichlorosilane [SiHCl3] and silane [SiH4].

Silicon tetrachloride has been the most studied and has seen the widest
industrial use. The overall reaction can be classed as a hydrogen
reduction of a gas.

SiCl4 [gas] + 2H2 [gas] = Si [solid] + 4HCl [gas]

For understanding the above reaction, we should determine for the Si –

CI – H system the equilibrium constant for each possible reaction and
the partial pressure of each gaseous species at the temperature of
interest. Equilibrium calculations reveal fourteen species to be in
equilibrium with solid silicon. In practice many of the species can be
ignored because their partial pressures are less than 10-6 atm.

Doping and Autodoping

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The considerations applied to epitaxial growth process are also

applicable to doping. Typical hydrides of the impurity atoms are used as
the source of dopant. Typical reaction for arsenic dopant is as below

 2AsH3(gas) = 2As[solid] + 3H2 [gas] = 2As (solid) = 2As+ [solid] + 2e

The hydride AsH3 does not decompose spontaneously as it is relatively

stable because of the large volume of hydrogen present in the reaction.
Interactions also take place between the doping process and the
growth process. In addition to intentional dopants incorporated into
the layer, unintentional dopants are introduced from the substrate.
This effect is termed autodoping. Autodoping limits the minimum layer
thickness that can be grown with controlled doping as well as the
minimum doping level.

Epitaxial Reactors

The epitaxial layer deposition takes place in a chamber called an

epitaxial reactor. There are three basic types of reactors.

 Horizontal Reactor
 Vertical Reactor and
 Cylindrical Reactor

The three reactors have been explained in the figure below.

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Epitaxial Reactors

Horizontal reactors offer lowest cost construction, however, controlling

the deposition process over the entire susceptor length is a problem.
Vertical reactors are capable of very uniform deposition but suffer from
mechanical complexity. Cylindrical reactors are also capable of uniform
deposition due to employment of radiant heating, but arc not suited for
extended operation at temperature above 1200°C.

Epitaxial Growth Process

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A typical epitaxial growth process includes several steps as follows.

 A hydrogen carrier gas is used to purge the reactor of air.

 The reactor is then heated to a temperature.
 After thermal equilibrium is established in the chamber,
anhydrous HCl gas is fed into the reactor. The HCl gas reacts
with the silicon at the surface of wafers in reaction that is
reverse of that given for [SiCl4+H2].This reverse reaction results
in vapor-phase-etching of the silicon surface and usually occurs
at a temperature between 1150 and 1200°C for 3 min.
 The temperature is then reduced to the growth temperature
with time allowed for stabilizing the temperature and flushing
the HCI gas. For [SiCI2 +H2] reaction, the graphite boat is heated
to a temperature in the range 1150 – 1250 degree Celsius. The
vapor of SiCl4 and hydrogen as a carrier gas arc introduced into
the lube for producing epitaxial layer.
 Once growth is complete, the dopant and silicon flows are
eliminated and the temperature reduced, usually by shutting of
the power.
 As the reactor cools toward ambient temperature, the
hydrogen flow is replaced by a nitrogen flow so that the
reactor may be opened safely.

Depending on wafer diameter and reactor type, capacities range from

10 to 15 wafer per batch. Process cycle times are about 1 hour. The
vapor-phase etching (VPE) described above is necessary to remove a
small amount of Si and other contaminants from the wafer surfaces to
ensure that a clear freshly etched silicon surface will be available for
epitaxial layer deposition. When the concentration of SiCI4, is high,

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etching can still occur even when hydrogen chloride is not present due
to a competing interaction.

SiC4 + Si = 2SiCl2

Thus, the growth rate of epitaxial silicon, which will be negative if

etching occurs. It is critically dependent on the concentration of silicon
chloride as well as the temperature. In typical environmental conditions
for growth, at a rate of around 1 micro meter per min, produces layers
which are well within the region for single-crystal epitaxy

When reduction of SiC4 lakes place, the reaction gives rise to free
silicon atoms. Atoms from the gas phase skid about on the surface of
the growing epitaxial film until they find correct position in the lattice
before becoming fastened into the growing structure.

For producing doped p-type or n-type epitaxial layers, a number of

gases can be metered into the reactor tube, including some very small
amounts of doping gases, such as B2H6 [diborane] for boron doping
and PH3 [phosphine] for phosphorus doping of the epitaxial layer.
During the epitaxial layer deposition the dopant gas molecules react
and become decomposed and the dopant atoms thus produced
become incorporated into the epitaxial layer. Doping of the epitaxial
layer is also achieved by adding controlled amounts of-the appropriate
impurity in liquid form, for example, phosphorus trichloride or arsenic
trichloride, to the silicon chloride.

The main advantages and disadvantages of SiCl4 as a source of Si

epitaxy are as follows:

Advantages

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 SiCl4 is non-toxic, inexpensive and easy to purify.

 The reaction making silicon from SiCl4 takes place only at
surface and not on the boat or reaction chamber walls.

Disadvantages

 The growth process is accompanied by the diffusion

phenomenon which causes an exchange of impurities between
silicon wafer and growing Film. This prevents the fabrication of
an ideal step junction.
 SiCl4 process requires higher temperature than silane process
and also has slower growth rate.

Problems in Growing Impurity Doped Epitaxial Layers

Epitaxial layer deposition takes place at temperatures in the range 950

to 1250°C. Due to this, diffusion of impurities may occur across the
epitaxial layer or substrate interface due to the deposition and high
temperature processing steps. This will cause a blurring of the impurity
profile in the region of this interface. But the main problem will be the
deposition of a very thin and very lightly doped epitaxial layer on a very
heavily doped substrate. The outdiffusion of impurities from the heavily
doped substrate into the lightly doped epitaxial layer will blot out the
sharp n/n+ transition that would otherwise be present at the layer-
substrate interface. The influx of donor atoms from the substrate will
reduce the effective thickness of the lightly doped epitaxial layer by 1
or 2 micro meter. To minimize this problem of outdiffusion from
heavily doped n+ substrate, slow donor diffusants such as antimony and
arsenic are often used for the doping of substrate in preference to
phosphorus.

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Molecular Beam Epitaxy (MBE)

Molecular beam epitaxy differs from vapor-phase epitaxy (VPE) in that

it employs evaporation [instead of deposition] method. Thus it is a non-
CVD epitaxial process. Although the method has been known since the
early 1960s, it has recently been considered a suitable technology for
silicon device fabrication. In the MBE process the silicon along with
dopants is evaporated. The evaporated species are transported at a
relatively high velocity in a vacuum to the substrate.

The relatively low vapor pressure of silicon and the dopants ensures
condensation on a low-temperature substrate. Usually, silicon MBE is
performed under ultra-high vacuum [UHV] conditions of 10-8 to l0-
16
Torr.

The two major reasons why MBE was not used were in earlier years
were that the quality was not commensurate with device needs and
that no industrial equipment existed. Equipments are now available,
but the process has low throughput and is expensive. MBE, however,
does have a number of inherent advantages over CVD techniques:

 It is a low temperature process. Thus outdiffusion and

autodoping is minimized.
 It allows precise control of doping and permits complicated
doping profiles in he generated, This is useful for discrete
microwave devices.
 A linear voltage -capacitance relationship is desired for varactor
diodes used in FM modulators. For this linear doping profile is
required, which is easily obtained with MBE.

Silicon Heteroepitaxy

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 While Si is not the ideal material from an electronic and optical

point of view, its abundance, ease of processing and availability of
a good native oxide have made it the backbone of semiconductor
industry.
 Combining Si substrates with compound semiconductor films
would enable higher optoelectronic functionality and higher
speeds.
 However, there are severe lattice mismatch and chemical
compatibility issues between Si and most III-V alloys that preclude
direct growth.
 Wafer Bonding
– The III-V epi-layer is grown on a lattice matched substrate
and bonded to a Si wafer by heat and pressure. The lattice
matched substrate is then removed by etching leaving the
Si/III-V structure behind.

Oxidation

Oxidation is the process by which a layer of silicon dioxide is grown on

the surface of a silicon wafer. Oxidation of silicon is achieved by heating
silicon wafers in an oxidizing atmosphere such as oxygen or water
vapor. Silicon has a very high band gap energy of 1.1eV , hence it is
used at high temperature.

Oxidation in IC Fabrication is very important process. In one line,

oxidation can be explained as the production of Si02 using the thermal
growth technique. Some of the important uses of Si02 are as follows.

 In bipolar and MOS transistors, it isolates one device from

other.

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 It provides surface passivation.

 It acts as a barrier or mask against the diffusion or the
implantation of impurity dopant in substrate.
 In MOS devices, it acts as a component.
 It serves as a dielectric isolation between multilevel inter
connect layers. There are different techniques of forming Si02
 Thermal oxidation

This is the basic process used in IC fabrication. When the charge density
level at the interface of silicon and oxide is required low, this technique
is used.

 Wet anodization
 Vapour phase oxidation

This process is also known as chemical vapour deposition. In multilevel

structures, the Si02 layer is formed on the top of the metal layer using
vapour phase oxidation process.

 Plasma oxidation

Oxidation Techniques

The selection of Oxidation in IC Fabrication technique to be used

depends on oxide properties and the thickness of the oxide layer
required. For thin oxides which require low charge at interface, the
oxides are grown in a dry oxygen. Wet and dry oxidation process is
preferred when sodium ion contamination is concerned. For thick
oxides, steam is used at high pressure with relatively moderate
temperatures. Let us study the most common process used in IC

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fabrication, Wet and dry thermal oxidation. The chemical reaction

involved in this technique are

 If thickness > 1mm --> field oxide layer

 If thickness < 1mm --> thin oxide layer

Equation (1) indicates reaction of silicon with oxygen, which is a dry

oxidation. Equation (2) indicates reaction of silicon with water vapour
or steam, which is wet oxidation. Using thermal oxidation, the oxygen
diffuses through the oxide to the boundary of Si-Si02. The reaction
takes place at the boundary of Si – Si02. After the completion of the
oxide growth, almost 46% of the oxide layer piereces within the original
substrate, while 54% of the remaining layer remains on the top of it as
shown in the Fig. 1.4.

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The silicon wafers are arranged in a quartz boat. Then the boat with
support is inserted into quartz furnace. The temperature of the furnace
lies in the range of 950CC to 1250`C and using proper control system,
the temperature is kept constant to about ± 19C. Then silicon wafers
are exposed to gas containing 02 and or H2 0. Following the chemical
reactions stated earlier. An uniform depth and composition layer
depends on the parameters such as growth time, teMperature,
pressure, 02 gas concentration etc.

Basically an Oxidation in IC Fabrication is high temperature process.

Due to the oxidation process, the layer departs from its original
location. To overcome this undesired result, the oxidation process is
carried out at low temperatures. But this increases the growth time. To
overcome this, pressure is increased because an increase by 1 atm
pressure decrease temperature by 209C for same growth rate. Thus
high pressure oxidations with pressures upto 25 atm are used in the
industrial applications at the temperatures in the range of 700 to 900°C.

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Initially the oxide grow formation rate is very fast and then gradually it
slows down as oxygen atoms have to diffuse through the oxide to reach
the interface between silicon substrate and Si02. As compared to dry
oxidation process, wet oxidation process is faster at a given
temperature. Typically to grow 1 Rin thick oxide layer, dry oxidation
process takes 2 hour 30 minutes while wet oxidation takes only 1 hour
and 30 minutes. Eventhough the wet oxidation process is time saving, it
has a drawback of higher impurity contents of the oxides. Generally
MOS ICs require a very pure oxide for reliable performance. For this
purpose specially dry oxidation process is preferred.

For VLSI, the thin oxides of 20 to 200 A° are in demand. The growth rate
for such thin oxide layers are very small. With low temperatures and
pressures growth rate reduces. For such very thin oxide layers special
techniques are applied. The oxide layers of 30 to 300 A° thick are grown
at pressures of 0.2 to 2 Torr. In other technique, for a very thin oxide
layer initially temperature is controlled at 1000CC typically, the growth
is carried out with 02 – HC1 agent and then heat treatment with N2,02
and HC1 is employed at 1250CC to work out desired thickness. By using
low temperatures (750`C) and high pressures (10 atm) in combination,
a 300A° thick layer can be grown in 30 minutes with this another special
technique.

Oxide Properties

For reliable performances of the devices, it is necessary to have a very

pure oxide. To carry out the oxidation process successfully, it is
necessary to study different properties of oxides.

1) Masking properties of SiO2

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A silicon dioxide acts as a barrier or mask against the diffusion of

dopant atoms. Due to ion implantation and chemical diffusion, the
dopant atoms gather at the surface of the oxide or near the surface. So
the utmost precaution must be taken during the diffusion of axide, such
that the dopant atoms do not diffuse through the oxide. This can be
achieved by controlling the diffusion in oxide slower as compared to
that in silicon. At a particular temperature and pressure, the oxide
thickness can be measured experimentally which is essential to avoid
the inversion of the lightly doped silicon substrate. In typical devices,
the oxide thickness required for the masking purpose is 0.5 to 0.7 um.
The masking property can be realized only when the oxide is partially
converted into the silica. For different dopant atoms, the diffusion
constants in silicon dioxide are different. These are dependent on the
structure and concentration of Si02. For n-type, the common impurities
are phosphorous (P), Antimony (Si), Arsenic (As), while for p-type
Borone (B) is the common impurity.

2) Oxide Charges

The thermally oxidized silicon consists different types of charges. There

exists a transition region at the silicon silicondioxide interface. At this
interface some of the charges are found. These charges induce opposite
polarity in the silicon substrate, changing the characteristics of MOS
devices. At interface, the silicon dioxide layer departs from the ideal
charge neutrality expected. There are three types of the charges
namely :

 Fixed oxide charge (Q f)

 Mobile ionic charge (Qm)
 Oxide trapped charge (Q„t)

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The fixed oxide charge Q f is usually positive. This cannot be charged or

discharged. It is not allowed beyond 30A° of Si — Si02 interface.
Depending upon oxidation and annealing conditions, its density ranges
from 1010 cm-2 to 1012 cm-2.

The mobile ionic charge Qm is positive most of the times. The alkali ions
such as sodium, potassium are referred as mobile ion charge. But the
negative ions and heavy metals are also referred as ionic charges. The
density of Qm ranges from 1010 cm-2 to 1012 cm-2. The radi of ionic
charges are more and also their mobility is very low.

The oxide trapped charge Q ot is either positive or negative. It arises

from either holes or electrons trapped in the oxide. The main cause of
Qot is the defects in the oxides. Also due to avalanche injection, ionizing
radiations and high currents in the oxides, Qot may be induced.
The density of Q ot ranges from 109 cm-2 to 1013 cm-2. In addition to
these charges, there is an interface trapped charge Q it.

All these tcharges are calculated using capacitance voltage (C–V)

analysis technique.

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3) Oxide stress

During the thermal oxidation of silicon, at the surface, Si02 is observed

in a state of compression. This is clearly indicated by thermally wrapped
silicon dioxide. The complex stress distribution takes place due to the
cut in the oxides. Thus there is a danger of high stress levels formation
at the discontinuities.

The stress can be relieved by using stress-relief mechanisms. Typically

oxidation at 9509C or below, the stress is of the order of 7 x 109
dyne/cm2. At room temperature, the stress is found to be 3 x 109
dyne/km2.

1) Oxidation Induced Defects

Oxidation Induced Stacking Faults: Stacking faults are produced on

<111> planes due to thermal oxidation of silicon. The stacking faults are
structural defects in the silicon lattice which are of extrinsic type and
are limited by partial dislocations. There is coalescence of excess silicon
atoms in the silicon lattice on nucleation site. This is called as growth
mechanism. The growth mechanism involves defects formed during
growth of a crystal, surface mechanical damage present before
oxidation, chemical contamination and saucer pits or hillocks. Due to
process of Oxidation in IC Fabrication the excess interstitial silicon is
present near the Si – SiO2 interface. A small part of these silicon atoms
flow into the bulk silicon. Growth rate depends upon the silicon
interstitial supersaturation in silicon. Stacking faults create some
problems like degraded junction characteristics and increased reverse
current in MOS structures.

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The growth of oxidation induced stacking faults is a function of

orientation of substrate, conductivity type and the defect nuclei
present. Growth rate is greater in <100> than in <111> substrates.

The length, of stacking fault is a function of oxidation temperature. For

lower oxidation temperature, less stacking faults are grown. For
oxidation temperature less than 9509C, the stacking faults formation is
suppressed completely.

Formation of the stacking fault length depends on rate of oxidation

which is given by

2) Oxide Isolation Defects :

Silicon is treched before oxidation, to produce planar surface. It

produces recessed oxides. In such recessed oxides stress along the edge
of an oxidizing area causes defects in silicon. These defects cause

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increased leakage in nearby devices. Growing oxides generate the

stress. This stress should be relieved without damaging the silicon.
Sufficiently high oxidation temperature relieves the stress in oxides by
viscous flow to make the oxide isolation to defects lesser. It can also be
achieved by growing a selective oxide without first trenching the silicon.
It is also seen that there is less oxidation in the stressed region which is
covered by nitride mask.

Oxidation Process in IC Fabrication

The function of a layer of silicon dioxide (SiO2) on a chip is

multipurpose. SiO2 plays an important role in IC technology because no
other semiconductor material has a native oxide which is able to
achieve all the properties of SiO2. The role of SiO2 in IC fabrication is as
below :

It acts as a diffusion mask permitting selective diffusions into silicon

wafer through the window etched into oxide.

 It is used for surface passivation which is nothing but creating

protective SiO2 layer on the wafer surface. It protects the
junction from moisture and other atmospheric contaminants.
 It serves as an insulator on the water surface. Its high relative
dielectric constant, which enables metal line to pass over the
active silicon regions.
 SiO2 acts as the active gate electrode in MOS device structure.
 It is used to isolate one device from another.
 It provides electrical isolation of multilevel metallization used
in VLSI.

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It is fortunate that silicon has an easily formed protective oxide, for

otherwise we should have to depend upon deposited insulators for
surface protection. Since SiO2 produces a stable layer, this has held
back germanium IC technology.

Growth and Properties of Oxide Layers on Silicon

Silicon dioxide (silica) layer is formed on the surface of a silicon wafer

by thermal oxidation at high temperatures in a stream of oxygen.

Si+02 = SiO2 (solid)

The oxidation furnace used for this reaction is similar to the diffusion
furnace. The thickness of the oxide layer depends on the temperature
of the furnace, the length of time that the wafers are in it, and the flow
rate of oxygen. The rate of oxidation can be significantly increased by
adding water vapour to the oxygen supply to the oxidizing furnace.

Si + 2H2O = SiO2 + 2H2

The time and temperature required to produce a particular layer

thickness arc obtained from empirically determined design curves, of
the type shown in the figures given below corresponding to dry-
oxygen atmosphere and also corresponding to steam atmosphere.

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Growth and Properties of Oxide Layers on Silicon

In the past, steam was obtained by boiling ultra-high-purity water and

passing it into the high-temperature furnace containing the silicon
wafers; however, present day technologies generally use hydrogen and
oxygen which are ignited in the furnace tube to form the ultra high-
purify water vapour.

The process of silicon oxidation takes place many times during the
fabrication of an IC. Once silicon has been oxidized the further growth
of oxide is controlled by the thickness of the initial or existing oxide
layer.

Growth Rate of Silicon Oxide Layer

The initial growth of the oxide is limited by the rate at which the
chemical reaction takes place. After the first 100 to 300 A of oxide has
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been produced, the growth rate of the oxide layer will be limited
principally by the rate of diffusion of the oxidant (02 or H20) through the
oxide layer, as shown in the figures given below.

The rate of diffusion of O2 or H2O through the oxide layer will be

inversely proportional to the thickness of the layer, so that we will have
that

dx/dt = C/x

where x is the oxide thickness and C is a constant of proportionality.

Rearranging this equation gives

xdx = Cdt

Integrating this equation both sides yields, x2/2 = Ct

Solving for the oxide thickness x gives, x = √2Ct

We see that after an initial reaction-rate limited linear growth phase

the oxide growth will become diffusion-rate limited with the oxide
thickness increasing as the square root of the growth time. This is also
shown in the figure below.

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The rate of oxide growth using H2O as the oxidant will be about four
times faster than the rate obtained with O2. This is due to the fact that
the H2O molecule is about one-half the size of the O2 molecule, so that
the rate of diffusion of H2O through the SiO2 layer will be much greater
than the O2 diffusion rate.

Oxide Charges

The interlace between silicon and silicon dioxide contains a transition

region. Various charges are associated with the oxidised silicon, some
of which are related to the transition region. A charge at the interface
can induce a charge of the opposite polarity in the underlying silicon,
thereby affecting the ideal characteristics of the MOS device. This
results in both yield and reliability problems. The figure below shows
general types of charges.

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Oxide Charges

 Interface-trapped charges

These charges at Si-SiO2 are thought to result from several sources

including structural defects related to the oxidation process, metallic
impurities, or bond breaking processes. The density of these charges is
usually expressed in terms of unit area and energy in the silicon band
gap.

 Fixed oxide charge

This charge (usually positive) is located in the oxide within

approximately 30 A of the Si –SiO2 interface. Fixed oxide charge cannot
be charged or discharged. From a processing point of view, fixed oxide
charge is determined by both temperature and ambient conditions.

 Mobile ionic charge

This is attributed to alkali ions such as sodium, potassium, and lithium

in the oxides as well as to negative ions and heavy metals. The alkali

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ions are mobile even at room temperature when electric fields are
present.

 Oxide trapped charge

This charge may be positive or negative, due to holes or electrons

trapped in the bulk of the oxide. This charge, associated with defects in
the Si02, may result from ionizing radiation, avalanche injection.

Effect of Impurities on the Oxidation Rate

The following impurities affect the oxidation rate

1) Water
2) Sodium
3) Group III and V elements
4) Halogen

In addition damage to the silicon also affects oxidation rate. As wet

oxidation occurs at a substantially greater rate than dry oxygen, any
unintentional moisture accelerates the dry oxidation. High
concentrations of sodium influence the oxidation rate by changing the
bond structure in the oxide, thereby enhancing the diffusion and
concentration of the oxygen molecules in the oxide.

During thermal oxidation process, an interface is formed, which

separates the silicon from silicon dioxide. As oxidation proceeds, this
interface advances into the silicon. A doping impurity, which is initially
present in the silicon, will redistribute at the interface until its chemical
potential is the same on each side of the interface. This redistribution
may result in an abrupt change in impurity concentration across the
interface. The ratio of the equilibrium concentration of the impurity,

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that is, dopant in silicon to that in SiO2 at the interface is called the
equilibrium segregation coefficient. The redistribution of the dopants at
the interface influences the oxidation behaviour. If the dopant
segregates into the oxide and remains there (such as Boron, in an
oxidizing ambient), the bond structure in the silica weakens. This
weakened structure permits an increased incorporation and diffusivity
of the oxidizing species through the oxide thus enhancing the oxidation
rate. Impurities that segregate into the oxide but then diffuse rapidly
through it (such as aluminium, gallium, and indium) have no effect on
the oxidation kinetics. Phosphorus impurity shows opposite effect to
that of boron, that is, impurity segregation occurs in silicon rather than
Si02. The same is true for As and Sb dopants.

Halogen (such as chlorine) impurities are intentionally introduced into

the oxidation ambient to improve both the oxide and the underlying
silicon properties. Oxide improvement occurs because there is a
reduction in sodium ion contamination, increase in oxide breakdown
strength, and a reduction in interface trap density. Traps arc energy
levels in the forbidden energy gap which are associated with defects in
the silicon.

Growth and Properties of Thin Oxides

MOS VLSI technology requires silicon dioxide thickness in the 50 to 500

A range in a repeatable manner. This section is devoted to the growth
and properties of such thin oxide. This oxide must exhibit good
electrical properties and provide long-term reliability. As an example,
the dielectric material for MOS devices can be thin thermal oxide. This
dielectric is an active component of the storage capacitor in dynamic

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RAMs, and its thickness determines the amount of charge that can be
stored.

The growth of thin oxide must be slow enough to obtain uniformity and
reproducibility. Various growth techniques for thin oxide are dry
oxidation, dry oxidation with HCl, sequential oxidations using different
temperatures and ambients, wet oxidation, reduced pressure
techniques, and high pressure/low temperature oxidation. High
pressure oxidation is discussed later. The oxidation rate will, of course,
be lower at lower temperatures and at reduced pressures. Ultra-thin
oxide (<50 A) have been produced using hot nitric acid, boiling water,
and air at room temperatures. Some recent developments in thin oxide
growth technique are

(i) Rapid thermal oxidation performed in a controlled oxygen

ambient with heating provided by tungsten-halogen
lamps and
(ii) Ultraviolet pulsed laser excitation in an oxygen
environment.

The properties of thin oxide depend upon the growth technique

employed. For example, oxide density increases as the oxidation
temperature is reduced. Additionally, HCl ambients have typically been
used to passivate ionic sodium, improve the breakdown voltage, and
getter impurities and defects in the silicon. This passivation effect
begins to occur only in the higher temperature range.

For thin oxides, there is an increase in leakage for a given voltage. In

thin oxides the dielectric breakdown may be field-dependent
(breakdown in a ramping field) or time-dependent (breakdown at a

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constant field). This breakdown is a failure mode for MOS ICs. Thinner
oxides are more prone to failure.

High Pressure Oxidation

There is a benefit of increase in the oxidation rate if the thermal

oxidation is carried out at pressures that are much above atmospheric
pressure. The rate of diffusion of the oxidant molecules through an
oxide layer is proportional to the ambient pressure. For example, at a
pressure of 10 atm the diffusion rate will be increased by a factor of 10
and the corresponding oxidation time can be reduced by nearly the
same factor. Alternatively, the oxidation can be done for the same
length of time, but the temperature required will be substantially
lower.

Thus, one principal benefit of high-pressure oxidation processing is

lower-temperature processing. The lower processing temperature
reduces the formation of crystalline defects and produces less effect on
previous diffusions and other processes. The shorter oxidation time is
also advantageous in increasing the system throughput. The major
limitation of this process is the high initial cost of the system.

Oxide Masking

The oxide layer is used to mask an underlying silicon surface against a

diffusion (or ion implantation) process. The oxide layer is patterned by
the phtolithographic process to produce regions where there are
opening or “windows” where the oxide has been removal to expose
the underlying silicon. Then these exposed silicon regions are subjected
to the diffusion (or implantation) of dopants, whereas the unexposed
silicon regions will be protected. The pattern of dopant that will be

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deposited into the silicon will thus be a replication of the pattern of

opening in the oxide layer. The replication is a key factor in the
production of tiny electronic components.

The thickness of oxide needed for diffusion masking is a function of the

type of diffusant and the diffusion time and temperature conditions. In
particular, an oxide thickness of some 5000 A will he vufftcieni to mask
against almost all diffusions. This oxide thickness will also be sufficient
to block almost alt but the highest-energy ion implantation.

Oxide Passivation

The other function of Si02 in IC fabrication is the surface passivation.

This is nothing but creating protective Si02 layer on the wafer surface.
The figure below shows a cross-sectional view of a p-n junction
produced by diffusion through an oxide window. There are lateral
diffusion effects, that is, the diffusion not only proceeds in the
downward direction, but also sideways as well, since diffusion is an
isotropic process. The distance from the edge of the oxide window to
the junction in the lateral direction underneath die oxide is indicated as
yj.

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Diffusion Masking

Lithography/Photolithography

When a sample of crystalline silicon is covered with silicon dioxide, the

oxide-layer acts as a barrier to the diffusion of impurities, so that
impurities separated from the surface of the silicon by a layer of oxide
do not diffuse into the silicon during high-temperature processing. A p-
n junction can thus be formed in a selected location on the sample by
first covering the sample with a layer of oxide [oxidation step] removing
the oxide in the selected region, and then performing a predeposition
and diffusion step. The selective removal of the oxide in the desired
area is performed with photolithography. Thus, the areas over which
diffusions are effective are defined by the oxide layer with windows cut
in it, through which diffusion can take place. The windows are
produced by the photolithographic process. This process is the means
by which microscopically small electronic circuits and devices can be
produced on silicon wafers resulting in as many as 10000 transistors on
a 1 cm x 1 cm chip.

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In fact photolithography or optical lithography is a kind of lithography.

The lithography technique was first used in the late 18th century by
people interested in art. A lithograph is a less expensive picture made
from a flat, specially prepared stone or metal plate and the lithography
is art of making lithographs. Therefore, lithography for IC
manufacturing is analogous to the lithography of the art world. In this
process the exposing radiation, such as ultraviolet (UV) light in case of
photolithography, is transmitted through the clear parts of the mask.
The circuit pattern of opaque chromium blocks some of die radiation.
This type of chromium/glass mask is used with UV light. Other types of
exposing radiations are electrons, X-rays, or ions. Thus for IC
manufacturing we have following types of lithography.
Photolithography has been explained in this post.

In IC fabrication a number of masks are employed. Except for the first

mask, every mask must be aligned to the pattern produced by the
previous mask. This is done using mask aligner. The mask aligner may
be contact type or proximity type or projection type. Accordingly we
have three types of printing. They are

 Contact printing
 Proximity printing
 Projection printing

Photolithographic Process Steps

1. Photoresist Application (Spinning)

A drop of light-sensitive liquid called photoresist is applied to the centre

of the oxidized silicon wafer that is held down by a vacuum chuck. The
wafer is then accelerated rapidly to a rotational velocity in the range

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3000 to 7000 RPM for some 30 to 60 seconds. This action spreads the
solution in a thin, nearly uniform coat and spins off the excess liquid.
The thickness of the coat so obtained is in the range 5000 to 10000 A,
as shown in the figure below. The thickness of the photoresist layer will
be approximately inversely proportional to the square root of the
rotational velocity.

Sometimes prior to the application of the photoresist the silicon wafers

are given a “bake-out” at a temperature Of at least 100°C to drive off
moisture from the wafer surfaces so as to obtain better adhesion of the
photoresist. Typical photoresist used is Kodak Thin Film Resist (KTFR).

2. Prebake

The silicon wafers coated with photoresist are now put into an oven at
about 80°C for about 30 to 60 minutes to drive off solvents in the
photoresist and to harden it into a semisolid film.

3. Alignment and Exposure

The coated wafer, as above, is now placed in an apparatus called a

mask aligner in very close proximity (about 25 to 125 micro meters) to a
photomask. The relative positions of the wafer and the photomasks are
adjusted such that the photomask is correctly lined up with reference
marks or a pre-existing pattern on the wafer.

The photomask is a glass plate, typically about 125 mm square and

about 2 mm thick. The photomask has a photographic emulsion or thin
film metal (generally chromium) pattern on one side. The pattern has
clear and opaque areas. The alignment of the photomask to the wafer
is often required to be accurate to within less than 1 micro meter, and
in some cases to within 0.5 micro meters. After proper alignment has
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been achieved, the wafer is brought into direct contact with the
photomask. Photomask making will be described separately.

A highly collimated ultraviolet (UV) light is then turned on and the areas
of the silicon wafer that are not covered by the opaque areas of the
photomask are exposed to ultraviolet radiation, as shown in the figure.
The exposure time is generally in the range 3 to 10 seconds and is
carefully controlled such that the total UV radiation dosage in watt-
seconds or joules is of the required amount.

4. Development

Two types of photoresist exist- negative photoresist and positive

photoresist. In the present description negative photoresist is used in
which the areas of the photoresist that are exposed the ultraviolet
radiation become polymerized. The polymerization process increases
the length of the organic chain molecules that make up the photoresist.
This makes the resist tougher and makes it essentially insoluble in the
developer solution. The resisting photoresist pattern after the
development process will therefore be a replication of the photomask
pattern, with the clear areas on the photomask corresponding to the
areas where the photoresist remains on the wafers, as shown in the
figure below.

An opposite type of process occurs with positive photoresist. Exposure

to UV radiation results in depolymerization of the photoresist. This
makes these exposed areas of the photoresist readily soluble in the
developer solution, whereas the unexposed areas are essentially
insoluble. The developer solution will thus remove the exposed or
depolymerized regions of the photoresist, whereas the unexposed
areas will remain on the wafer. Thus again there is a replication of the
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photomask pattern, but this time the clear areas of the photomask
produce the areas on the wafer from which the photoresist has been
removed.

5. Postbake

After development and rinsing the wafers are usually given a postbake
in an oven at a temperature of about 150°C for about 30 to 60 minutes
to toughen further the remaining resist on the wafer. This is to make it
adhere better to the wafer and to make it more resistant to the
hydrofluoric acid [HF] solution used for etching of the silicon dioxide.

6. Oxide Etching

The remaining resist is hardened and acts as a convenient mask

through which the oxide layer can be etched away to expose areas of
semiconductor underneath. These exposed areas are ready for impurity
diffusion.

For etching of oxide, the wafers are immersed in or sprayed with a

hydrofluoric [HF] acid solution. This solution is usually a diluted solution
of typically 10: 1, H2O : HF, or more often a 10 : 1 NH4F [ammonium
fluoride]: HF solution. The HF solutions will etch the SiO2 but will not
attack the underlying silicon, nor will it attack the photoresist layer to
any appreciable extent. The wafers are exposed to the etching solution
ion enough to remove the SiO2 completely in the areas of the wafer
that are not covered by the photoresist as shown in the figure.

The duration of oxide etching should be carefully controlled so that all

of the oxide present only in the photoresist window is removed. If
etching time is excessively prolonged, it will result in more undercutting

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underneath the photoresist and widening of the oxide opening beyond

what is desired.

The above oxide etching process is termed wet etching process since
the chemical reagents used are in liquid form. A newer process for
oxide etching is a dry etching process called plasma etching. Another
dry etching process is ion milling.

7. Photoresist Stripping

Following oxide etching, the remaining resist is finally removed or

stripped off with a mixture of sulphuric acid and hydrogen peroxide and
with the help of abrasion process. Finally a step of washing and drying
completes the required window in the oxide layer. The figure below
shows the silicon wafer ready for next diffusion.

Photolithographic Process Steps

Negative photoresists, as above, are more difficult to remove. Positive

photoresists can usually be easily removed in organic solvents such as
acetone.

The photolithography may employ contact, proximity, or projection

printing. For IC production the line width limit of photolithography lies
near 0.4 micro meters, although 0.2 micro meters features may be

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printed under carefully controlled conditions. At present, the

photolithography occupies the primary position among various
lithographic techniques.

Photoresists

One of the major factors in providing increasingly complex devices has

been improvement in photolithographic art. A large part of this
improvement has been due to high quality photoresist, materials as
improved techniques of coating, baking, exposing and developing
photoresists.

The principal constituents of a photoresist solution are a polymer, a

sensitizer and a suitable solvent system Polymers have properties of
excellent film forming and coating. Polymers generally used are
polyvinyl cinnamate, partially cyclized isoprene family and other types
are phenol formaldehyde.

When photoresist is exposed to light, sensitizer absorbs energy and

initiates chemical changes in the resist. The sensitizers are
chromophoric organic molecules. They greatly enhance cross linking of
the photoresist. Cross linking of polymer or long chain formation of
considerable number of monomers makes high molecular weight
molecules on exposure to light radiation, termed as photo-
polymerization. Typical sensitizers are carbonyl compounds, Benzoin,
Benzoyl peroxide, Benzoyl disulphide, nitrogen compounds and halogen
compounds.

The solvents used to keep the polymers in solution are mixture of

organic liquids. They include aliphetic esters such as butyl acetate and
cellosolve acetate, aromatic hydrocarbons like xylene and

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Ethylbenzene, chlorinated hydrocarbons like chlorobenzene and

methylene chloride and ketones such as cyclohexanone. The same
solvents are used as thinners and developers.

Characteristics of Good Photoresist

To achieve faithful registration of the mask geometry over the

substrate surface, the resist should satisfy following conditions.

 Uniform film formation

 Good adhesion to the substrate
 Resolution
 Resistance to wet and dry etch processes

Types of Photoresist

Polymers film is either photosensitive or capable or reacting with the

pholysis product of additional compound so that the solubility increases
or decreases greatly by exposure to UV (ultra-violet) radiation.
According to the changes that take place, photoresists are termed
negative or positive. Materials which are rendered less soluble in a
developer solution by illumination^ yield a negative pattern of the
mask and are called negative photoresists. Conversely, positive
photoresists become more soluble when subjected to light and
therefore yield a positive image of the mask.

Negative Photoresist

Kodak negative photoresist contain polyvinyl cinnametes. KPR is being

used in printing circuit boards. KTFR is widely used in fabrication of ICs.
It provides good adhesion to silicon dioxide and metal surfaces. It gives
well etch results to different etchant solutions. For finer resolution,

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thinner coating of KTFR is used. To achieve controlled and uniform

thickness, the viscosity of resist is suitably lowered using thinners.

Another negative photoresist is Kodak Microneg 747 which provides

high scan speeds at high aperature giving high throughput and
resolution.

Positive Photoresist

Positive Photoresists have solved the problem of resolution and

substrate protection. Photo resists can be used at a coating thickness of
1 micro meter that eliminates holes and minimises defects from dust.

Positive photoresist is inherently of low solubility (polymerized)

material. The base polymer is active by itself. A sensitizer, when
absorbs light, makes the base resist soluble in an alkali developer.
Positive photoresists are Novolac resins. Typical solvents are cellosolve
acetate, butyl acetate, xylene and toluene.

Resist requirements for VLSI

For fine line geometries in VLSI circuits, the resist requirements become
more stringent. The resist properties should meet the required demand
of high resolution. Here the resist should exhibit

 High sensitivity for partial exposure tool chosen

 Dry developing, dry compatibility
 Vertical profile control

Photomask Fabrication

Photolithography is used to produce windows in the oxide layer of the

silicon wafer, through which diffusion can take place. For this purpose

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photomask is required. In this section we shall discuss various

techniques of mask fabrication. The pattern appearing on the mask is
required to be transferred to the wafer. For this purpose various
exposure techniques are employed. We will also discuss these
techniques.

Mask Making

IC fabrication is done by the batch processing, where many copies of

the same circuit are fabricated on a single wafer and many wafers are
fabricated at the same time. The number of wafers processed at one
time is called the lot size and many vary between 20 to 200 wafers.
Since each IC chip is square and the wafer is circular, the number of
chips per wafer is the number of complete squares of a given size that
can fit inside a circle.

The pattern for the mask is designed from the circuit layout. Many
years ago, bread boarding of the circuit was typical. In this, the circuit
was actually built and tested with discrete components before its
integration. At present, however, when LSI and VLSI circuits contain
from a thousand to several hundred thousand components, and
switching speeds are of such high order where propagation delay time
between devices is significant, bread boarding is obviously not
practical. Present-day mask layout is done with the help of computer.

The photographic mask determines the location of all windows in the

oxide layer, and hence areas over which a particular diffusion step is
effective. Each complete mask consists of a photographic plate on
which each window is represented by an opaque are, the remainder
being transparent. Each complete mask will not only include all the
windows for the production of one stage of a particular IC, but in
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addition, all similar areas for all such circuits on the entire silicon as
shown in the figure below.

It will be obvious that a different mask is required for each stage in the
production of an array of IC’s on a wafer. There is also a vital
requirement for precise registration between one mask and the other
in series, to ensure that there is no overlap between components, and
that each section of a particular transistor is formed in precisely the
correct location.

To make a mask for one of the production stages, a master is first

prepared which is an exact replica of that portion of the final mask
associated with one individual integrated circuit, but which is 250x [say]
enlargement of the final size of IC. The figure below shows a possible
master for the production of a mask to define a particular layer of
diffusion for a hypothetical circuit. Art work at enlarge size avoids large
tolerance errors. Large size also permits the art work to be dealt easily
by human operator. In the design of the art work, the locations of all
components that is, resistor, capacitor, diode, transistor and so on, are
determined on the surface of the chip. Therefore, six or more layout
drawings are required. Each drawing shows the position of Windows
that are required for a particular step of the fabrication. For complex
circuit the layout is generated by the use of computer-aided graphics.

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Photomask Fabrication

The master, typically of order 1 m x 1 m, is prepared from cut and strip

plastic material which consists of two plastic films, one
photographically opaque called Rubilith and the other transparent
[mylar], which are laminated together. The outline of the pattern
required is cut in the red coating of Rubilith (which is opaque) using a
machine controlled cutter on an illuminated drafting table. The opaque
film is then peeled off to reveal transparent areas, each representing a
window region in die final mask.

The next step is to photograph the master using back illumination, to

produce a 25 x reduced sub-master plate. This plate is used in a step
and repeat camera which serves the dual purpose of reducing the
pattern by a further 10 x to finished size and is also capable of being
stepped mechanically to produce an array of identical patterns on the
final master mask, each member of the many corresponding to one

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complete IC. Instead of the photographic plate being transported

mechanically in discrete steps, better accuracy may be achieved by
using continuous plate movement; discrete exposures then being made
by an electronically synchronized flash lamp which effectively freezes
the motion.

The entire sequence just described can be done with plates containing
a photosensitive emulsion; typically the emulsion is considered too
vulnerable to abrasion and tears. For this reason, masks are often made
of harder materials such as chrome or iron oxide.

For very complex circuits automated mask generation equipment is

used. In this, a computer controlled light flashes to build up the pattern
on a photographic film by a series of line or block exposures, the
resulting film is then reduced and handled in a step and repeat system
to create the production mask. Alternatively, the master mask can be
generated by an electron beam exposure system, again controlled by
computer.

Various Printing Techniques

Photolithography comprises the formation of images with visible or U V

radiation in a photoresist using contact proximity, or projection
printing. Here we will discuss about these printing techniques.

1. Contact Printing

In this printing technique, the photomask is pressed against the resist

coated wafer with a pressure typically in the range of 0.05 atm to 0.3
atm and exposure by light of wavelength near 400 micro meters. A
resolution of less than 1 micro meter linewidth is possible, but it may
vary across the wafer because of spatial non-uniformity of the contact.
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To provide better contact over the whole wafer, a thin (0.2 mm) flexible
mask has been used.

2. Proximity Printing

In proximity or shadow printing, there exists a gap between mask and

wafer in the range of 20 to 50 micro meters. This has the advantage of
longer mask life because there is no contact between the mask and the
wafer. In the proximity printing, the mask and wafer are both placed in
an equipment called a projection aligner. Looking through a
microscope, an operator brings the mask into close proximity [say 10 to
20 micro meters] to the wafer and properly aligns the wafer and mask
using alignment mark on the mask and the wafer. UV light is then
projected through the mask on to the entire resist coated wafer at one
time. This mask that is used is a full wafer x 1 mask. The resolution of
this process is a function of the wavelength of the light source and the
distance between the mask and the wafer. Typically, the resolution of
proximity printing is 2 to 4 micro meter and is therefore not suitable for
a process requiring less than a 2 um minimum line width.

3. Projection Printing

In this case the image is actually projected with the help of a system of
lenses, onto the wafer. The mask can be used a large number of times,
substantially reducing the mask cost per wafer. Theoretically a mask
can be used an unlimited-number of times, but actual usage is limited
to about 100,000 times because the mask must be cleaned due to dust
accumulation, and it is scratched at each cleaning. This is costliest of
the conventional systems, however mask life is good, and resolution
obtained is higher than proximity printing together with large
separation between mask and wafer.
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Automated Mask Generation

As discussed above, layouts of electronic circuit are drawn on large

mylar sheets. They can also be drawn on a CRT screen by which layouts
are stored digitally in a magnetic tape (or disk). In this case we need to
prepare many layouts since each layout represents a pattern on each
mask to be used during fabrication. Since the layouts are to be stored
digitally, it is required to convert the layouts drawn on mylar sheets
into digital data. This is performed by a digitizer with the aid of a
computer. Then different portions of each layout are displayed on a
CRT one by one and inspected for further mistakes. After all the
corrections have been made, a reticle, which is a small photographic
plate of the layout image, is prepared from each layout stored on the
magnetic tape.

Depending upon the type of equipment used, the mask to be fabricated

contains one IC chip pattern which is repeated as many times as there
are on the wafer. Alternatively, the mask consists of only magnified
chip pattern as shown in the figure below.

Automated Mask generation

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The two most common approaches to automated mask making or

generation are

 Using optical projection and

 Using electron beam

A pattern generator (PG) tape is used as the Input to both approaches.

The PG tape, contains the digitized data necessary to control the light
source or electron beam that is used to write a pattern on a
photosensitive glass plate. An Ax10 pattern for a single chip (called a
x10 reticle) is first produced. This reticle is then photo enlarged by a
factor of 15, yielding x 150 blowback, which is used for visual checking.
A x 1 mask of the type shown in the figure is then produced from the x
10 reticle by optical reduction and projection onto a second
photosensitive plate. The same pattern is stepped and repeated on this
plate as many as there are chips on the wafer. This step and repat
operation is performed by photo repeater. The glass plate is then
developed yielding a x 1 mask which is called a master mask and looks
like a tile floor where each rectangular tile has the same layout image
of the chp. During the step and repeat process the position and angle of
the reticle are precisely aligned with the help of two fiducial marks
incorporated in the PG files of all layouts in the same relative position
with respect to the entire chip. The master mask plate is then placed in
close proximity to the wafer and optically projected on to a resist-
coated wafer during the lithographic process.

The figure below shows the second approach. This employs electron-
beam mask generation equipment winch generates the mask plate in
one step. The layout data are converted into a hit map of 1’s and 0’s on
a raster image. The electron beam sweeps the row in a repeating S

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pattern, blanking or unblanking the beam according to the input bit

value, 0 or 1. In the figure, the x10 reticle is optically reduced and
stepped directly onto the wafer. This is referred to as direct-step on
wafer (DSW) lithography.

Automated Mask Generation Process

The main advantage of electron-beam pattern generator is speed in the

case of complex chips. A large, dense chip can require 20 hours or more
of optical pattern generator time, but only two hours or less of
electron-beam pattern generator time.

Lithography Process

Optical lithography is a photographic process by which a light-sensitive

polymer, called a photoresist, is exposed and developed to form 3D

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relief images on the substrate. In general, the ideal photoresist image

has the exact shape of the designed or intended pattern in the plane of
the substrate, with vertical walls through the thickness of the resist.
Thus, the final resist pattern is binary: parts of the substrate are
covered with resist while other parts are completely uncovered. This
binary pattern is needed for pattern transfer since the parts of the
substrate covered with resist will be protected from etching, ion
implantation, or other pattern transfer
mechanism.

The general sequence of steps for a typical

optical lithography process is as follows:
substrate preparation, photoresist spin coat,
prebake, exposure, post-exposure bake,
development, and postbake. A resist strip is
the final operation in the lithographic
process, after the resist pattern has been
transferred into the underlying layer via
etching or ion implantation. This sequence is generally performed on
several tools linked together into a contiguous unit called a lithographic
cluster.

Doping

Introduction

Doping refers to the addition of specific impurities to a semiconductor

to modify its electrical properties. In microfabrication the commonly
used ma- terial is silicon. Pure Si (intrinsic Si) is a poor conductor with a
negative temperature coefficient of resistance (i.e. resistance decreases
with rise in temperature) due to thermal generation of electrons and
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holes. Doping helps in exponentially increasing the conductivity and

also produces a stable, tem- perature independent, resistance around
room temperature. Doped or ex- trinsic semiconductors can be p or n
type depending on the nature of the impurity atom.

Doping means the introduction of impurities into the semiconductor

crystal to deliberately change its conductivity due to deficiency or
excess of electrons. In contrast to the doping during the wafer
fabrication, where the entire wafer is doped, this article describes the
partial doping of silicon. The introduction of foreign substances can be
achieved by diffusion, ion implantation (or alloy).

The starting wafers in integrated circuit (IC) manufacturing are usually p

or n type doped wafers. To form devices like transistors, diodes, or
resistors, specific regions of the wafer must be doped with specific
amounts and types of impurities. Some examples of doped devices are
shown in figure 1. There are two main methods of doping.

Figure 1: Schematic of a (a) diode, (b) MOSFET, and (c) BJT. These are
made by adding p and n type dopants to different parts of a base wafer.
In

(a) and (b) the base wafer is p type while it is n type in (c).

2. Thermal diffusion

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3. Ion implantation

The two methods are summarized in figure 2. As part of the process

flow, there are specific goals that doping should meet

1. Create a specific concentration of dopant atoms at and below

the surface of the wafer, i.e. establish a controlled
concentration gradient.

2. Create a junction (p-n or n-p or graded p or n) at a specific depth

from the wafer surface. This is important for MOSFETs since this
defines the channel width. In a BJT, doping is used to define
widths of the emitter, base, and collector regions.

3. Create specific distributions and concentrations of dopants

laterally along the wafer surface. This is related to patterning
and is used to define the smallest lateral region that can be
doped.

Thermal diffusion

Thermal diffusion is a two step process, similar to the steps in oxidation

process by consuming the underlying Si.

Deposition - dopant atoms are introduced at the wafer surface.

Drive-in - the dopant atoms then diffuse into the wafer to create the
required concentration gradient.

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Figure 2: Types of doping. (a) Thermal diffusion (b) Ion implantation. In

thermal diffusion, the maximum concentration is at the surface and
dopants diffuse into the wafer. In ion implantation, the dopants are
embedded below the surface.

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Figure 3: (a) The stages in thermal diffusion. The dopant atoms are in-
troduced at the wafer surface and they diffuse into the wafer. (b) A
cross section schematic showing the final concentration distribution.

The two steps are shown schematically in figure 3. While dopant atoms
move vertically into the wafer, there is also a lateral spread. This has
implications for the minimum dimensions of the region that can be
doped. In Si, the com- mon dopants are boron for p type and arsenic,
antimony, and phosphorus for n type.

Diffusion

Molecular diffusion, often called simply diffusion, is a net transport of

molecules from a region of higher concentration to one of lower
concentration by random molecular motion. The result of diffusion is a
gradual mixing of materials. To illustrate: a drop of ink in a glass of
water is evenly distributed after a certain amount of time. In a silicon

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crystal, one finds a solid lattice of atoms through which the dopant has
to move. This can be done in different ways:

 empty space diffusion: the impurity atoms can fill empty places in
the crystal lattice which are always present, even in perfect single
crystals

 inter lattice diffusion: the impurity atoms move in-between the

silicon atoms in the crystal lattice.

 changing of places: the impurity atoms are located in the crystal

lattice and are exchanged with the silicon atoms.

The dopant can diffuse as long as either a concentration gradient is

balanced, or the temperature was lowered, so that the atoms can no
longer move. The speed of the diffusion process depends on several
factors:

 dopant
 concentration gradient
 temperature
 substrate

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 crystallographic orientation of the substrate

Diffusion with an exhaustible source

Diffusion with an exhaustible source means that the dopant is available

in a limited amount only. The longer the diffusion process continues,
the lower the concentration at the surface, and therefore the depth of
penetration into the substrate increases. The diffusion coefficient of a
substance indicates how fast it moves in the crystal. Arsenic with a low
diffusion coefficient penetrates slower into the substrate, as for
example phosphorus or boron.

Diffusion with an inexhaustible source

In diffusion processes with an inexhaustible source the dopants are

available in unlimited amount, and therefore the concentration at the
surface remains constant during the process. Particles that have
penetrated into the substrate are continually replenished.

Diffusion methods

In the subsequent processes the wafers are placed in a quartz tube that
is heated to a certain temperature.

Diffusion from the gas phase

A carrier gas (nitrogen, argon, ...) is enriched with the desired dopant
(also in gaseous form, e.g. phosphine PH3 or diborane B2H6) and led to
the silicon wafers, on which the concentration balance can take place.

Diffusion with solid source

Slices which contain the dopants are placed in-between the wafers. If
the temperature in the quartz tube is increased, the dopant from the
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source discs diffuses into the atmosphere. With a carrier gas, the
dopant will be distributed uniformly, and thus reaches the surface of
the wafers.

Diffusion with liquid source

As liquid sources boron bromide BBr3 or phosphoryl chloride POCl3 can

be used. A carrier gas is led through the liquids and thus transporting
the dopant in gaseous state. Since not the entire wafers should be
doped, certain areas can be masked with silicon dioxide. The dopants
can not penetrate through the oxide, and therefore no doping takes
place at these locations. To avoid tensions or even fractions of the
discs, the quartz tube is gradually heated (e.g. +10 °C per minute) till
900 °C. Subsequent the dopant is led to the wafers. To set the diffusion
process in motion, the temperature is then increased up to 1200 °C.

Characteristic:

 since many wafers can be processed simultaneously, this method

is quite favorable

 if there already are dopants in the silicon crystal, they can diffuse
out in later processes due to high process temperatures

 dopants can deposit in the quartz tube, and be transported to the

wafers in later processes

 dopants in the crystal are spreading not only in perpendicular

orientation but also laterally, so that the doped area is enlarged in
a unwanted manner

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Diffusion sources

There are different sources for the dopant atoms. These can be solid,
liquid, or gaseous sources. Some examples of dopant materials for Si
are

1. Antimony (Sb) - Sb2O3 (s)

2. Arsenic (As) - As2O3 (s), AsH3 (g)
3. Phosphorus (P) - POCl3 (l), P2O5 (s), PH3 (g)
4. Boron (B) - BBr3 (l), B2O3 (s), BCl3 (g)

A more complete list of sources are shown in table 1.

For liquid and gaseous sources, a concentration of the dopant vapor

should

Table 1: Some commonly diffusion sources in silicon. The compound

and its state is also included. The use of dopants in different state
determines the shape of the concentration profile within the wafer.
Adapted from Microchip fabrication - Peter van Zant.

Type Element Compound Formula State

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n-type Antimony Antimony Trioxide Sb2O3 solid

Arsenic Arsenic Trioxide As2O3 solid

Phosphoro Arsine AsH3 gas
us POCl3 liquid
Phosphorous
P2O5 PH3 solid
oxychloride
gas
Phosphorous
Pentoxide Phosphine

p-type Boron Boron Tribromide BBr3 liquid

Boron Trioxide B2O3 solid

Diborane B2H6 BCl3 gas
BN gas
Boron Trichloride
solid
Boron Nitride

be established at the surface. For a liquid source, a carrier gas is usually

used to transport the vapors to the diffusion furnace. The setup is
shown

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Figure 4: Thermal diffusion setup with a liquid dopant source. A carrier

gas like nitrogen is bubbled through the dopant liquid and the vapor is
carried into the furnace. Oxygen is also used when an oxide surface
needs to be created along with doping.

in figure 4. A similar arrangement is used for gaseous sources. Here, the

carrier gas is used to dilute the dopant gas to the required
concentration. The gas manifold system is shown in figure 5. For solid
sources, wafer sized ”slugs” are packed into the furnace along with the
product wafers (e.g. for boron, boron nitride slugs can be used as solid
sources), this is called a solid neighbor source. Another option is to spin
on the oxide source on the wafer surface using a suitable solvent,
typically used for oxide sources. It is also possible to vaporize the solid
source is a neighboring furnace and use a carrier gas to transport the
vapors to the wafer. The use of solid sources in thermal diffusion is
shown in figure 6.

Drive-in

Once the dopant atoms have arrived on the wafer surface, they need to
be redistributed into the bulk. This process is called drive-in. At the
same time, the carrier gas could also react with the wafer surface,
especially if there is some reactive gas like oxygen (dry ox) or water
vapor (wet ox). These could cause oxidation of the Si along with dopant
diffusion. While this might be desirable under some circumstances, it
would also affect dopant distribution, since the presence of an oxide
layer can lead to an increase of n-type dopants and decrease of p-type
dopants, just below the interface. This is shown in figure 7. The drive-in
process requires diffusion of the impurities into Si. Depending on the

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relative size of the impurity atom, this can be either through vacancy
diffusion or interstitial diffusion. The interstitial

Figure 5: The gas manifold system for a thermal diffusion system. The dopant gas
and inert gas are mixed to get the right dopant concentration. There is also a
reaction gas, like oxygen, if an oxide layer also needs to be formed.

mechanism is shown in figure 8 while the substitutional mechanism is

shown in figure 9. Boron and Phosphorus are small and diffuse by a
dual (vacancy and interstitial mechanism) while As and Sb
predominantly diffuse by the vacancy mechanism.
 Diffusion concentration gradients
The amount of impurities that can be incorporated in Si depends on
the solid solubility. This depends on the impurity atom and
temperature, given by figure 10. To calculate the concentration of
the impurities as a function of depth from the wafer surface, Fick’s
laws of diffusion can be used. Fick’s first law is written as

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∂c(x, t)
(1)
J = −D
∂x
where J is the flux of impurity atoms, which is a constant with
respect to time (steady state diffusion) and c(x, t) is the
concentration at depth x and time t and D is the diffusion coefficient.
D is temperature dependent and is

Figure 6: Solid sources for thermal diffusion can be either (a) remote or (b)
neighbor sources. In a remote source the solid is vaporized and the vapors are
passed into the furnace. In neighbor sources, the solid is loaded in the furnace
along with the wafers. Both sources produce different concentration profiles in
the wafer.

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Figure 7: Growth of oxide layer on Si can cause (a) pile-up of n type impu- rities
and (b) depletion of p type impurities. The oxide layer can be grown along with
dopant diffusion or once diffusion is complete.

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Figure 8: Interstitial diffusion mechanism showing motion of dopant atom from

position in (a) to (b). Here, the dopant atom is smaller than the silicon atom, so
that interstitial doping is possible.

Figure 9: Substitutional diffusion mechanism showing motion of dopant atom

from position in (a) to (b). Substitutional diffusion happens when the dopant size
is comparable to the Si atom.

given by

(2)

where D0 is the pre-exponent factor and Ea is the activation energy for diffusion.
For unsteady state, with the flux varying with time and position, a more general
equation is Fick’s second law, given by

(3)

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The assumption is that D is not a function of concentration. By applying equations

1 and 3, it is possible to calculate the concentration gradient under various
conditions. The maximum amount of dopants that can be incorpo- rated is given
by the impurity solubility shown in 10. This represents the thermodynamic limit.
There are two common doping conditions that exist in thermal diffusion.

 Constant surface concentration

For gaseous and liquid sources, there is a constant concentration of impurities at

the surface. There is a vapor of impurity atoms (it is also true for a solid source
with remote evaporation) that maintains the constant concentration on the
surface. Also, the diffusion length is much smaller than the wafer thickness so
that the wafer can be approximated as a semi-infinite solid. In

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Figure 10: Solid solubility of various impurities in Si as a function of T. Commonly

used p and n dopants have high solubility, approaching the level of degenerate
semiconductors. Other impurities like metals and oxygen have solubility levels of
a few ppm.

Figure 11: Concentration profiles for constant surface concentration with in-
creasing time. The maximum concentration is at the surface. With increasing
time, the junction depth goes deeper within the wafer. The junction depth is
defined as when the dopant concentration becomes equal to the wafer bulk
doping level. In this case, the bulk dopant concentration is 10 13 cm−3.

This case, the impurity concentration, C(x, t), is given by

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Figure 12: Comparison of (a) and (c) error function solution and (b) and
(d) Gaussian solution to the diffusion equations, for different diffusion
lengths. Compared to the error function solution, the slope of the
Gaussian solution is less steep. Thus, there is greater penetration of the
dopants in the bulk, with respect to the surface concentration, for the
same diffusion length.

 Constant total dopant

In this scenario, the total amount of dopant atoms at the start of the
diffusion process is a constant and the concentration of the atoms at
the surface gradually decreases with time. This happens in the case of
doping from a solid source that is placed close to the wafer (either solid
slugs close to the wafer or dopants spun on the wafer surface). Let QT
be the total amount of dopants on the surface (at start of diffusion) per
unit area. Then, the concentration, C(x, t), is given by

This is a Gaussian function, in contrast to the error function solution for

a constant surface concentration. The change in surface concentration
as a function of time can be obtained from equation 6 with x = 0. This
gives

The error function and Gaussian solutions are compared in figure 12.

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Diffusion example

Consider a n-type Si wafer with As concentration of 1016 cm−3. A pn

junction is to be formed by diffusing p-type impurity, using a solid
boron source. The diffusion is to be carried out at 1000 K. The diffusion
coefficients for various dopants in Si, as a function of temperature, are
×
shown in figure 13. Extrapolating from figure 13, the diffusion
coefficient of B in Si at 1000 K is 2.9 10−18 cm2s−1. The diffusion
coefficient can also be calculated from known values of pre-exponent
factor (D0), which is 0.76 cm2s−1, and activation energy, which is (Ea) is
3.46 eV for B in Si, using equation 2.

Since B is a solid source, this is a case of constant total dopant

concentration, discussed in section 3.2. Hence, the concentration as√a
function of depth

and time, C(x, t), is given by equation 6. The term 4Dt represents
the

diffusion length for two-dimensional diffusion. Let QT be 1013 atoms

cm−2, is the total surface concentration per unit area at the start of the
process. Using equation 6, it is possible to calculate the junction depth
after a certain time, say t = 2 hrs. Junction depth, xpn, is defined at the
depth when the n and p concentrations are equal. At 2 hrs, and at 1100
◦
C, the depth, xpn is calculated to be 8.3 nm, represents a shallow
junction.

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To increase the junction depth (for the same time), the diffusion
coefficient has to be increased. One way to achieve
× this, is by increasing
temperature. For a temperature of 1200 K, the value of D is 2.3 10 −15
cm2s−1. This translates, using equation 6, into a junction depth of 180
nm.

A combination of error function and Gaussian diffusion profiles is used

for forming transistor junctions, e.g. BJT junction shown in figure 1. In
this case, the first layer is formed by diffusion from a solid source
(Gaussian profile) followed by diffusion from liquid or gas source (erf
profile), as shown in figure 14. The intersection points for the two
concentration profiles and the point where the Gaussian profile
intersects the base dopant concentration, represent the junction
locations. This is shown in figure 15. The dopant profiles will get
affected with any subsequent annealing steps. Pre-exponent factors
and activation energies for different dopants in Si are listed in table 2.

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Figure 13: Diffusion coefficients as a function of temperature for

different impurities in Si. This is a semi log plot of concentration vs.
inverse temperature and the slope gives the activation energy.

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Figure 14: Concentration profiles for multiple diffusion sources. The

Gaussian profile is less steep than the error function solution. The
intersection of the two profiles and the intersection of the Gaussian
profile with the bulk doping level represent the positions of the
junctions.

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Figure 15: (a) Concentration profiles from a solid and liquid/gas source
(b) Net dopant concentration as a function of depth (c) Formation of a
BJT resulting from the dopant concentration in (b).

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Figure 16: Lateral diffusion below an oxide window for (a) constant
source diffusion (b) depleting source diffusion. Lateral diffusion
increases with diffusion length, either increase in D or t.

Ion implantation

The biggest limitation of thermal diffusion is that the process is

isotropic i.e. lateral diffusion cannot be avoided, though diffusion
coefficients in different crystallographic directions might be different.
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Thus, an oxide window that serves as a mask to protect certain regions

of the wafers, can be ineffective due to lateral diffusion. This is shown
in figure 16. This is especially important for doping small regions (due to
device miniaturization). Doping control is also difficult to achieve due to
presence of concentration gradients. These gradients will change in
subsequent annealing steps. Thus, there is a thermal budget associated
with doping.

Ion implantation is a relatively newer doping technique that operates

close to room temperature. It is a physical process of doping, not based
on a chemical reaction. Since ion implantation takes place close to
room temperature, it is compatible with conventional lithographic
processes, so small regions can be doped. Also, since temperature is
low, lateral diffusion is negligible.

In ion implantation, dopant atoms are ionized, isolated, accelerated and

made to impinge on the wafer surface. These atoms penetrate some
depth into the material and get embedded into the wafer. The
schematic of the process is shown in figure 17. The source material is
usually in the form of a gas

AsH3, PH3, and BF3 are some common sources. Similarly, elemental
sources like As and P are also used as solid sources. Electron
bombardment is used to create ions. The ions are then separated using
a mass analyzer, which is a 90◦ magnet, which bends the ions
depending on the mass. After selection, the desired ions are then
accelerated and made to impinge on the wafer surface. Beam scanning
or rastering is also possible using electric field coils to deflect the ion
beams.

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The penetration depth of the ions depend on their energy (changed by

the accelerating field). The concentration profile for ion implantation is
shown in figure 18. The maximum concentration is at a certain depth
below the surface, called range. In thermal diffusion, the maximum
concentration is at the surface and the concentration decreases with
depth. The range depends on the ion type and the energy, as shown in
figure 19. There are two stopping mechanisms - the nucleus of the
wafer atoms and the interaction of the positive ions with the electrons.
In ion implantation, the beam density (# ions/cm2), ion energy, and
orientation of the wafer matter.

In the ion implantation charged dopants (ions) are accelerated in an

electric field and irradiated onto the wafer. The penetration depth can
be set very precisely by reducing or increasing the voltage needed to
accelerate the ions. Since the process takes place at room temperature,
previously added dopants cannot diffuse out. Regions that should not
be doped, can be covered with a masking photoresist layer.

An implanter consists of the following components:

 ion source: the dopants in gaseous state (e.g. boron trifluoride

BF3) are ionized

 accelerator: the ions are drawn with approximately 30

kiloelectron volts out of the ion source

 mass separation: the charged particles are deflected by a

magnetic field by 90 degrees. Too light/heavy particles are
deflected more/less than the desired ions and trapped with
screens behind the separator

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 acceleration lane: several 100 keV accelerate the particles to their

final velocity (200 keV accelerate bor ions up to 2.000.000 m/s)

 Lenses: lenses are distributed inside the entire system to focus

the ion beam

 distraction: the ions are deflected with electrical fields to irradiate

the desired location

 wafer station: the wafers are placed on large rotating wheels and
held into the ion beam

Illustration of an ion implanter

Penetration depth of ions in the wafer

In contrast to diffusion processes the particles do not penetrate into

the crystal due to their own movement, but because of their high
velocity. Inside the crystal they are slowed down by collisions with
silicon atoms. The impact causes damage to the lattice since silicon
atoms are knocked from their sites, the dopants themselves are mostly

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placed interstitial. There, they are not electrically active, because there
are no bonds with other atoms which may give rise to free charge
carriers. The displaced silicon atoms must be re-installed into the
crystal lattice, and the electrically inactive dopants must be activated.

Recovery the crystal lattice and activation of dopants

Right after the implantation process, only about 5 % of the dopants are
bond in the lattice. In a high temperature process at about 1000 °C, the
dopants move on lattice sites. The lattice damage caused by the
collisions have already been cured at about 500 °C. Since the dopants
move inside the crystal during high temperature processes, these steps
are carried out only for a very short time.

Channeling

The substrate is present as a single crystal, and thus the silicon atoms
are regularly arranged and form "channels". The dopant atoms injected
via ion implantation can move parallel to these channels and are
slowed only slightly, and therefore penetrate very deeply into the
substrate. To prevent this, there are several possibilities:

 wafer alignment: the wafers are deflected by about 7° with

respect to the ion beam. Thus the radiation is not in parallel
direction to the channels and the ions are decelerated by
collisions immediately.

 scattering: on top of the wafer surface a thin oxide is applied,

which deflects the ions, and therefore prevents a parallel arival

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Characteristic:

 the reproducibility of ion implantation is very high

 the process at room temperature prevents the outward diffusion

of other dopants

 spin coated photoresist as a mask is sufficient, an oxide layer, as it

is used in diffusion processes, is not necessary

 ion implanters are very expensive, the costs per wafer are
relatively high

 the dopants do not spread laterally under the mask (only

minimally due to collisions)

 nearly every element can be implanted in highest purity

 previous used dopants can deposit on walls or screens inside the

implanter and later be carried to the wafer

 three-dimensional structures (e.g. trenches) can not be doped by

ion implantation

 the implantation process takes place under high vacuum, which

must be produced with several vacuum pumps

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There are several types of implanters for small to medium doses of ions
(1011 to 1015 ions/cm2) or for even higher doses of 1015 to 1017
ions/cm2.

The ion implantation has replaced the diffusion mostly due to its
advantages.

Doping using Alloy

For completeness it should be mentioned that besides ion implanation

and diffusion there is an alternative process: doping using alloy. Since
this procedure, however, brings disadvantages with it such as cracks in
the substrate, it is not used in today's semiconductor technology any
more.

In ion implantation, since the wafer surface is impacted by high energy

ions, it can cause damage by knocking Si atoms from their position,
causing local structural damage. This needs a a post thermal annealing
treatment to repair the damage. There are two ways of doing this.

1. Tube furnace - low temperature annealing (600-1000 ◦C). To

minimize lateral diffusion.

2. Rapid thermal annealing - higher temperatures are possible but

for shorter times.

Ion implantation is especially useful with device scaling. It can be used

to create shallow junctions, by having a small range. It can also be used
to dope small regions. It is usually used later in the process flow when
thermal budgets are tight and the high temperature of thermal
diffusion is not allowed.

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Figure 17: Schematic of the ion implantation process. Dopant atoms are ionized
by bombarding with electrons. These are then isolated, accelerated, and then
impinged on the wafer. There is also a scanning system that allows the ion beam
to scan over the wafer surface.

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Figure 18: Concentration profile for ion implantation. The maximum con-
centration is below the wafer surface, unlike thermal diffusion, and the depth
increases with the ion energy.

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Figure 19: Plot of the range (penetration depth) vs. ion energy for three different
dopants, i.e P, As, and S. Channeling effects are shown for S, marked SA and SB.

Etching

This is is the removal of the silicon dioxide layer from selected regions
across the wafer where the photoresist was removed after
development. In this industry, two etching processes exist; wet
chemical etching and dry plasma etching. In wet etching process, an
acid solution (eghydrofluoric acid buffered with ammonium fluoride) is
typically used to chemically attack the silicon dioxide and not the
protective layer.

In dry plasma etching, the wafer is exposed to an ionized gas in a

vacuum chamber. (the gas is usually a mix of nitrogen, chlorine and
boron trichloride). Electrical energy is then used to ionize a portion of
the gas, thus creating a plasma. The high-energy plasma then reacts
with the unprotected target surface and removes material by
vaporization.

Wet chemical etching is the older of the two processes and is easier to
use however in wet etching, process variables such as immersion time,
etchant concentration and temperature are critical factors which must
be controlled because under/over etching can easily occur. An
advantage of plasma etching is that it’s etching is much more defined
and is more anisotropic, thus it follows the directed path better than
wet chemical etching and can create sharp contours. This reduces the
potential under/over-cut which the wet-etching can produce.

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The etch process removes selected areas from the surface of the wafer
so that other materials may be deposited.

“Dry” (plasma) etching is used for circuit-defining steps, while “wet”

etching (using chemical baths) is used mainly to clean wafers. Dry
etching is one of the most frequently used processes in semiconductor
manufacturing. Before etching begins, a wafer is coated with
photoresist or a hard mask (usually oxide or nitride) and exposed to a
circuit pattern during photolithography. Etching removes material only
from the pattern traces. This sequence of patterning and etching is
repeated multiple times during the chip making process.

Etch processes are referred to as conductor etch, dielectric etch, or

polysilicon etch to indicate the types of films that are removed from the
wafer. For example, dielectric etch is involved when an oxide layer is
etched to leave “oxide isolators” separating devices from each other;
polysilicon etch is used to create the gate in a transistor; dielectric etch
is employed to etch via holes and trenches for metal conductive paths;
and metal etch removes aluminum, tungsten, or copper layers to reveal
the pattern of circuitry at progressively higher levels of the device
structure.

Plasma etching is performed by applying electromagnetic energy

[typically radio frequency (RF)] to a gas containing a chemically reactive
element, such as fluorine or chlorine. The plasma releases positively
charged ions that bombard the wafer to remove (etch) materials and
chemically reactive free radicals that react with the etched material to
form volatile or nonvolatile byproducts. The electric charge of the ions
directs them vertically toward the wafer. This produces the almost
vertical etch profiles essential for the miniscule features in today’s

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densely packed chip designs. Typically, high etch rates (amount of

material removed in a given time) are desirable.

Process chemistries differ depending on the types of films to be etched.

Those used in dielectric etch applications are typically fluorine-based.
Silicon and metal etch use chlorine-based chemistries. A specific etch
step may be performed on one or more film layers. When multiple
layers are involved and also when the etch process must stop precisely
on a particular layer without damaging it, the selectivity of the process
becomes important. Selectivity is the ratio of two etch rates: the rate
for the layer to be removed and the rate for the layer to be protected
(e.g. mask or stop layer). Higher selectivities are usually desirable.

In reactive ion etching (RIE), described above, the objective is to

optimize the balance between physical and chemical etching such that
physical bombardment (etch rate) is sufficient to remove the requisite
material while appropriate chemical reactions occur to form either
easily exhausted volatile byproducts or protective deposits on the
remainder (selectivity and profile control). Magnetically enhanced RIE
can aid processing by increasing ion density without increasing ion
energy (which can damage the wafer).

Ideally, the etch rate is the same (uniform) at all points on a wafer. The
degree to which it might vary at different points on the wafer is known
as non-uniformity (or microloading) and is usually expressed as a
percentage. Minimizing non-uniformity and microloading are important
objectives in etching.

Applied Materials has consistently developed innovative and cost-

effective solutions to evolving etch challenges. These can arise from
ever-decreasing device sizes; changes in materials used (such as high-
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k films or ultra-porous dielectrics); diversification in device architecture

(such as FinFETs and 3D NAND transistors), and new packaging
approaches (such as TSV technology).

Photoresist removal: After etching, the remaining resist coating that is

left on the surface must be removed. Stripping of this excess
photoresist residue can be accomplished either using dry or wet
techniques. For wet stripping, a mixture of liquid chemicals can be
used; a solution of sulfuric acid and hydrogen peroxide is common. Dry
stripping uses a high temperature plasma etching with oxygen as the
reactive gas to remove the resist without damaging the circuit layers.

Spin, rinse and dry:The wafer is cleaned with deionized water and dried
with nitrogen by means of a special tool called SRD. Since modern
semiconductor devices are so microscopically small, the circuitry can be
destroyed even by the smallest dust or dirt particle. To solve this
problem and prevent this from happening, all the processing steps are
conducted in ultra-clean rooms.

In the processing of a given wafer, the photolithographic process is

repeated as many times as needed in order to make the desired
integrated circuit, using a different mask at each layer to define the
appropriate pattern.

Etching Processes

In order to form a functional MEMS structure on a substrate, it is

necessary to etch the thin films previously deposited and/or the
substrate itself. In general, there are two classes of etching processes:

1. Wet etching where the material is dissolved when immersed in a

chemical solution
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2. Dry etching where the material is sputtered or dissolved using

reactive ions or a vapor phase etchant

In the following, we will briefly discuss the most popular technologies

for wet and dry etching.

Wet etching

This is the simplest etching technology. All it requires is a container

with a liquid solution that will dissolve the material in question.
Unfortunately, there are complications since usually a mask is desired
to selectively etch the material. One must find a mask that will not
dissolve or at least etches much slower than the material to be
patterned. Secondly, some single crystal materials, such as silicon,
exhibit anisotropic etching in certain chemicals. Anisotropic etching in
contrast to isotropic etching means different etch rates in different
directions in the material. The classic example of this is the <111>
crystal plane sidewalls that appear when etching a hole in a <100>
silicon wafer in a chemical such as potassium hydroxide (KOH). The
result is a pyramid shaped hole instead of a hole with rounded
sidewalls with a isotropic etchant. The principle of anisotropic and
isotropic wet etching is illustrated in the figure below.

Figure 1: Difference between anisotropic and isotropic wet etching.

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Dry etching

The dry etching technology can split in three separate classes called reactive ion
etching (RIE), sputter etching, and vapor phase etching.

In RIE, the substrate is placed inside a reactor in which several gases are
introduced. A plasma is struck in the gas mixture using an RF power source,
breaking the gas molecules into ions. The ions are accelerated towards, and reacts
at, the surface of the material being etched, forming another gaseous material.
This is known as the chemical part of reactive ion etching. There is also a physical
part which is similar in nature to the sputtering deposition process. If the ions
have high enough energy, they can knock atoms out of the material to be etched
without a chemical reaction. It is a very complex task to develop dry etch
processes that balance chemical and physical etching, since there are many
parameters to adjust. By changing the balance it is possible to influence the
anisotropy of the etching, since the chemical part is isotropic and the physical
part highly anisotropic the combination can form sidewalls that have shapes from
rounded to vertical. A schematic of a typical reactive ion etching system is shown
in the figure below.

A special subclass of RIE which continues to grow rapidly in popularity is deep RIE
(DRIE). In this process, etch depths of hundreds of microns can be achieved with
almost vertical sidewalls. The primary technology is based on the so-called "Bosch
process", named after the German company Robert Bosch which filed the original
patent, where two different gas compositions are alternated in the reactor. The
first gas composition creates a polymer on the surface of the substrate, and the
second gas composition etches the substrate. The polymer is immediately
sputtered away by the physical part of the etching, but only on the horizontal
surfaces and not the sidewalls. Since the polymer only dissolves very slowly in the
chemical part of the etching, it builds up on the sidewalls and protects them from
etching. As a result, etching aspect ratios of 50 to 1 can be achieved. The process
can easily be used to etch completely through a silicon substrate, and etch rates
are 3-4 times higher than wet etching.

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Sputter etching is essentially RIE without reactive ions. The systems used are very
similar in principle to sputtering deposition systems. The big difference is that
substrate is now subjected to the ion bombardment instead of the material target
used in sputter deposition.

Vapor phase etching is another dry etching method, which can be done with
simpler equipment than what RIE requires. In this process the wafer to be etched
is placed inside a chamber, in which one or more gases are introduced. The
material to be etched is dissolved at the surface in a chemical reaction with the
gas molecules. The two most common vapor phase etching technologies are
silicon dioxide etching using hydrogen fluoride (HF) and silicon etching using
xenon diflouride (XeF2), both of which are isotropic in nature. Usually, care must
be taken in the design of a vapor phase process to not have bi-products form in
the chemical reaction that condense on the surface and interfere with the etching
process.

Figure 2: Typical parallel-plate reactive ion etching system.

Isolation Techniques

Thermal grown oxide is mainly used as isolation material in

semiconductor fabrication. For the isolation of
neighboring MOS transistors there exist two techniques, namely Local
Oxidation of Silicon and Shallow Trench Isolation. The differences in
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their process flow and their final oxide shapes are described in the
following.
Local Oxidation of Silicon

Local Oxidation of Silicon (LOCOS) is the traditional isolation technique.

At first a very thin silicon oxide layer is grown on the wafer, the so-
called pad oxide. Then a layer of silicon nitride is deposited which is
used as an oxide barrier. The pattern transfer is performed by
photolithography. After lithography the pattern is etched into the
nitride. The result is the nitride mask as shown in Fig. 1.1a, which
defines the active areas for the oxidation process. The next step is the
main part of the LOCOS process, the growth of the thermal oxide. After
the oxidation process is finished, the last step is the removal of the
nitride layer. The main drawback of this technique is the so-called bird's
beak effect and the surface area which is lost to this encroachment. The
advantages of LOCOS fabrication are the simple process flow and the
high oxide quality, because the whole LOCOS structure is thermally
grown.

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Figure 1.1: Process sequence for local oxidation of silicon (LOCOS).

Shallow Trench Isolation

The Shallow Trench Isolation (STI) is the preferred isolation technique

for the sub-0.5 m technology, because it completely avoids the bird's
beak shape characteristic. With its zero oxide field encroachment STI is
more suitable for the increased density requirements, because it allows
to form smaller isolation regions. The STI process starts in the same
way as the LOCOS process. The first difference compared to LOCOS is
that a shallow trench is etched into the silicon substrate, as shown in
Fig. 1.2a. After underetching of the oxide pad, also a thermal oxide in
the trench is grown, the so-called liner oxide (Fig. 1.2c). But unlike
with LOCOS, the thermal oxidation process is stopped after the
formation of a thin oxide layer, and the rest of the trench is filled with a
deposited oxide (Fig. 1.2d). Next, the excessive (deposited) oxide is
removed with chemical mechanical planarization. At last the nitride

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mask is also removed. The price for saving space with STI is the larger
number of different process steps.

Figure 1.2: Steps in a typical shallow trench isolation (STI) process flow.

Wafer Fab Isolation Techniques

The individual components that make up the circuit on a monolithic die

need to have electrical isolation from each other in order to function.
The most common techniques used for achieving component isolation
during wafer fabrication include the following: 1) by employing reverse-
biased p-n junctions; 2) through what is known as mesa isolation; 3) by
wafer bonding to an insulating substrate; 4) by oxide isolation; 5) by
trenching; and 6) through a combination of any of these processes.

A reverse-biased p-n junction has an extremely low leakage current,

which is why its use as an isolation technique during wafer fabrication is
very common. By doping two adjacent regions with opposite types of
conductivity and providing them with adequate reverse biasing, they
become effectively isolated from each other. Under such a situation,
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the coupling between the regions is only capacitive in nature, which

becomes an issue only at high frequencies.

Another somewhat obvious technique for achieving component

isolation is known as mesa isolation. This involves the building of the
components on an active film which was grown on an insulating (or
semi-insulating) film, and then etching moats around the components.
This results in the components becoming individual 'islands', or 'mesas',
hence the name 'mesa isolation' given to this isolation technique.
Circuits fabricated on silicon on insulators, as well as those made on
epitaxial GaAs over semi-insulating (SI) GaAs substrate, are examples
of applications of mesa isolation.

Wafer bonding to an insulative substrate may be considered as a

variant of mesa isolation. This isolation technique takes advantage of
the fact that any two flat, smooth, clean, and hydrophilic surfaces can
be bonded at ambient temperature without the use of external forces.
Wafer bonding can be applied to widely dissimilar materials. Once the
moats are etched around the 'mesas', isolation is provided by the
insulating substrate.

As its name implies, oxide isolation techniques consist of a series of

material deposition and removal steps that leads to the formation of
active single-crystal tubs that are completely surrounded by an oxide
layer. Such oxide layers, once formed, provide near-perfect isolation
between the active tubs.

Trenching is a process wherein anisotropic wet etching or reactive ion

etching is employed to dig a trench around the active region. The dug
trench is then filled up with isolating material. Planarization is done
after filling up the trenches.
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Metallization

Metallization is a deposition process which aims to serve several duties.

The deposition of conductive materials is done to; further form certain
components in the IC, provide the critical interconnection paths
between the separate devices on the chip and to also allow the chip to
be connected to external circuits by forming the bonding pads that
connect the chip to its exterior package and eventually to the circuit
board of the system it will support.

The conducting materials used are not just any regular metals. These
metals must have specific properties relating to electrical conductivity
and ease of use in the manufacturing processing. These metals should
have a low resistivity and have low-contact resistance with silicon
whilst maintaining a good adherence to the silicon substrate or silicon
dioxide layer. The metals should be easily deposited and must be
compatible with photolithography and not react in any negative way
(eg corrosion, contamination). The metals must also be able to
withstand the high temperatures experienced during manufacturing
and preferably have a long lifetime. Currently no conducting material
which satisfies all these properties perfectly exists on the market,
however aluminium is a close second as it reaches most of these
requirements well. Hence, this is why it is the most commonly used
metallization material. To improve aluminium’s role in the metallization
process, it is usually alloyed with copper to prevent the movement of
aluminium atoms which can occur by flow of current whilst the IC is in
service. It can also be doped with small amounts of silicon to reduce its
reactivity with silicon in the substrate.

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Just as in the photolithography process; the doping and metallization

processes can be repeated as many times as necessary to create the
multiple layers in an IC.

Metallization is the final step in the wafer processing sequence.

Metallization is the process by which the components of IC’s are
interconnected by aluminium conductor. This process produces a thin-
film metal layer that will serve as the required conductor pattern for
the interconnection of the various components on the chip. Another
use of metallization is to produce metalized areas called bonding pads
around the periphery of the chip to produce metalized areas for the
bonding of wire leads from the package to the chip. The bonding wires
are typically 25 micro meters diameter gold wires, and the bonding
pads are usually made to be around 100×100 micro meters square to
accommodate fully the flattened ends of the bonding wires and to
allow for some registration errors in the placement of the wires on the
pads.

Aluminium

Aluminium (At) is the most commonly used material for the

metallization of most IC’s, discrete diodes, and transistors. The film
thickness is as about 1 micro meters and conductor widths of about 2
to 25 micro meters are commonly used. The use of aluminium offers
the following advantages:

 It has as relatively good conductivity.

 It is easy to deposit thin films of Al by vacuum evaporation.
 It has good adherence to the silicon dioxide surface.

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 Aluminium forms good mechanical bonds with silicon by sintering

at about 500°C or by alloying at the eutectic temperature of
577°C.
 Aluminium forms low-resistance, non-rectifying (that is, ohmic)
contacts with p-type silicon and with heavily doped n-type silicon.
 It can be applied and patterned with a single deposition and
etching process.

Aluminium has certain limitations:

1. During packaging operation if temperature goes too high, say

600°C, or if there is overheating due to current surge, Al can fuse
and can penetrate through the oxide to the silicon and may cause
short circuit in the connection. By providing, adequate process
control and testing, such failures can be minimized.

2. The silicon chip is usually mounted in the package by a gold

perform or die backing that alloys with the silicon. Gold lead wires
have been bonded to the aluminium film bonding pads on the
chip, since package lead are usually gold plated. At elevated
temperatures, a reaction between the metal of such systems
causes formation of intermetallic compounds, known as the
purple plague. Purple plague is one of six phases that can occur
when gold and aluminium inter-diffuse. Because of dissimilar rate
of diffusion of gold and aluminium, voids normally occur in the
form of the purple plague. These voids may result in weakened
bonds, resistive bonds or catastrophic failure. The problem is
generally solved by using aluminium lead wires, or another metal
system, in circuits that will be subjected so elevated
temperatures. One method is to deposit gold over an under layer

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of chromium. The chromium acts as a diffusion barrier to the gold

and also adheres well to both oxide and gold. Gold has poor
adhesion to oxide because it does not oxide itself. However, the
chromium-gold process is comparatively expensive, and it has an
uncontrollable reaction with silicon during alloying.

3. Aluminium suffers from electromigration which can cause

considerable material transport in metals. It occurs because of the
enhanced and directional mobility of atoms caused by the direct
influence of the electric field and the collision of electrons with
atoms, which leads to momentum transfer. In thin-film
conductors that carry sufficient current density during device
operations, the mode of material transport can occur at much
lower temperature (compared to bulk metals) because of the
presence of grain boundaries, dislocations and point defects that
aid the material transport. Eecctromigration-induced failure is the
most important mode of failure in Al lines.

In general the desired properties of the metallization for IC can be listed

as follows.

 Low resistivity.
 Easy to form.
 Easy to etch for pattern generation.
 Should be stable in oxidizing ambient , oxidizable.
 Mechanical stability; good adherence, low stress.
 Surface smoothness.
 Stability throughout processing including high temperature sinter,
dry or wet oxidation, gettering, phosphorous glass (or any other
material) passivation, metallization.
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 No reaction with final metal, aluminium.

 Should not contaminate device, wafers, or working apparatus.
 Good device characteristics and life times.
 For window contacts-low contact resistance, minimum junction
penetration, low electromigration.

Metallization Application in VLSI

For VLSI, metallization applications can be divided into three groups:

1 Gates for MOSFET

2 Contacts, and
3 Interconnects.

Interconnection metallization interconnects thousands of MOSFETs or

bipolar devices using fine-line metal patterns. It is also same as gate
metallization for MOSFET. All metallization directly in contact with
semiconductor is called contact metallization. Polysilicon film is
employed in the form of metallization used for gate and
interconnection of MOS devices. Aluminium is used as the contact
metal, on devices and as the second-level inter-connection to the
outside world. Several new schemes for metallization have been
suggested to produce ohmic contacts to a semiconductor. In several
cases a multiple-layer structure involving a diffusion barrier has been
recommended. Platinum silicide (PtSi) has been used as a Schottky
barrier contact and also simply as an ohmic contact for deep junction.
Titanium/platinum/gold or titanium/palladium/gold beam lead
technology has been successful in providing high-reliability connection
to the outside world. The applicability of any metallization scheme in
VLSI depends on several requirements. However, the important

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requirements are the stability of the metallization throughout the IC

fabrication process and its reliability during the actual use of the
devices.

In VLSI, different new Metallization Process schemes for gate,

interconnections, ohmic contacts are introduced. But the application of
any new metallization scheme is tested in accordance with certain
requirements as given below.

 The metal layer should be of low resistivity.

 The formation of layer should be easy.
 The layer should be easy for pattern generation to etched off.
 The layer should be stable in oxidizing ambients.
 The layer should have surface smoothness; mechanically stable
with low stress and good adherence.
 The layer should not react with final metal.
 The metal should not contaminate devices, wafers.
 The device characteristics should be good enough.

Based on the types of applications there are three types of

Metallization Process namely

1. Gate metallization:

The metallization which connects a base (in bipolar transistors) or gate

(in MOSFETs) to the neighbouring two regions is called gate
metallization.

2. Contact Metallization:

The metallization which is directly in contact with semiconductor is

called contact metallization.

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3. Interconnection Metallization:

The metallization which connects number of bipolar devices or

MOSFETs is called interconnection metallization.

Ohmic contacts

When a metal is deposited on the semiconductor a good ohmic contact

should be formed. This is possible, if the deposition metal does not
perturb device characteristics. Also die contact should be stable both
electrically and mechanically.

Other important application of metallization is the top-level metal that

provides a connection to the outside world. To reduce interconnection
resistance and save area on a chip, multilevel metallization, as
discussed in this section is also used. Metallization is also used to
produce rectifying (Schottky barrier) contacts, guard rings, and diffusion
barriers between reacting metallic films.

We have already stated the desired properties of metallization for ICs.

None of the metals satisfies all the desired characteristics. Even Al,
which has most of the desired properties suffers from a low melting
point-limitation and electromigration as discussed above.

Poly-silicon has been used for gate metallization, for MOS devices.
Recently, poly-silicon/refractory metal silicide bi-layers have replaced
poly-silicon so that lower resistance an be achieved at the gale and
interconnection level. By preserving the use of polysilicon as the
“metal” in contact with the gate oxide, well known device
characteristics and processes have been unaltered. The silicides of
molybdenum (MoSi2), tantalum (TaSi2) and tungsten (WSi2) have been
used in the production of microprocessors and random-access
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memories. TiSi2 and CoSi2 have been suggested to replace MoSi2, TaSi2,
and WSi2. Aluminium and refractory metals tungsten and Mo are also
being considered for the gate metal.

For contacts, Al has been the preferred metal for VLSI. However, for
VLSI applications, several special factors such as shallower junctions,
step coverage, electromigration (at higher current densities), and
contact resistance can no longer be ignored. Therefore, several possible
solutions to the contact problems in VLSI have been considered. These
include use of

 Dilute Si-Ai alloy.

 Polysilicon layers between source, drain, or gate and top-level Al.
 Selectively deposited tungsten, that is, deposited by CVD methods
so that metal is deposited only on silicon and not on oxide.
 A diffusion barrier layer between silicon and Al, using a silicide,
nitride, carbide, or their combination.

Use of self-aligned silicide, such as, PtSi, guarantees extremely good

metallurgical contact between silicon and silicide. Silicides are also
recommended in processes where shallow junctions and contacts are
formed at the same time. The most important requirement of an
effective metallization scheme in VLSI is that metal must adhere to the
silicon in the windows and to the oxide that defines die window. In this
respect, metals such as, Al, Ti, Ta, etc., that form oxides with a heat of
formation higher than that of Si02 are the best. This is why titanium is
the most commonly used adhesion promoter.

Although silicides are used for contact metallization, diffusion barrier is

required to protect from interaction with Al which is used as the top

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metal. Aluminium interacts with most silicides in the temperature

range of 200-500 degree Celsius. Hence transition metal nitrides,
carbides, and borides are used as a diffusion barrier between silicide (or
Si) and Al due to their high chemical stability.

Metallization Processes

Metallization Process in which a thin layer of metal is formed which is

used to make interconnections between the components on the chip as
well as interconnections between the components and the outside
world.

Metals and Alloys for Metallization:

In most of the IC’s, aluminium is the widely used metal for metallization
because

 it is a good conductor
 it can form mechanical bonds with silicon
 it can form loW resistance, ohmic contacts with heavily doped
n-type and p-type silicon.

But now a days alongwith aluminium, platinum silicide (Pt Si) has been
used as a schottky barrier contact. It may be used as an ohmic contact
simply for deep junctions. For high reliable connections to the outside,
platinum / titanium / gold beam lead technology is prefered.

Actually no metal satisfies all the desired properties. Eventhough

aluminium is most widely used metal, it has certain drawbacks such as :

 low melting point

 undesirable electromigration behaviour.

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In MOS devices, polysilicon is generally used for gate metallization.

With this metal in contact with gate oxides, devices characteristics and
processes are unaltered. To have low resistance at gate and
interconnection level, polysilicon is replaced by polysilicon /refractory
silicides.

In the production of microprocessors and RAMs, refactor silicides with

highest compatibility are used. The common examples are
molybdenum (MoSi2), tantalum (TaSi2) and tungston (WSi2) which are
all disilicides.

Because of junction spiking, high contact resistance, electromigration

resistance, contact failure takes place. The contact problems can be
overcome by using (i) Si-Alalloy, polysilicon layers gate and aluminium,
(iii) selectively deposited tungston. Some times self aligned silicide such
as platinum silicide (PtSi) is used inbetween silicon and silicide to
ensure high metallurgical contact.

When aluminium is used as a top metal there is a possibility of

interaction of silicide with aluminium in the 200 to 500° C temperature
range. To overcome this, transition metal nitrides, carbides and borides
are used as barrier between silicide and aluminium.

Lastly the most important characteristics of a Metallization Process is

that it should be good adhesive. From that point of view, the metals,
forming oxides, such as Al, Ta, Tl etc are most commonly used. The
titanium is the most commonly used metal providing good adherence.
The important property of titanium is that it forms a good bond with
SiO2 at two temperatures and acts as a glue layer.

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The following Table 1.5 gives the list of metals and alloys used for
different metallization applications.

Metallization Metals / Alloys

Polysilicon, silicides, nitrides,

carbides, borides, refractory metals,
Gates, contacts and aluminium and alloys of two or three
1. interconnections. of above.

2. Top level. Aluminium.

3. Diffusion barrier. Nitrides, carbides, silicides, borides.

4.. Selectiyely formed. Tungston, aluminium and silicides.

The important properties of the metallization are

 resistivity (μΩ-cm),
 melting point (°C), and
 linear thermal expansion coefficient (ppm/ ° C)

The resistivity ρ for the pure, thick and single crystalline film is lower ;
while for impure and grain boundaries, it is higher. Due to chemical or
metallurgical interactions, the resistivity of metallization either
increases or decreases.

The second important property is the melting point. The solid state
diffusion controls grain growth, annealing of defects as well as

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interactions in solid state. It is observed that the solid state is effective

only at a temperature larger than one third of the melting point of the
solid in which diffusion takes place.

The last property is the thermal expansion coefficient a. If there is a

difference between the thermal expansion coefficients of the film and
substrate, the stress conditions are observed on thin films. The stress
will be greater, if the difference between the thermal expansions
coefficients is more. The silicides show large stress conditions. This
internal stress is balanced by a substrate producing opposite stress.
Thus for proper formation of metal layer on substrate, the film stresses
and factors affecting must be studied in detail.

The Metallization Process takes place in a chamber which is called

vacuum evaporation chamber. The chamber pressure is adjusted to the
range of 10-6 to 10-7 Torr. The material to be evaporated is placed in a
basket. Then using electron gun, high power density electron beam is
focused at the surface of the material. Due to this, material starts
heating up and vaporizing. These vapours hit substrate and condence
there to form a thing film coating. After the metalization process is
over, the thin film is patterned to form required interconnections. By
using proper etching process, aluminium is removed form unwanted
places.

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Metallisation Deposition process can be classified info two types:

1 CVD and
2 Physical Vapour Deposition

1. Chemical vapour deposition :

This process has number of advantages over other process such as, (i)
low temperature process, (ii) high throughput, and (iii) excellent step
coverage.

Using chemical vapour deposition technique only Molybdenum and

tungston is depositied. This process is carried at low pressure, hence
also known as LPCVD. Using laser CVD, selective area deposition or
direct writing throughout, both is possible.

CVD offers three important advantages. They are

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 Excellent step coverage

 Large throughput
 Low-temperature processing
 The basic physical vapour deposition methods are
 Evaporation
 Sputtering

Both these methods have three identical steps.

 Converting the condensed phase (generally a solid) into a

gaseous or vapour phase.
 Transporting the gaseous phase from the source to the
substrate, and
 Condensing the gaseous source on the substrate.

In both methods the substrate is away from the source.

In cases where a compound, such as silicide, nitride, or carbide, is

deposited one of the components is as gas and the deposition process
is termed reactive evaporation or sputtering.

2. Physical vapour deposition :

There are two types of physical vapour deposition processes namely

evaporation and sputtering. In both the processes, first the condensed
phase of the solid is converted into gaseous or vapour phase. Then the
gaseous phase of the solid is transported to the substrate. And then
lastly the gaseous source is condensed on the substrate followed by
film growth.

The evaporation method is the simplest method of film deposition by

the condensation of a vapour on a substrate. In this method, the

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temperature of the substrate is maintained lower than that of the

vapour. When any metal is heated to sufficiently high temperature, it
vapourizes. To heat a metal to high temperature different methods of
heating are used such as resistance heating, inductive heating, electron
bombardment and laser heating. For aluminium, which is the most
common metal used for Metallization Process, any of the methods can
be used.

In sputter deposition, unlike evaporation method, energetic ions are

bombarded on the target material. Due to this process, some atoms of
the target materials are released. These released \ atoms are then
condensed on the substrate. The sputtering deposition process is
applicable to any type of materials such as ‘ insulators, semiconductors,
metals or alloys. As compared to evaporation process, the sputtering
process is well controlled. This is carried at relatively high pressures like
1 Pa.

Metallization Applications:

 Gate and interconnection metallization controls the speed of the

circuit by controlling the resistance of the interconnection lines.
For high speed operation, such resistance should be as small as
possible.

 The gate and interconnection metallization also controls flat band

voltage VFB, which is essential to maintain a flat band condition in
the

 The contact metallization gives electrically and mechanically

stable ohmic contact having contact resistance negligibly small
compared to the device

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 The top level metal is thick as it carries current which provides

connection to the outside world.

The metallization is used to, produce rectifying contacts and diffusion

barriers between reacting metallic film

Deposition Methods

In the evaporation method, which is the simplest, a film is deposited by

the condensation of the vapour on the substrate. The substrate is
maintained at a lower temperature than that of the vapour. All metals
vaporize when heated to sufficiently high temperatures. Several
methods of heating are employed to attain these temperatures. For AI
deposition, resistive, inductive (RF), electron bombardment [electron-
gun] or laser heating can be employed. For refractory metals, electron-
gun is very common. Resistive heating provides low throughput.
Electron-gun cause radiation damage, but by heat treatment it can be
annealed out. This method is advantageous because the evaporations
take place at pressure considerably lower than sputtering pressure. This
makes the gas entrapment in the negligible. RF heating of the
evaporating source could prove to be the best compromise in providing
large throughput, clean environment, and minimal levels of radiation
damage.

In sputtering deposition method, the target material is bombarded by

energetic ions to release some atoms. These atoms are then condensed
on the substrate to form a film. Sputtering, unlike evaporation is very
well controlled and is generally applicable to all materials metals,
alloys, semiconductors and insulators. RF-dc and dc-magnetron
sputtering can be used for metal deposition. Alloy-film deposition by
sputtering from an alloy target is possible because the composition of
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the film is locked to the composition of the target. This is true even
when there is considerable difference between the sputtering rates of
the alloy components. Alloys can also be deposited with excellent
control of composition by use of individual component targets. In
certain cases, the compounds can be deposited by sputtering the metal
in a reactive environment. Thus gases such as methane, ammonia, or
nitrogen, and diborane can be used in the sputtering chamber to
deposit carbide, nitride, and boride, respectively. This technique is
called reactive sputtering. Sputtering is carried out at relatively high
pressures (0.1 to 1 pascal or Pa). Because gas ions are the bombarding
species, the films usually end up including small amount of gas. The
trapped gases cause stress changes. Sputtering is a physical process in
which the deposited film is also exposed to ion bombardment. Such ion
bombardment causes sputtering damage, which leads to unwanted
charges and internal electric fields that affect device proxies. However
such damages can be annealed out at relatively low temperatures
(<500°C), unless the damage is so severe as to cause an irreversible
breakdown of the gate dielectric.

Deposition Apparatus

The metallization is usually done in vacuum chambers. A mechanical

pump can reduce the pressure to about 10 to 0.1 Pa. Such pressure
may be sufficient for LPCVD. An oil-diffusion pump can bring the
pressure down to 10-5 Pa and with the help of a liquid nitrogen trap as
low as 10-7 Pa. A turbomolecular pump, can bring the pressure down to
10-8-10-9 Pa. Such pumps are oil-free and are useful HI molecular-beam
epitaxy where oil contamination must be avoided. Besides the pumping
system, pressure gauges and controls, residual gas analyzers,
temperature sensors, ability to clean the surface of the wafers by
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backsputtering, contamination control, and gas manifolds, and the use

of automation should be evaluated.

As typical high-vacuum evaporation apparatus is shown in the figure

below.

Metallization Process

The apparatus consists of a hell jar, a stainless-steel cylindrical vessel

closed at the top and sealed at the base by a gasket. Beginning at
atmospheric pressure the jar is evacuated by a roughing pump, such as
a mechanical rotary-van pump reducing pressure to about 20 Pa or a
combination mechanical pump and liquid-nitrogen-cooled molecular
pump (reducing pressure lo about 0.5 Pa). At the appropriate pressure,
the jar is opened to a high-vacuum pumping system that continues to

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reduce the pressure. The high-vacuum, pumping system may consist of

a liquid nitrogen-cooled trap and an oil-diffusion pump, a trap and a
turbomolecular pump, or a trap and a closed-cycle helium refrigerator
cryopump. The cryopump acts as a trap and must be regenerated
periodically, the turbomolecular and diffusion pumps act as transfer
pumps, expelling their gas t a forepump. The high vacuum pumping
system brings the jar to a low pressure that is tolerable for the
deposition process.

All components in the chamber are chemically cleaned and dried.

Freedom from sodium contamination is vital when coating MOS
devices.

The sputtering system operates with about 1 Pa of argon pressure

during film deposition. For sputtering, a throttle valve should be placed
between the trap and the high-vacuum pumping system. The argon gas
pressure can to be maintained by reducing the effective pumping speed
of the high-vacuum pump, while the full pumping speed of the trap for
water vapour is utilized. Water vapour and oxygen are detrimental to
film quality at background pressures of about 10-2 Pa.

The use of thickness monitors is common in evaporation and sputtering

deposition. This is necessary for controlling the thickness of the film,
because thinner film can cause excess current density and excessive
thickness can lead to difficulties in etching.

Metallization Patterning

Once the thin-film metallization has been done the film must be
patterned to produce the required interconnection and bonding pad
configuration. This is done by a photolithographic process of the same

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type that is used for producing patterns in Si02 layers. Aluminium can
be etched by a number of acid and base solutions including HCl, H 3PO4,
KOH, and NaOH. The most commonly used aluminium etchant is
phosphoric acid with the addition of small amounts of HN03 (nitric acid)
and acetic acid, to result a moderate etch rate of about 1 micro meter
per minute at 50°C. Plasma etching can also be used with aluminium.

Lift-off Process

The lift-off process is an alternative metallization patterning technique.

In this process a positive photoresist is spun on the wafer and
patterned using the standard photolithographic process. Then the
metallization thin film is deposited on top of the remaining photoresist.
The wafers are then immersed in suitable solvent such as acetone and
at the same time subjected to ultrasonic agitation. This causes swelling
and dissolution of the photoresist. As the photoresist comes off it lifts
off the metallization on top of it, for the lift-off process to work, the
metallization film thickness must generally be somewhat less than the
photoresist thickness. This process can, however produce a very fine
line-width metallization pattern, even with metallization thickness that
are greater than the line width.

Pattering for VLSI Applications

VLSI applications require anisotropic etching techniques for

metallization patterning because of the requirements of tight control
on metallization dimensions. Therefore dry-etching techniques are
most suitable. Reactive-ion etching (RIE) is anisotropic. Hence it is
preferred. For RIE, reactive gases such as, Cl2 and CCI3F are used, hence
the name reactive ion etching.

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WIRE BONDING

Wire bonding is the process of creating electrical interconnections

between semiconductors (or other integrated circuits) and silicon chips
using bonding wires, which are fine wires made of materials such as
gold and aluminium.

The two most common processes are gold ball bonding and aluminium
wedge bonding.

Gold wire bonding is achieved through thermosonic bonding. This

involves melting the end of the wire to form a gold ball, which is known
as a free-air ball. The diameter of the free-air ball measures 1.5 to 2.5
times the diameter of the wire. After being formed, the free-air ball is
placed into contact with the bond pad and pressure, heat and
ultrasonic forces are applied to it for a certain amount of time. This
forms a metallurgical weld between the ball and the bond pad while
also allowing deformation of the ball bond into its ending shape.

In the next step, the wire is run to a finger of the lead frame, which
forms an arc between the bond pad and the lead finger. A second bond,
called a wedge bond, is then formed through applying pressure and
ultrasonic forces to the wire using the lead finger. A machine called the
wirebonder then clamps the wire and raises the capillary in order to
break the wire to prepare for the next wirebonding.

Aluminium wedge wire bonding involves bringing a clamped aluminium

wire in contact with the aluminium bond pad. The wire is then held
down while ultrasonic energy is applied to it for a certain amount of
time, which forms the first wedge bond between the wire and bond
pad, before being pressed against the corresponding lead finger.

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Further application of ultrasonic energy to the wire forms the second

bond, before the wire is broken off by being clamped and moved.

Compared to aluminium wedge bonding, gold ball bonding is

significantly faster due to being non-directional, resulting in its
widespread use in plastic packaging. However, gold ball bonding on
aluminium bond pads cannot be used in hermetic packages due to the
high sealing temperatures used in such packages, as these
temperatures greatly accelerate the formation of gold-metal
intermetallics which can result in early life failures. Conversely, gold ball
bonding on gold bond pads can be utilised in hermetic packages.

Gold-aluminium ball bonding requires the use of heat to enable the

bonding process. Good bonding between the aluminium bond pad and
the gold ball bond - without causing damage to the wire, bond pad or
silicon substrate - through solely ultrasonic methods is impossible due
to the aluminium bond pad being harder than the gold ball bond. The
aluminium bond pads are softened through applying thermal energy to
them, which encourages the aluminium and gold atoms to inter-diffuse,
which forms the gold-aluminium bond. The application of thermal
energy also improves the bonding process by eliminating organic
contaminants on the surface of the bond pad.

Recent transitioning in the wire bonding industry has seen a preference

in copper over gold for use in the wire bonding process, the reason
being that the cost of gold is rising. Despite there being concerns that
copper is less reliable due to its hardness and susceptibility to
corrosion, copper wire can be used at smaller diameters while
performing identically to gold, making it more cost-effective.

Materials
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Bondwires usually consist of one of the following materials:

 Aluminum
 Copper
 Silver
 Gold

Wire diameters start at 15 μm and can be up to several hundred

micrometres for high-powered applications.

The wire bonding industry is transitioning from gold to copper. This

change has been instigated by the rising cost of gold and the
comparatively stable, and much lower, cost of copper. While possessing
higher thermal and electrical conductivity than gold, copper had
previously been seen as less reliable due to its hardness and
susceptibility to corrosion. By 2015, it is expected that more than a
third of all wire bonding machines in use will be set up for copper.

Copper wire has become one of the preferred materials for wire
bonding interconnects in many semiconductor and microelectronic
applications. Copper is used for fine wire ball bonding in sizes from
0.0004 inch (10 micrometres) up to 0.004 inch (100 micrometres).
Copper wire has the ability of being used at smaller diameters providing
the same performance as gold without the high material cost.

Copper wire up to 0.020 inch (500 micrometres) can be

successfully wedge bonded. Large diameter copper wire can and does
replace aluminum wire where high current carrying capacity is needed
or where there are problems with complex geometry. Annealing and
process steps used by manufacturers enhance the ability to use large

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diameter copper wire to wedge bond to silicon without damage

occurring to the die.

Copper wire does pose some challenges in that it is harder than both
gold and aluminum, so bonding parameters must be kept under tight
control. The formation of oxides is inherent with this material, so
storage and shelf life are issues that must be considered. Special
packaging is required in order to protect copper wire and achieve a
longer shelf life. Palladium coated copper wire is a common alternative
which has shown significant resistance to corrosion, albeit at a higher
hardness than pure copper and a greater price, though still less than
gold. During the fabrication of wire bonds, copper wire, as well as its
plated varieties, must be worked in the presence of forming gas [95%
nitrogen and 5% hydrogen] or a similar anoxic gas in order to prevent
corrosion. A method for coping with copper's relative hardness is the
use of high purity [5N+] varieties.

Pure gold wire doped with controlled amounts of beryllium and other
elements is normally used for ball bonding. This process brings together
the two materials that are to be bonded using heat, pressure
and ultrasonic energy referred to as thermosonic bonding. The most
common approach in thermosonic bonding is to ball-bond to the chip,
then stitch-bond to the substrate. Very tight controls during processing
enhance looping characteristics and eliminate sagging.

Junction size, bond strength and conductivity requirements typically

determine the most suitable wire size for a specific wire bonding
application. Typical manufacturers make gold wire in diameters from
0.0005 inch (12.5 micrometres) and larger. Production tolerance on
gold wire diameter is +/-3%.

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Alloyed aluminum wires are generally preferred to pure aluminum

wire except in high-current devices because of greater drawing ease to
fine sizes and higher pull-test strengths in finished devices. Pure
aluminum and 0.5% magnesium-aluminum are most commonly used in
sizes larger than 0.004 inch (101 micrometre).

All-aluminum systems in semiconductor fabrication eliminate the

"purple plague" (brittle gold-aluminum intermetallic compound)
sometimes associated with pure gold bonding wire. Aluminum is
particularly suitable for thermosonic bonding.

In order to assure that high quality bonds can be obtained at high

production speeds, special controls are used in the manufacture of
1% silicon-aluminum wire. One of the most important characteristics of
high grade bonding wire of this type is homogeneity of the alloy
system. Homogeneity is given special attention during the
manufacturing process. Microscopic checks of the alloy structure of
finished lots of 1% silicon-aluminum wire are performed routinely.
Processing also is carried out under conditions which yield the ultimate
in surface cleanliness and smooth finish and permits entirely snag-free
de-reeling.

Techniques of Attachment

The main classes of wire bonding:

 Ball bonding
 Wedge bonding
 Compliant bonding

Ball bonding usually is restricted to gold and copper wire and usually
requires heat. For wedge bonding, only gold wire requires heat. Wedge
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bonding can use large diameter wires or wire ribbons for power
electronics application. Ball bonding is limited to small diameter wires,
suitable for interconnect application.

In either type of wire bonding, the wire is attached at both ends using a
combination of downward pressure, ultrasonic energy, and in some
cases heat, to make a weld. Heat is used to make the metal softer. The
correct combination of temperature and ultrasonic energy is used in
order to maximize the reliability and strength of a wire bond. If heat
and ultrasonic energy is used, the process is called thermosonic
bonding.

In wedge bonding, the wire must be drawn in a straight line according

to the first bond. This slows down the process due to time needed for
tool alignment. Ball bonding, however, creates its first bond in a ball
shape with the wire sticking out at the top, having no directional
preference. Thus, the wire can be drawn in any direction, making it a
faster process.

Compliant bonding transmits heat and pressure through a compliant or

indentable aluminum tape and therefore is applicable in bonding gold
wires and the beam leads that have been electroformed to the silicon
integrated circuit (known as the beam leaded integrated circuit).

Semiconductor manufacturing and wire bonding

Semiconductors are manufactured using a precise process that includes

wire bonding, where electrodes on an integrated circuit are connected
to lead frames using soldered gold, aluminum and copper wires. These
wires can be as small as 10 µm in diameter and require a soldering
accuracy as small as 2 to 3 µm. The level of precision necessary to

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solder the wires means that tiny vibrations can cause weak bonding,
which, in turn, can cause the electronic device to fail.

Manufacturers inspect semiconductor wire bonding for flaws such as

disconnected wires, shifts in wire pitch, bonding separation, or peeling
and migration. Since semiconductors are manufactured in large
quantities, they are typically inspected by high-speed, automated
equipment that provides a “pass/fail” result for each chip.
Semiconductors that fail are pulled off the line and examined in detail
by the quality control department using a light or digital microscope.

Challenges when inspecting bonded wires

The bonded wires are in a loop configuration rather than a straight

configuration, making inspection using conventional or digital
microscopes difficult. As such, there are three main challenges that
inspectors face. During the first phase of the inspection, users will
check the wires under low magnification so that they can observe the
entire wire at once. However, most low-magnification objectives lack
the resolution necessary to deliver very sharp images, making some
bonding failures challenging to spot.

A second challenge is the difficulty of bringing the entire wire into focus
under low magnification due to the wire’s shape. Even with a digital
microscope that offers a good depth of focus when using high-
magnification lenses, the resolution is usually not adequate for
analyzing very small failures in bonding wires.

Lastly, if a problem is identified under low magnification, an inspector

using an optical microscope may have to switch to a high-magnification
microscope or change lenses to conduct a more detailed observation.

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However, this changeover takes time as the area of interest needs to be

reacquired. If the inspector is using a digital microscope, the procedure
for changing to a higher magnification depends on the system. Some
digital microscopes only have one zoom objective lens. In this case, the
low-magnification lens needs to be removed from the microscope body
and a new one needs to take its place.

Advantages of inspecting bonded wires using the DSX1000 digital

microscope

The DSX1000 microscope offers features that solve each of the

inspection challenges discussed above. The microscope’s lenses use
Olympus’ advanced optical technology to deliver both an excellent
depth of focus and high resolution under low and high magnification.
This feature makes it easier to spot smaller defects while having the
entire wire in focus. If an even greater depth of focus is required than
what the objectives provide, the Focus Depth Up function enables users
to increase the focal depth with the push of a button.

The microscope also makes changing from low to high magnification

simple. The quick-change lenses slide in and out of the microscope
body, so exchanging them is fast and easy. Likewise, because the lens
position remains fixed, users do not have to spend time reacquiring the
area of interest. For more information, visit Olympus’ website.

Thin Film Deposition and Characterization Techniques

Fabrication of copper indium diselenide thin film (CIS) solar cells

requires excellent structural, optical and electrical properties of various
semiconductor layers. This chapter discusses the thin film deposition
methods used in this study for the growth of different semiconductor

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materials. The techniques used to investigate the structural features of

the thin films viz. X-ray diffraction (XRD), Scanning electron microscopy
(SEM), Transmission electron microscopy (TEM), and Atomic force
microscopy (AFM). The optical characterization technique utilized to
study the transmission of the grown semiconductor thin films. Electrical
measurements of semiconductor thin films are carried out using hot
probe method, four point probe method, and Hall effect.

Thin Film Deposition Techniques

In this, section evaporation and sputtering are focused, two of the most
important methods used for depositing thin films. The objective of
these deposition processes is, controllably transfer atoms from a source
to a substrate where film formation and growth proceed atomistically.
Experimental techniques used to deposit various thin film
semiconducting layer in CIS thin film solar cell and their
characterization techniques are discussed here.

1. Thermal Evaporation Method

A typical thermal evaporation system is schematically shown in figure

2.1. The system consists of an evaporation source that vaporizes the
desired material and a substrate is located at an appropriate distance
facing the evaporation source. Both the source and the substrate are
located in a vacuum chamber. The substrate can be heated or
electrically biased or rotated during deposition. The desired vapor
pressure of source material can be generated by simply heating the
source to elevated temperatures, and the concentration of the growth
species in the gas phase can be easily controlled by varying the source
temperature. The substrate temperature during the thin film
deposition is measured using chromel-alumel thermocouple kept in
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good thermal contact with the substrate. The rate of deposition and
thicknesses of the films are continuously monitored during the film
deposition using a quartz crystal thickness monitor DTM -101 (Hind Hi
Vac., India). In order to improve crystallinity the evaporated thin films
are deposited at different substrate temperatures (Ts).

Figure 2.1: A schematic of the thermal evaporation system

2. Flash Evaporation Method

Flash evaporation technique is widely used by researchers to deposit

binary/ternary semiconductor compound material owing to its
simplicity and ease of operation. The schematic off lash system
installed in vacuum coating unit is shown in figure 2.2. The system
consists of a evaporation source and an electromagnetically vibrating
feeder known as flash system, which supplies the powder material to
the boat. Fine grains of pulverized material are fed into the preheated
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evaporation source kept at temperature higher than evaporation

temperature of material via vibratory feeder. This result in uniform film
deposition on substrates kept at different Ts.

Figure 2.2 The Flash evaporation system installed in vacuum coating unit

3. Sputtering Technique

Sputtering is one of the most versatile deposition techniques used for

the deposition of transparent conducting oxides (TCO). When
sputtering is compared to other techniques, sputtering produces films
with higher purity and better-controlled composition. It also produces
films with greater adhesive strength, homogeneity and permits better
control of film thickness. Sputtering processes involves the creation of
gas plasmas (usually an inert gas such as argon) between an anode and
cathode. The cathode is used as the source of sputtered particles

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whereas the anode is usually the substrate holder. The source material
is subjected to intense bombardment by ions. Using the momentum
transferred from the bombarding ions, particles are ejected from the
surface of the source (cathode) and then diffuse away from it,
depositing a thin film onto the substrate. Sputtering is usually
performed at pressures of 10-2- 10-3 Torr.

In standard sputtering processes there are usually two modes of

powering the sputtering system. These two modes are direct current
(DC) or by radio frequency (RF). In DC sputtering, a direct voltage is
applied between the cathode and the anode. This method works well
with conductive targets (molybdenum, silver, aluminum, etc). The
second method involves the use of a radio frequency source with a
typical frequency of 13.56 MHz. This method is referred for both
conductive as well as non-conductive targets. However, with the ever
increasing demand for increased sputter rates it is found that the
application of magnets above the target increased the sputtering rate
and decreased the unintentional substrate heating. Generally this
method is known as RF magnetron sputtering. The schematic diagram
of RF magnetron sputtering is shown in figure 2.3. The system consists
of, a RF generator, a matching unit, the vacuum coating unit, and the
gas inlet system. Each part plays a specific role in the sputter process as
outlined below.

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Figure 2.3: A Schematic showing the principle of RF sputtering system.

 RF generator: A Huttinger (Germany) PFG 600 RF generator with a

maximum output of 600 W is used to deposit the Mo and ZnO
thin films. The RF generator creates a dense glow discharge
(plasma) due to bias potential built up on the target surface. The
negative bias potential of the target results in the ion
bombardment, i.e., sputtering of the target.
 Matching unit: A matching unit is connected with the magnetron
unit, which is kept inside the vacuum chamber. To achieve an
efficient energy transfer from the RF generator at a nominal load

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of approximately 50 £2, the matching unit is kept closer to the

chamber.
 Vacuum coating unit; A high vacuum coating unit (Model; 15F6
from Hind High Vacuum Co. (P) Ltd.) equipped with water cooled
target holder (cathode electrode), adjustable substrate holder and
accessory. There are two pumps, a rotary pump and a diffusion pump to
achieve a base pressure of 10'5 Torr.
 Gas inlet system: Combination of rotameter and needle valve is used to
control the flow of the argon gas used for the sputtering process.

Thin Film Characterization Techniques

A wide variety of characterization techniques are used to evaluate the

material quality of the semiconductor thin films. The structural
properties of the polycrystalline films are studied by scanning electron
microscopy (SEM) and atomic force microscopy (AFM) in non-contact
mode while the presence of crystalline phases by X-ray diffraction
(XRD) and transmission electron microscopy (TEM). Composition
measurements are made by energy dispersive analysis of X-rays (EDAX)
equipped with SEM. The electrical properties of the materials are
investigated by Four-point probe and Hall Effect measurements. The
optical properties of the films are studied using transmission
measurements.

 X-Ray Diffraction (XRD)

X-ray diffraction (XRD) is a very powerful experimental technique for

studying crystal structures of solids and thin films. The preferred
orientation of crystallites grown in semiconducting thin-film samples
used for CIS solar cell fabrication viz. CIS, CdS and ZnO is obtained from
XRD analysis.

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In XRD analysis, a collimated beam of X-rays, with a wavelength

typically ranging from 0.7 to 2 , is incident on a specimen and is
diffracted by the crystalline phases in the specimen according to
Bragg’s law:

(2.1)

where d is the spacing between atomic planes in the crystalline phase

and X is the X-ray wavelength. The intensity of the diffracted X-rays is
measured as a function of the diffraction angle θ. This diffraction
pattern is used to identify the crystalline phases present in thin films.

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Figure 2.4: Shimazdu Lab X 6000 X- ray diffractometer.

X-ray diffraction (XRD) relies on the dual wave/particle nature of X-rays to obtain
information about the structure of crystalline materials. A primary use of the
technique is the identification and characterization of compounds based on their
diffraction pattern.

The dominant effect that occurs when an incident beam of monochromatic X-rays
interacts with a target material is scattering of those X-rays from atoms within the
target material. In materials with regular structure (i.e. crystalline), the scattered
X-rays undergo constructive and destructive interference. This is the process of
diffraction. The diffraction of X-rays by crystals is described by Bragg’s Law,
n(lambda) = 2d sin(theta). The directions of possible diffractions depend on the
size and shape of the unit cell of the material. The intensities of the diffracted
waves depend on the kind and arrangement of atoms in the crystal structure.
However, most materials are not single crystals, but are composed of many tiny
crystallites in all possible orientations called a polycrystalline aggregate or
powder. When a powder with randomly oriented crystallites is placed in an X-ray
beam, the beam will see all possible interatomic planes. If the experimental angle

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is systematically changed, all possible diffraction peaks from the powder will be
detected.

The parafocusing (or Bragg-Brentano) diffractometer is the most common

geometry for diffraction instruments.

This geometry offers the advantages of high resolution and high beam intensity
analysis at the cost of very precise alignment requirements and carefully prepared
samples. Additionally, this geometry requires that the source-to-sample distance
be constant and equal to the sample-to-detector distance. Alignment errors often
lead to difficulties in phase identification and improper quantification. A mis-
positioned sample can lead to unacceptable specimen displacement errors.
Sample flatness, roughness, and positioning constraints preclude in-line sample
measurement. Additionally, traditional XRD systems are often based on bulky
equipment with high power requirements as well as employing high powered X-
ray sources to increase X-ray flux on the sample, therefore increasing the
detected diffraction signals from the sample. These sources also have large
excitation areas, which are often disadvantageous for the diffraction analysis of
small samples or small sample features.

Polycapillary X-ray optics can be used to overcome many of these drawbacks and
constraints to enhance XRD applications. Polycapillary collimating optics convert a
highly divergent beam into a quasi-parallel beam with low divergence. They can
be used to form a Parallel Beam XRD instrument geometry which greatly reduces
and removes many sources of errors in peak position and intensity inherent to the
parafocusing geometry, such as sample position, shape, roughness, flatness, and
transparency. Polycapillary focusing optics collect X-rays from a divergent X-ray
source and direct them to a small focused beam at the sample surface with
diameters as small as tens of micrometers for micro X-ray diffraction applications
of small samples or small specimen features. Both types of polycapillary optics
direct very high X-ray intensities to the sample surface, such that XRD systems
employing optics can use low power X-ray sources, reducing instrument size, cost,
and power requirements.

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X-ray diffraction using X-ray optics has been applied to many different types of
applications including thin film analysis, sample texture evaluation, monitoring of
crystalline phase and structure, and investigation of sample stress and strain.

 Scanning Electron Microscopy (SEM)

The morphological and compositional characterization of the

semiconducting thin films in this work are carried out using scanning
electron microscope ESEM, 30XL, Philips make, equipped with energy
dispersive analysis of x-rays (EDAX) facilities operated at 30 keV with
standardless ZAF quantification.

A schematic representation of a typical SEM is shown in figure 2.5.

Electrons emitted from an electron gun pass through a series of lenses
to be focused and scanned across the sample. Electron beams having
energies ranging from 0.5 keV to 30 keV, is focused by one or two
condenser lenses. The beam then passes through pairs of scanning coils
or pairs of deflector plates in the electron column, typically in the final
lens.

When the electron beam interacts with the sample, the electrons lose
energy by repeated random scattering and absorption. The energy
exchange between the electron beam and the sample results in the
reflection of high-energy electrons by elastic scattering, emission of
secondary electrons by inelastic scattering and the emission of
electromagnetic radiation, each of which can be detected by detectors.
The beam current absorbed by the specimen can also be detected and
used to create images of the distribution of specimen current.
Electronic amplifiers of various types are used to amplify the signals,
which are displayed as variations in brightness on a cathode ray tube
(CRT). The raster scanning of the CRT display is synchronized with that

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of the beam on the specimen in the microscope, and the resulting

image is therefore a distribution map of the intensity of the signal being
emitted from the scanned area of the specimen. The image can be
digitally captured and displayed on a computer monitor and saved to a
computer's hard disk.

 Energy Dispersive Analysis of X-rays (EDAX)

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Figure 2.5: Schematic representation of scanning electron microscope.

The first technique, the energy dispersive spectrometry, is known as

EDS or EDAX, while the second approach is called wavelength dispersive
spectrometry (WDS or WDX). We have used EDAX for compositional
analysis of CIS and CdS thin films.

 Transmission Electron Microscopy (TEM)

Transmission electron microscope (TEM) is, in principle, similar to

optical microscopes; both contain a series of lenses to magnify the
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surface of the test sample. Transmission electron microscopy is

originally used for higher magnification. Later, analytical capabilities
such as electron energy loss detectors and X-ray detectors are added to
the instrument and the - technique is now also known as stands for
either “microscopy” or “microscope.”

A schematic of a transmission electron microscope is shown in figure

2.6. Electrons from an electron gun are accelerated to high voltages-
focused on the sample by the condenser lenses. The sample is placed
on a small copper grid, a few mm in diameter. The static beam has a
diameter of a few microns. The sample must be sufficiently thin (a few
tens to a few hundred nm) to be transparent to electrons. The
transmitted and forward scattered electrons form a diffraction pattern
in the back focal plane and a magnified image in the image plane. With
additional lenses, either the image or the diffraction pattern is
projected onto a fluorescent screen for viewing or electronic or
photographic recording. The ability to form a diffraction pattern yields
structural information.

Selected area (electron) diffraction (abbreviated as SAD or SAED), is a

crystallographic experimental technique that can be performed inside a
transmission electron microscope (TEM). SAD pattern of CIS and CdS
thin films are obtained in this study using the JEOL make TEM, JEM-
2100. To obtain SAD pattern the wavelength of high-energy electrons is
incident on very thin, -50-100 nm, semiconducting film. The atoms in
the film act as a diffraction grating to the electrons, which are
diffracted. That is, some fraction of them will be scattered to particular
angles, determined by the crystal structure of the sample, while others
continue to pass through the sample without deflection. As a result, the
image on the screen of the TEM will be a series of spots known as the
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selected area diffraction pattern, (SAD) shown in figure 3.6 and 4.3.
Here, each spot corresponds to a satisfied diffraction condition ofthe
sample's crystal structure.

 Atomic Force Microscopy (AFM)

Atomic force microscope is a versatile tool to investigate the

morphology and growth structure of the thin films. We have
investigated the surface morphology of semiconducting thin films using
atomic force microscope CP n research head, Veeco (USA) make, in non
contact mode.

thick. The vertical sensitivity of cantilever depends on its length, which

can be sensed by one or several methods [79]. The cantilever motion
causes the reflected light to impinge on different segments of the
photodiode.

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Figure 2.6: Schematic representation of transmission electron microscope.

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Figure 2.7: Schematic illustration of atomic force microscope.

Cantilevers come in two common shapes as shown in figure 2.8. The

three common modes of operation of AFMs are, 1) Contact mode, 2)
Non- contact mode, and 3) Tapping mode.

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Figure 2.8: AFM cantilevers (a) V-Shaped type (b) Beam type.

In the contact mode, the probe tip is dragged across the surface and
the resulting image is a topographical map of the sample surface. The
dragging motion ot the probe lip, combined with adhesive forces
between the tip and the surface can distort measurement data and
damage the sample. In the non-contact mode, the instrument senses
Van-der Waal attractive forces between the surface and the probe tip
held above the sample surface. Unfortunately, these forces are
substantially weaker than the contact mode forces, so weak in fact that
the tip must be given a small oscillation and ac detection methods are
used to detect the small forces between tip and sample. Non-contact
mode provides lower resolution than either contact or tapping mode.
Tapping mode imaging overcomes the limitations of the conventional
scanning modes by alternately placing the tip in contact with the
surface to provide high resolution and then lifting the tip off the surface
to avoid dragging the tip across the surface [80]. During scanning, the
vertically oscillating tip alternately contacts the surface and lifts off,
generally at a frequency of 50 to 500 kHz. Tapping mode imaging works
well for soft, adhesive, or fragile samples, allowing high resolution
topographic imaging of sample surfaces that are easily damaged or
otherwise difficult to image by other AFM techniques.

 Optical Transmission Measurements

The optical transmission of various semiconducting thin films, viz. CIS,

CdS and AZO is used to determine the energy band gap of the material.
During transmission measurements light is incident on the sample and
the transmitted light is measured as a function of wavelength. The
transmitted light, It, can be measured absolutely or the ratio of

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transmitted to incident light, lo. The absorption coefficient is

determined using Lambert’s law [81],

Here, a Tungsten-Halogen lamp is used as a polychromatic light source.

The light from the lamp is focused on the monochromator input slit
using a convex lens. We have used l/8m monochromator (CM110). The
output beam from the monochromator is chopped using a mechanical
chopper. This chopped beam is then incident on the sample near-
normal geometry and the transmitted beam is directed to the photo-
detector. The detector measures the intensity of the transmitted beam
with the help of lock-in amplifier (SR-530). The monochromator and the
lock-in amplifier have been interfaced with the computer using COM
port and GPEB, respectively. The experiment is automated using Lab
VIEW.

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Figure 2.9: Set up for transmission measurements.

Electrical Measurements

1. Hot-Probe Method

The semiconductor conductivity can be determined using hot probe

method. The schematic diagram for hot probe measurement is shown
in figure 2.10.

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Figure 2.10: Schematic diagram of hot probe method.

In the hot or thermoelectric probe method the conductivity type is

determined by the sign of the thermal emf or Seebeck voltage
generated by a temperature gradient. Two probes contact the sample
surface: one is hot the other is cold. Electrons diffuse from the hot to
the cold region setting up an electric field that opposes the diffusion.
The electric field produces a potential detected by the voltmeter with
the hot probe positive with respect to the cold probe.

2. Four-point Probe Method

The four-point probe is commonly used technique to measure the

semiconductor resistivity. It is an absolute measurement without
recourse to calibrated standards and is sometimes used to provide
standards for other resistivity measurements. The schematic diagram of
four-point probe measurement technique is shown in figure 2.11. It is
seen that by applying current I between terminal 1 and 4 (outer
terminals in the figure) and measuring voltage V across terminal 2 and 3
(inner terminals) one can calculate sheet resistance (RSh) of the film
using following equation.

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Figure 2.11: Schematic diagram of four point probe method.

3. Hall Effect Measurement

The Hall effect measurement technique has found wide application in

the characterization of semiconductor materials because it gives the
resistivity, the carrier density, and the carrier mobility. A detailed
discussion of the Hall effect and its application to mobility
measurements is given in [82] and explained the next paragraphs.

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Consider the p-type semiconductor sample in figure 2.12. A current I

flows in the Xdirection, indicated by the holes flowing to the right and a
magnetic field B is applied in the Z-direction. The current is given by,

The magnetic field in conjunction with the current deflects some holes
to the bottom of the sample, as indicated in figure 2.12. For n-type
samples, the electrons are also deflected to the bottom of the sample

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for t he same current direction as that in figure 2.12 because they flow
in the opposite direction to holes and have opposite charge. In the y-
direction there is no net force on the holes since no current can flow in
that direction and Fy = 0. Combining equations (2.8) and (2.5) gives,

Conclusions

This chapter outlines the thin film deposition methods used to deposit
various semiconducting thin films for thin film CIS solar cell device
fabrication. The structural, morphological, characterization methods of
thin films viz. XRD, TEM, SEM, AFM, are discussed in this chapter.

Thin and Thick Film ICs

These devices are larger than monolithic ICs but smaller than discrete
circuits. These ICs can be used when power requirement is
comparatively higher. With a thin- or thick-film IC, the passive
components like resistors and capacitors are integrated, but the
transistors and diodes are connected as discrete components to form a
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complete circuit. Therefore, commercially available thin- and thick-film

circuits are combination of integrated and discrete components.

The essential difference between the thin- and thick-film ICs is not their
relative thickness but the method of deposition of film. Both have
similar appearance, properties and general characteristics.

Thin-film ICs

Thin-film ICs are fabricated by depositing films of conducting material

on the surface of a glass or ceramic base. By controlling the width and
thickness of the films and by using different materials selected for their
resistivity, resistors and conductors are fabricated. Capacitors are
produced by sandwiching a film of insulting oxide between two
conducting films. Inductors are made by depositing a spiral formation
of film. Transistors and diodes can be produced by thin-film technology;
but usually tiny discrete components are connected into the circuit.

One method used for producing thin films is vacuum evaporation in

which vapourized material is deposited on a substrate contained in a
vacuum. In other method, called cathode sputtering, atoms from a
cathode made of the desired film material are deposited on a substrate
located between a cathode and an anode.

Thick-film ICs

Thick-film ICs are sometimes referred to as printed thin-film circuits. In

their manufacturing process silk-screen printing techniques are used to
create the desired circuits pattern on a ceramic substrate. The screens
are actually made of fine stainless steel wire mesh, and the inks are
pastes having conductive, resistive, or dielectric properties. After
printing, the circuits are high temperature-fired in a furnace to fuse the
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films to the substrate. Thick-film passive components are fabricated in

the same way as those in thin-film circuits. As with thin-film circuits,
active components are added as separate devices. A portion of thick-
film circuit is given in fig 1.

Fig 1

ICs produced by thin- or thick-film techniques have the advantages of

forming passive components with wider range and better tolerances,
better isolation between their components, greater flexibility in circuit
design and of providing better high-frequency performance than
monolithic ICs.

However, such ICs suffer from the drawbacks of larger physical size,
comparatively higher cost and incapability of fabrication of active
components.

MOS Technologies

A microprocessor design company started by some ex-Motorola

designers, shortly after the Intel 8080 and Motorola 6800 appeared, in
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about 1975. MOS Technologies introduced the 650x series, based on

the Motorola 6800 design, though they were not exact clones for legal
reasons.

The design goal was a low-cost (smaler chip) design, realized by

simplifying the decoder stage. There were no instructions with the
value xxxxxx11, reducing the 1-of-4 decoder to a single NAND gate.
Instructions with the value xxxxxx11 actually executed two instructions
in paralell, some of them useful.

The 6501 was pin-compatible with the 6800 for easier market
penetration. The 650x-series had an on-chip clock oscillator while the
651x-series had none.

The 6510 was used in the Commodore 64, released September 1981
and MOS made almost all the ICs for Commodore's pocket calculators.

The PET was an idea of the of the 6500 developers. It was completly
developed by MOS, but was manufactured and marketed by
Commodore. By the time the it was ready for production (and
Commodore had cancelled all orders) MOS had been taken over by
Rockwell (Commodore's parent company). Just at this time the 6522
(VIA) was finished, but the data sheet for it was not and its developers
had left MOS. For years, Rockwell didn't know in detail how the VIA
worked.

MOS Technology, 1963-1974: A Dozen Crucial Years

A line can be drawn from the Frosch’s and Derick’s work on silicon
dioxide to the MOS (metaloxide-semiconductor) transistor’s dominance
of semiconductor technology, but it is neither short nor straight. That
line has several discernable segments, first from Frosch and Derick’s
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work, until 1963. In this interval, by and large, no one thought seriously
about a metal-oxide-semiconductor as a viable technology in its own
right. The second segment runs from 1963, when the combination of
integrated circuits and the planar manufacturing process had led
people to see MOS transistors as a potentially promising semiconductor
technology, until the mid-1970s, at which point the MOS transistor had
been established as a commercially successful and sustainable
technology. This article will detail that second segment, concentrating
on work done by Fairchild Semiconductor Corporation and IBM, and
will show that three types of work were crucial during this period: first,
research on the chemistry and physics of MOS structures; second,
product design and development to create integrated circuits that had
some advantages over bipolar technologies; and third, organizational
change to create environments where MOS technology could thrive.

Early Research at Fairchild

In its earliest years, Fairchild had put a lot of time and effort into
studying the surfaces of bipolar transistors, but the first sustained work
on the MOS transistor as a potential product came from Frank Wanlass,
who joined Fairchild in August 1962 after earning a PhD in physics from
the University of Utah. In a period of remarkable creativity stretching
until his departure for the start-up General Microelectronics in
December 1963, Wanlass explored the chemistry and physics of MOS
structures, built MOS integrated circuits, and considered how various
MOS phenomena could be commercially exploited. Wanlass’s greatest
technological contribution was the invention of CMOS (complementary
MOS), which led to transistor circuits that consumed almost no power
in standby operation (see Figs. 1 and 2). While the complexities of
building CMOS circuits were so great in the 1960s that most firms
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concentrated on making p-channel MOS circuits his CMOS circuitry and

the low power consumption it allows has been one of the technical
foundations of MOS’s dominance over the last three decades. Wanlass,
who often worked at the very edge of what was possible, seldom
published and bounced around among marginally successful MOS
companies, and is one of the vastly under-recognized figures in the
history of MOS technology.

After Wanlass’s MOS transistor work in early 1963, Gordon Moore,

then director of research and development at Fairchild, and C. T. Sah,
the manager of the solid-state physics department, began putting
together a team to understand the MOS structure and the silicon-
silicon dioxide system in a systematic way. Moore’s main reason for
starting this team was to produce better bipolar transistors—Fairchild’s
main area of business. But this work would also be expected to address
the stability problems of MOS transistors. Up to this time, the problems
of MOS stability were so great—an MOS transistor’s characteristics
might vary by over a hundred volts over time or with changes in
temperature and operating conditions—that they made MOS
transistors useless as a product. If these problems could be solved,
MOS transistors would be technically viable. The first member of the
group was Bruce Deal, who came to Fairchild in March 1963 with a PhD
in chemistry from Iowa State University and many years researching
oxidation processes. Andrew Grove joined later that spring after
receiving his PhD in chemical engineering from UC Berkeley, where he
had worked on fluid mechanics. Ed Snow came later that year from the
University of Utah, where he had earned a PhD in solid-state physics
based on the migration of ions in quartz.

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In October 1963 this Fairchild group made a breakthrough discovery.

Snow began a project assuming that different metals applied as a gate
electrode over the silicon-dioxide layer might show different levels of
stability. Researchers typically evaporated aluminum onto the silicon
dioxide using a tungsten filament, but because of the extremely high
melting points of platinum and tantalum, Snow instead used an
electron-beam evaporator to apply these metals. As he examined the
stability of these platinum and tantalum structures, Snow found they
were more stable than

The MOS transistor

The most basic element in the design of a large scale integrated circuit
is the transistor. For the processes we will discuss, the type of transistor
available is the Metal-Oxide-Semiconductor Field Effect Transistor
(MOSFET). These transistors are formed as a ``sandwich'' consisting of a
semiconductor layer, usually a slice, or wafer, from a single crystal of
silicon; a layer of silicon dioxide (the oxide) and a layer of metal. These
layers are patterned in a manner which permits transistors to be
formed in the semiconductor material (the ``substrate''); a diagram
showing a typical (idealized) MOSFET is shown in Figure . Silicon dioxide
is a very good insulator, so a very thin layer, typically only a few
hundred molecules thick, is required. Actually, the transistors which we
will use do not use metal for their gate regions, but instead use
polycrystalline silicon (poly). Polysilicon gate FET's have replaced
virtually all of the older devices using metal gates in large scale
integrated circuits. (Both metal and polysilicon FET's are sometimes
referred to as IGFET's --- insulated gate field effect transistors, since the
silicon dioxide under the gate is an insulator. We will still continue to
use the term MOSFET to refer to polysilicon gate FET's.)
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Figure: 1.1 MOS Transistor

The transistor consists of three regions, labeled the ``source'', the

``gate'' and the ``drain''. The area labeled as the gate region is actually a
``sandwich'' consisting of the underlying substrate material, which is a
single crystal of semiconductor material (usually silicon); a thin
insulating layer (usually silicon dioxide); and an upper metal layer.
Electrical charge, or current, can flow from the source to the drain
depending on the charge applied to the gate region. The semiconductor
material in the source and drain region are ``doped'' with a different
type of material than in the region under the gate, so an NPN or PNP
type structure exists between the source and drain region of a MOSFET.
Figure 1.1 shows a cross section of both types of MOSFET. In Figure 1.1
(a), the source and drain regions are doped with N type material and
the substrate doped with P type material. Such a transistor is called an
N channel MOSFET. If they were doped with P type material, and the
substrate doped with N type material as in Figure 1.1 (b), the device
would be called a P channel MOSFET.

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Figure: 1.1(a) N channel MOSFET Figure: 1.1(b) P channel MOSFET

The source and drain regions are quite similar, and are labeled
depending on to what they are connected. The source is the terminal,
or node, which acts as the source of charge carriers; charge carriers
leave the source and travel to the drain. In the case of an N channel
MOSFET, the source is the more negative of the terminals; in the case
of a P channel device, it is the more positive of the terminals. The area
under the gate oxide is called the ``channel''.

The MOSFET can operate as a very efficient switch for current flowing
between the source and drain region of the device. For the simplest
type of MOSFET, the ``enhancement mode MOSFET'', which acts as a
``normally open'' switch, the operation of the device can be described
qualitatively with reference to Figure.1.3

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Figure 1.3 (a) shows an N-channel MOSFET with the source and drain
connected to power (VDS) and ground (VSS); the substrate, or body of
the device, is also connected to ground. In this case, there is a reverse
biased PN junction between at least one of the N wells and the
substrate, so no current can flow through the substrate. In particular,
there will be no current flow in the channel region under the gate of
the transistor, and therefore no current will flow between the source
and drain of the device. Under these conditions, the MOSFET is turned
off.

Figure1.3 (b) shows the same N-channel MOSFET with a positive charge
applied to the gate of the device. Under these circumstances, if the
gate is given a sufficiently large charge, negative charge carriers
(electrons) will be attracted from the bulk of the substrate material into
the channel region immediately below the oxide under the gate. When
more electrons are attracted into this region than there are positive
charge carriers (holes) in the channel, then the channel effectively
behaves as an N type region, and current can flow between the source

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and the drain. When this happens, the MOSFET is turned on. Note that
a certain minimum charge must be applied to the gate to overcome the
excess of holes already in the channel region because of the P type
doping in the substrate. This means that the switch is not turned on
immediately, rather there must be some minimum amount of charge
applied to the gate before the transistor is switched on. The voltage
which must be applied to the gate before the transistor allows current
to flow between the source and drain is called the ``threshold voltage'',
designated as Vth.

This type of transistor is called an N channel enhancement mode

MOSFET. (It is called N channel because the conduction in the channel
is due to N type charge carriers; it is said to be an ``enhancement
mode'' device because the channel conduction is enhanced by a charge
applied to the gate.) Figure1.4 shows a set of typical characteristic
curve for the current IDS between the drain and source of a MOSFET as
a function of the voltage VDS for a range of gate voltages, VGS.

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A second type of MOSFET can also be constructed; this type of device is

commonly used in purely NMOS designs, but is not used in CMOS
designs. (Presently, we only have access to CMOS processes.) This type
of MOSFET, the ``depletion mode MOSFET'', acts as a ``normally closed''
switch. Its behavior can qualitatively be explained with reference to
Figure 1.5 which shows an N channel depletion mode MOSFET.

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In the depletion mode MOSFET, a thin layer of semiconductor material

immediately beneath the gate oxide is permanently doped with the
same type material as the source and drain regions (but different from
the bulk of the substrate semiconductor material). This thin layer allows
conduction to occur in the channel region when no charge is applied to
the gate. If a negative charge is applied to the gate, then the negative
charge carriers in the thin N-doped region immediately beneath the
gate oxide will be repelled from this region, leaving no free charge
carriers, and conduction will cease. In the depletion mode MOSFET, a
charge (with the same polarity as the drain dopant) applied to the gate
turns the transistor off.

Depletion mode MOSFETs find their most common use not as switches
but as resistors. As a permanently ``on'' transistor, the device has a high
resistance compared with the doped semiconductor material itself, and
the resistance is readily variable by modifying the size of the transistor.
(At fabrication time, the resistance can be modified by varying the
number of ions which are implanted in the gate region of the device).
The commonly used circuit symbols for Nand P- channel enhancement
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and depletion mode MOSFETs are shown in Figure 1.6. Figure 1.6 (a)
shows the commonly used circuit symbols for P- and N- channel
enhancement mode MOSFETs; the corresponding circuit symbols for
depletion mode devices are shown in Figure 1.6 (b).

Enhancement mode

Depletion mode

(a) N-Channel (b) P-Channel

Figure: 1.6 N- and P- channel enhancement and depletion mode MOSFETs

Both enhancement and depletion mode transistors are used in many of

today's microelectronic circuits. The most popular circuit technology
using both enhancement and depletion mode devices is the
conventional NMOS technology. In this technology, depletion mode
transistors are mainly as resistors, and enhancement mode transistors
are used as switches. Figure 1.7 shows a typical inverter implemented
in this technology, together with its switch equivalent. Also shown is a
plot of the output of a typical example of such an inverter for a given
input pulse. (The input pulse has a rise and fall time of 0.5 ns.)
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The gate of the depletion mode transistor is connected to its drain, to

keep the transistor permanently turned on. The depletion mode
transistor is used as a ``pull-up'' resistor, and the enhancement mode
transistor is used as a switch to ``pull down'' the output when the
switch is turned on. Note that in this technology, the resistance of the
permanently turned on depletion mode transistor must be large
compared with the ``on'' resistance of the enhancement mode
transistor, but small compared with the ``off'' resistance of the
transistor. This type of logic is often called a ``ratioed logic'', since the
ratio of the pull-up resistance to the pull-down resistance effectively
determines the voltage at which the output of the device changes
state. Typically, Rph  4Rpd. The large resistive pull-up transistor causes
three particular problems with this technology:

1. The depletion mode transistor must be made large (i.e., long

and thin) to create the large ``on'' resistance.

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2. When driving a capacitive output load such as the gate of

another transistor, the charging time (proportional to RdepC )
will be long compared to the discharging time (proportional
to RenhC). This effect is clearly evident in Figure 1.7 (c).
3. The device consumes DC power whenever the enhancement
mode pull down device is turned on, due to the resistive
losses in the pull-up transistor.

The third problem becomes more serious as feature sizes for transistors
decrease, because the number of such resistors per unit area increases,
and the devices may well, resulting in device failure due to overheating.

VLSI

The full form of VLSI is Very Large Scale Integration. By incorporating

thousands of transistors into a single chip, VLSI is the process by which
integrated circuits (ICs) are produced.

 Before the introduction of VLSI technology, most circuits

restricted the range of functions they can handle.
 A ROM, CPU, RAM and other glue logic might comprise an
electrical circuit.
 VLSI allows all of that to be added into one chip by IC designers.
 It’s used on a single mini-silicon chip to build so many chips &
circuits.
 VLSI started when complicated semiconductor & communication
techniques were developed in the 1970s.
 VLSI computer is a microprocessor.

VLSI Technology

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Fig. 1: A Representational Image Of VLSI Technology

Gone are the days when huge computers made of vacuum tubes sat
humming in entire dedicated rooms and could do about 360
multiplications of 10 digit numbers in a second. Though they were
heralded as the fastest computing machines of that time, they surely
don’t stand a chance when compared to the modern day machines.
Modern day computers are getting smaller, faster, and cheaper and
more power efficient every progressing second. But what drove this
change? The whole domain of computing ushered into a new dawn of
electronic miniaturization with the advent of semiconductor transistor
by Bardeen (1947-48) and then the Bipolar Transistor by Shockley
(1949) in the Bell Laboratory.

Since the invention of the first IC (Integrated Circuit) in the form of a

Flip Flop by Jack Kilby in 1958, our ability to pack more and more
transistors onto a single chip has doubled roughly every 18 months, in
accordance with the Moore’s Law. Such exponential development had

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never been seen in any other field and it still continues to be a major
area of research work.

Fig. 2: Image Showing Comparison Of First Planar IC And Intel Nehleam

Quad Core Die

History & Evolution

The development of microelectronics spans a time which is even lesser

than the average life expectancy of a human, and yet it has seen as
many as four generations. Early 60’s saw the low density fabrication
processes classified under Small Scale Integration (SSI) in which
transistor count was limited to about 10. This rapidly gave way
to Medium Scale Integration in the late 60’s when around 100
transistors could be placed on a single chip.

It was the time when the cost of research began to decline and private
firms started entering the competition in contrast to the earlier years
where the main burden was borne by the military. Transistor-

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Transistor logic (TTL) offering higher integration densities outlasted

other IC families like ECL and became the basis of the first integrated
circuit revolution. It was the production of this family that gave impetus
to semiconductor giants like Texas Instruments, Fairchild and National
Semiconductors. Early seventies marked the growth of transistor count
to about 1000 per chip called the Large Scale Integration.

By mid eighties, the transistor count on a single chip had already

exceeded 1000 and hence came the age of Very Large Scale
Integration or VLSI. Though many improvements have been made and
the transistor count is still rising, further names of generations like ULSI
are generally avoided. It was during this time when TTL lost the battle
to MOS family owing to the same problems that had pushed vacuum
tubes into negligence, power dissipation and the limit it imposed on the
number of gates that could be placed on a single die.

The second age of Integrated Circuits revolution started with the

introduction of the first microprocessor, the 4004 by Intel in 1972 and
the 8080 in 1974. Today many companies like Texas
Instruments, Infineon, Alliance
Semiconductors, Cadence, Synopsys, Celox Networks, Cisco, Micron
Tech, National Semiconductors, ST Microelectronics, Qualcomm,
Lucent, Mentor Graphics, Analog Devices, Intel, Philips, Motorola and
many other firms have been established and are dedicated to the
various fields in “VLSI” like Programmable Logic Devices, Hardware
Descriptive Languages, Design tools, Embedded Systems etc.

VLSI Future

Future of VLSI

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Fig. 3: Graph Showing Future Of VLSI Technology In Various Sectors

Where do we actually see VLSI Technology in action? Everywhere, in

personal computers, cell phones, digital cameras and any electronic
gadget. There are certain key issues that serve as active areas of
research and are constantly improving as the field continues to mature.
The figures would easily show how Gordon Moore proved to be a
visionary while the trend predicted by his law still continues to hold
with little deviations and don’t show any signs of stopping in the near
future. VLSI has come a far distance from the time when the chips were
truly hand crafted. But as we near the limit of miniaturization of Silicon
wafers, design issues have cropped up.

VLSI is dominated by the CMOS technology and much like other logic
families, this too has its limitations which have been battled and

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improved upon since years. Taking the example of a processor, the

process technology has rapidly shrunk from 180 nm in 1999 to 60nm in
2008 and now it stands at 45nm and attempts being made to reduce it
further (32nm) while the Die area which had shrunk initially now is
increasing owing to the added benefits of greater packing density and a
larger feature size which would mean more number of transistors on a
chip.

As the number of transistors increase, the power dissipation is

increasing and also the noise. If heat generated per unit area is to be
considered, the chips have already neared that of the nozzle of a jet
engine. At the same time, the Voltage scaling of threshold voltages
beyond a certain point poses serious limitations in providing low
dynamic power dissipation with increased complexity. The number of
metal layers and the interconnects be it global and local also tend to
get messy at such nano levels.

Even on the fabrication front, we are soon approaching towards the

optical limit of photolithographic processes beyond which the feature
size cannot be reduced due to decreased accuracy. This opened up
Extreme Ultraviolet Lithography techniques. High speed clocks used
now make it hard to reduce clock skew and hence putting timing
constraints. This has opened up a new frontier on parallel processing.
And above all, we seem to be fast approaching the Atom-Thin Gate
Oxide layer thickness where there might be only a single layer of atoms
serving as the oxide layer in the CMOS transistors. New alternatives like
Gallium Arsenide technology are becoming an active area of research
owing to this.

VLSI Design Flow

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The VLSI IC circuits design flow is shown in the figure below. The
various levels of design are numbered and the blocks show processes in
the design flow.

Specifications comes first, they describe abstractly, the functionality,

interface, and the architecture of the digital IC circuit to be designed.

Behavioral description is then created to analyze the design in terms of

functionality, performance, compliance to given standards, and other
specifications.

RTL description is done using HDLs. This RTL description is simulated to

test functionality. From here onwards we need the help of EDA tools.

RTL description is then converted to a gate-level netlist using logic

synthesis tools. A gatelevel netlist is a description of the circuit in terms

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of gates and connections between them, which are made in such a way
that they meet the timing, power and area specifications.

Finally, a physical layout is made, which will be verified and then sent to
fabrication.

Y Chart

The Gajski-Kuhn Y-chart is a model, which captures the considerations

in designing semiconductor devices.

The three domains of the Gajski-Kuhn Y-chart are on radial axes. Each
of the domains can be divided into levels of abstraction, using
concentric rings.

At the top level (outer ring), we consider the architecture of the chip; at
the lower levels (inner rings), we successively refine the design into
finer detailed implementation −

Creating a structural description from a behavioral one is achieved

through the processes of high-level synthesis or logical synthesis.

Creating a physical description from a structural one is achieved

through layout synthesis.

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Design Hierarchy-Structural

The design hierarchy involves the principle of "Divide and Conquer." It

is nothing but dividing the task into smaller tasks until it reaches to its
simplest level. This process is most suitable because the last evolution
of design has become so simple that its manufacturing becomes easier.

We can design the given task into the design flow process's domain
(Behavioral, Structural, and Geometrical). To understand this, let’s take
an example of designing a 16-bit adder, as shown in the figure below.

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Here, the whole chip of 16 bit adder is divided into four modules of 4-
bit adders. Further, dividing the 4-bit adder into 1-bit adder or half
adder. 1 bit addition is the simplest designing process and its internal
circuit is also easy to fabricate on the chip. Now, connecting all the last
four adders, we can design a 4-bit adder and moving on, we can design
a 16-bit adder.

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VLSI Design - FPGA Technology

The full form of FPGA is “Field Programmable Gate Array”. It contains

ten thousand to more than a million logic gates with programmable
interconnection. Programmable interconnections are available for users
or designers to perform given functions easily. A typical model FPGA
chip is shown in the given figure. There are I/O blocks, which are
designed and numbered according to function. For each module of logic
level composition, there are CLB’s (Configurable Logic Blocks).

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CLB performs the logic operation given to the module. The inter
connection between CLB and I/O blocks are made with the help of
horizontal routing channels, vertical routing channels and PSM
(Programmable Multiplexers).

The number of CLB it contains only decides the complexity of FPGA. The
functionality of CLB’s and PSM are designed by VHDL or any other
hardware descriptive language. After programming, CLB and PSM are
placed on chip and connected with each other with routing channels.

Advantages

 It requires very small time; starting from design process to

functional chip.
 No physical manufacturing steps are involved in it.
 The only disadvantage is, it is costly than other styles.

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Gate Array Design

The gate array (GA) ranks second after the FPGA, in terms of fast
prototyping capability. While user programming is important to the
design implementation of the FPGA chip, metal mask design and
processing is used for GA. Gate array implementation requires a two-
step manufacturing process.

The first phase results in an array of uncommitted transistors on each

GA chip. These uncommitted chips can be stored for later
customization, which is completed by defining the metal interconnects
between the transistors of the array. The patterning of metallic
interconnects is done at the end of the chip fabrication process, so that
the turn-around time can still be short, a few days to a few weeks. The
figure given below shows the basic processing steps for gate array
implementation.

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Typical gate array platforms use dedicated areas called channels, for
inter-cell routing between rows or columns of MOS transistors. They
simplify the interconnections. Interconnection patterns that perform
basic logic gates are stored in a library, which can then be used to
customize rows of uncommitted transistors according to the netlist.

In most of the modern GAs, multiple metal layers are used for channel
routing. With the use of multiple interconnected layers, the routing can
be achieved over the active cell areas; so that the routing channels can
be removed as in Sea-of-Gates (SOG) chips. Here, the entire chip
surface is covered with uncommitted nMOS and pMOS transistors. The
neighboring transistors can be customized using a metal mask to form
basic logic gates.

For inter cell routing, some of the uncommitted transistors must be

sacrificed. This design style results in more flexibility for
interconnections and usually in a higher density. GA chip utilization
factor is measured by the used chip area divided by the total chip area.
It is higher than that of the FPGA and so is the chip speed.

Standard Cell Based Design

A standard cell based design requires development of a full custom

mask set. The standard cell is also known as the polycell. In this
approach, all of the commonly used logic cells are developed,
characterized and stored in a standard cell library.

A library may contain a few hundred cells including inverters, NAND

gates, NOR gates, complex AOI, OAI gates, D-latches and Flip-flops.
Each gate type can be implemented in several versions to provide
adequate driving capability for different fan-outs. The inverter gate can

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have standard size, double size, and quadruple size so that the chip
designer can select the proper size to obtain high circuit speed and
layout density.

Each cell is characterized according to several different characterization

categories, such as,

 Delay time versus load capacitance

 Circuit simulation model
 Timing simulation model
 Fault simulation model
 Cell data for place-and-route
 Mask data

For automated placement of the cells and routing, each cell layout is
designed with a fixed height, so that a number of cells can be bounded
side-by-side to form rows. The power and ground rails run parallel to
the upper and lower boundaries of the cell. So that, neighboring cells
share a common power bus and a common ground bus. The figure
shown below is a floorplan for standard-cell based design.

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Full Custom Design

In a full-custom design, the entire mask design is made new, without

the use of any library. The development cost of this design style is
rising. Thus, the concept of design reuse is becoming famous to reduce
design cycle time and development cost.

The hardest full custom design can be the design of a memory cell, be it
static or dynamic. For logic chip design, a good negotiation can be
obtained using a combination of different design styles on the same
chip, i.e. standard cells, data-path cells, and programmable logic arrays
(PLAs).

Practically, the designer does the full custom layout, i.e. the geometry,
orientation, and placement of every transistor. The design productivity

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is usually very low; typically a few tens of transistors per day, per
designer. In digital CMOS VLSI, full-custom design is hardly used due to
the high labor cost. These design styles include the design of high-
volume products such as memory chips, high-performance
microprocessors and FPGA.

VLSI Design - MOS Transistor

Complementary MOSFET (CMOS) technology is widely used today to

form circuits in numerous and varied applications. Today’s computers,
CPUs and cell phones make use of CMOS due to several key
advantages. CMOS offers low power dissipation, relatively high speed,
high noise margins in both states, and will operate over a wide range of
source and input voltages (provided the source voltage is fixed)

For the processes we will discuss, the type of transistor available is the
Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). These
transistors are formed as a ‘sandwich’ consisting of a semiconductor
layer, usually a slice, or wafer, from a single crystal of silicon; a layer of
silicon dioxide (the oxide) and a layer of metal.

Structure of a MOSFET

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As shown in the figure, MOS structure contains three layers −

 The Metal Gate Electrode

 The Insulating Oxide Layer (SiO2)
 P – type Semiconductor (Substrate)

MOS structure forms a capacitor, with gate and substrate are as two
plates and oxide layer as the dielectric material. The thickness of
dielectric material (SiO2) is usually between 10 nm and 50 nm. Carrier
concentration and distribution within the substrate can be manipulated
by external voltage applied to gate and substrate terminal. Now, to
understand the structure of MOS, first consider the basic electric
properties of P – Type semiconductor substrate.

Concentration of carrier in semiconductor material is always following

the Mass Action Law. Mass Action Law is given by −

Where,

 n is carrier concentration of electrons

 p is carrier concentration of holes
 ni is intrinsic carrier concentration of Silicon

Now assume that substrate is equally doped with acceptor (Boron)

concentration NA. So, electron and hole concentration in p–type
substrate is

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Here, doping concentration NA is (1015 to 1016 cm−3) greater than

intrinsic concentration ni. Now, to understand the MOS structure,
consider the energy level diagram of p–type silicon substrate.

As shown in the figure, the band gap between conduction band and
valance band is 1.1eV. Here, Fermi potential ΦF is the difference
between intrinsic Fermi level (Ei) and Fermi level (EFP).

Where Fermi level EF depends on the doping concentration. Fermi

potential ΦF is the difference between intrinsic Fermi level (Ei) and
Fermi level (EFP).

Mathematically,

The potential difference between conduction band and free space is

called electron affinity and is denoted by qx.

So, energy required for an electron to move from Fermi level to free
space is called work function (qΦS) and it is given by

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The following figure shows the energy band diagram of components

that make up the MOS.

As shown in the above figure, insulating SiO2 layer has large energy
band gap of 8eV and work function is 0.95 eV. Metal gate has work
function of 4.1eV. Here, the work functions are different so it will
create voltage drop across the MOS system. The figure given below
shows the combined energy band diagram of MOS system.

As shown in this figure, the fermi potential level of metal gate and
semiconductor (Si) are at same potential. Fermi potential at surface is
called surface potential ΦS and it is smaller than Fermi potential ΦF in
magnitude.

Working of a MOSFET
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MOSFET consists of a MOS capacitor with two p-n junctions placed

closed to the channel region and this region is controlled by gate
voltage. To make both the p-n junction reverse biased, substrate
potential is kept lower than the other three terminals potential.

If the gate voltage will be increased beyond the threshold voltage

(VGS>VTO), inversion layer will be established on the surface and n – type
channel will be formed between the source and drain. This n – type
channel will carry the drain current according to the VDS value.

For different value of VDS, MOSFET can be operated in different regions

as explained below.

Linear Region

At VDS = 0, thermal equilibrium exists in the inverted channel region and

drain current ID = 0. Now if small drain voltage, VDS > 0 is applied, a
drain current proportional to the VDS will start to flow from source to
drain through the channel.

The channel gives a continuous path for the flow of current from source
to drain. This mode of operation is called linear region. The cross
sectional view of an n-channel MOSFET, operating in linear region, is
shown in the figure given below.

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At the Edge of Saturation Region

Now if the VDS is increased, charges in the channel and channel depth
decrease at the end of drain. For VDS = VDSAT, the charges in the channel
is reduces to zero, which is called pinch – off point. The cross sectional
view of n-channel MOSFET operating at the edge of saturation region is
shown in the figure given below.

Saturation Region

For VDS>VDSAT, a depleted surface forms near to drain, and by increasing

the drain voltage this depleted region extends to source.

This mode of operation is called Saturation region. The electrons

coming from the source to the channel end, enter in the drain –
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depletion region and are accelerated towards the drain in high electric
field.

MOSFET Current – Voltage Characteristics

To understand the current – voltage characteristic of MOSFET,

approximation for the channel is done. Without this approximation, the
three dimension analysis of MOS system becomes complex.
The Gradual Channel Approximation (GCA) for current – voltage
characteristic will reduce the analysis problem.

Gradual Channel Approximation (GCA)

Consider the cross sectional view of n channel MOSFET operating in the

linear mode. Here, source and substrate are connected to the ground.
VS = VB = 0. The gate – to – source (VGS) and drain – to – source voltage
(VDS) voltage are the external parameters that control the drain current
ID.

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The voltage, VGS is set to a voltage greater than the threshold voltage
VTO, to create a channel between the source and drain. As shown in the
figure, x – direction is perpendicular to the surface and y – direction is
parallel to the surface.

Here, y = 0 at the source end as shown in the figure. The channel

voltage, with respect to the source, is represented by VC(Y). Assume that
the threshold voltage VTO is constant along the channel region,
between y = 0 to y = L. The boundary condition for the channel voltage
VC are −

We can also assume that

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Let Q1(y) be the total mobile electron charge in the surface inversion
layer. This electron charge can be expressed as –

The figure given below shows the spatial geometry of the surface
inversion layer and indicate its dimensions. The inversion layer taper off
as we move from drain to source. Now, if we consider the small region
dy of channel length L then incremental resistance dR offered by this
region can be expressed as −

Here, minus sign is due to the negative polarity of the inversion layer
charge Q1 and μn is the surface mobility, which is constant. Now,
substitute the value of Q1(y) in the dR equation −

Now voltage drop in small dy region can be given by

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Put the value of dR in the above equation

To obtain the drain current ID over the whole channel region, the
above equation can be integrated along the channel from y = 0 to y = L
and voltages VC(y) = 0 to VC(y) = VDS,

For linear region VDS < VGS − VTO. For saturation region, value of VDS is
larger than (VGS − VTO). Therefore, for saturation region VDS = (VGS − VTO).

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Scaling

In order to build the high performance CMOS circuits certain electrical

design rules are taken into account. These rules are used to develop the
mathematical model of the physical phenomenon occurring in the
circuits.

As the current CMOS fabrication processes are improved and the device
dimensions are shrinking these design rules will change.

Hence as the device dimensions are changing the electrical parameters

of the devices are also has to be scaled accordingly to apply the
previously developed models to the current modern devices and
circuits.

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Efforts are under way to make transistors as small as possible to

increase speed and circuit complexity per unit of chip area.In scaling
of the MOS devices the characteristics of the device are maintained and
the basic operational characteristics are preserved by introducing a
dimensionless factor

For this purpose, we have to adjust a fabrication process and the bias
voltage to allow proper operation of reduced size devices. The
adjustments aim at achieving small dimension, at the same time,
avoiding several side effects, such as the smaller dimension effects.
Such a shrinking of device without side effects is called as scaling.

Advantages of Scaling:

The reduction in lateral dimensions of the MOSFET and interconnects

size is known as 'scaling' of the geometric dimensions of the MOSFET.

The advantages of Scaling are as follows,

1. Improved current driving capability improves the device

characteristics.
2. Due to small geometries the capacitance reduces.
3. Improved interconnect technology reduces the RC delay.
4. The multiple threshold devices due to scaling adjusts the active
and stand by power trade-offs.
5. The integration density improves due to single chip devices.
6. Enhanced performance in terms of speed and power
consumption.
7. Cost of a chip decreases by twice.

Disadvantages of Scaling:

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1. The power consumption per unit area increases as devices are

scaled down. That means scaled devices run increasingly hot. This
is a severe performance limitation for scaled devices.
2. The scaling leads to mistakes of having scale proportionally to
zero dimension or to zero threshold voltages.
3. Since scaling reduces the carrier mobility, gain of the device
reduces.
4. Due to reduction in conductor size, the current handling capacity
of the device reduce. To solve this addition metal layers are
necessary for more densely packed structure.
5. As the packing density per chip increases, due to higher power
density, the device becomes very hot and needs forced cooling at
the additional cost.
6. Higher fields also cause hot electron and oxide reliability
problems.

Types of Scaling:

There are three types of scaling as constant voltage, constant field and
lateral scaling. In constant voltage scaling, VDD is kept constant, and
the process is scaled. For constant field scaling, the device dimensions
are scaled by the parameter λ.

Constant Field Scaling:

The effect of scaling is shown in Table belowIn constant field scaling

the scaled devices are obtained by scaling all dimensions of transistor,
device voltages and the doping concentration densities by factor

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Types-of-Scaling

Types-of-Scaling

The most important point in this scaling is the supply voltage is scaled
but the electric field remains constant hence the same constant field
scaling is given.From the table it is seen that the device dimension, L,
W, tox, xj, NA are scaled by factor

Constant Voltage Scaling:

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 In constant voltage scaling the supply voltage VDD is kept

constant while the process is scaled. The effect of scaling is shown
in Table below.

Types-of-Scaling

 With constant voltage scaling the electric field increases which

has lead to the development of the lateral double diffused
structures.

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Lateral Scaling: In lateral scaling only the gate length is scaled. This is
also called as the "gate shrinking". The effect of this scaling of
parameters is shown in Table below.

Types-of-Scaling

Scaling of MOS devices

Introduction

The MOS transistor is the basic building block of integrated circuits.

Scaling of the MOS transistor improves its size, cost and performance.
Today's fabricated integrated circuits are many times faster and occupy
much less area, like today's microprocessors that contain nearly one
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billion transistors on a single chip. The role of supply voltage is vital for
controlling the power consumption and hence reducing the power
dissipation. It is reducing for each new technology generation.
Threshold voltage of the device must be reduced proportionally as
supply voltage reduces to sustain the transistor's output performance.
The reduction in threshold voltage increases the leakage current
drastically with each new technology generation. As the leakage
current increases with a new technology generation, it will affect the
overall logic circuit's power dissipation. Leakage current is the major
problem in the deep submicron region, so we need a powerful leakage
reduction technique to minimize the effect of threshold voltage scaling.

Scaling methods pay a significant role in reducing the power dissipation

from one technology node to another node. There are various scaling
methods used for VLSI circuits. Most common are voltage scaling, load
scaling, technology scaling and transistor sizing (width scaling). The
purpose of studying various scaling methods is to decide a suitable
method for scaling while keeping power dissipation and propagation
delay in mind. In this paper the work investigations are carried out on
the above said four scaling methods for a CMOS buffer circuit.

Scaling methods

 Voltage scaling

A common and very effective method of reducing the power dissipation

of a circuit is to reduce its supply voltage. The dynamic power
dissipation component is directly proportional to V2DD that makes this
technique so effective. Power reduction is possible through the voltage
scaling at a constant clock frequency. It is observed that a CMOS

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inverter will continue to operate correctly with a supply voltage which

is as low as the limit value shown in Eq. (1)

One MOS device is always in on condition in CMOS inverter for any

input voltage. The term voltage scaling used here is different from that
of constant voltage scaling because here all other parameters are kept
constant instead of scaling them by the same factor. This is the reason
for propagation delay increasing because only the supply voltage is
reduced. This is analytically observed from Eq. (2) for propagation delay
of the CMOS inverter as

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where τ is the propagation delay due to low to high and high to low
output voltage transition. Vth is the threshold voltages of the MOS
device. CL is the load capacitance and VDD is the power supply voltage.

The circuits operate more slowly as the supply voltage decreases when
assuming no other changes are made. This is the drawback of this
approach. Another drawback is that some circuit styles cannot function
at low supply voltages. The propagation delay increases with reducing
the power supply voltage and can be compensating if the threshold
voltage of the transistor is reduced accordingly. However, a reduction
in the threshold voltage will cause an exponential increase in the device
sub-threshold leakage current. In turn, this increases the static power

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of the device to unacceptable levels. This study clearly justifies the need
for leakage reduction techniques.

 Load scaling

Load scaling is the other way to reduce the power dissi- pation. Larger
load capacitance draws more charge from the power supply during
each switching and hence increases the dynamic power dissipationŒ8].
The larger capacitance reduces the speed of operation. Figure 1 shows
the load capacitance and its components at output node Vout.

Here Cgd1 and Cgd2 are the overlap capacitances, Cg1 and Cg2 are the
gate capacitances, Cdb1 and Cdb2 are the drain/source diffusion
capacitances, and Cint is the interconnect capacitance which is due to
parallel plate capacitance, fringing capacitance and wire-wire
capacitance.

Therefore the capacitances are given as below:

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If RL is the summed resistance of the overall circuit at the load terminal

then propagation delay of the circuit is the multiply of load capacitance
and load resistance.

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 Transistor width scaling

Transistor sizing is also known as channel width scal- ing. Transistor

width scaling effectively reduces power dissipation. If the channel width
of the transistor is increased, then it reduces the signal transition at the
output and hence propagation delay of the logic circuit. The small value
of channel width is utilized for optimization of power dissipation and
chip area while the large value is used to optimize the propagation
delay of the logic circuit. For high performance calculation it may be
seen that finding a single critical path can degrade the performance of
the entire circuit. However, in low power de- sign the focusable target
is on lower power dissipation while taking propagation delay
constraints and assuming the certain active area for the logic circuit.

Figure 3 shows the 2-gate circuit with the first gate driving the gate
capacitance Cg and the parasitic capacitance CP to the next gate.

The input gate capacitance of both gates is given by NCref, where Cref is
the gate capacitance of an MOS device with the possible smallest
aspect ratio. The propagation delay through the first gate at a supply
voltage Vref is given by Eq. (6)

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where ˛ is the ratio of CP to Cref, and K stands for the condi- tions
independent of the device’s width and voltage.

 Transistor’s technology scaling

CMOS technology has continued to scale down at a dra- matic rate to

opt high performance. In 1975, Moore predicted that the number of
transistors per square inch in an IC would double every 18 months. In
each new technology generation, the overall lateral and vertical
dimensions of the transistors are scaled down by a factor. Figure 4
reflects the reduction of the key dimensions of a typical MOSFET while
increasing of the doping densities.

The new technology generation has an impact on reducing the power

dissipation, as well as increasing the circuit’s speed due to reduction of
all capacitance effects. As today’s technol- ogy scales below 45 nm, the
transistor density will continue to growŒ11]. A number of limitation

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factors like short channel effects, sub-threshold conduction, body effect

etc. arise in the very deep submicron region for further scaling of the
transis- tors. In practice, there are two types of scaling strategies for
MOSFET devices: full scaling and constant voltage scaling.

Constant field scaling reduces both the drain voltage and the drain
current by a factor of S. Therefore, the power dis- sipation of the
transistor decreases by a factor of S2, while it increases by the factor S
in constant voltage scaling. This sig- nificant reduction of the power
dissipation is one of the most attractive features of constant field
scaling. However, the con- stant field scaling causes the sub-threshold
leakage currents to grow exponentially and becomes an increasingly
larger com- ponent of the total power dissipationŒ12].

Conventional and LPTG CMOS buffer

A conventional CMOS buffer consists of two inverters cas- caded as

shown in Fig. 5. The input and the output have a def- inite delay time
due to the device transitions in the CMOS cir- cuits. The buffer circuit is
generally used to drive large capac- itive loads developed both by the
next stage and the intercon- nect capacitances too. So, while building
buffers, both strong NMOS and PMOS are used. This would help the
device in charging and discharging the buffers quicker than normal. But
these strong MOS devices in turn provide large capacitance and affect
the time delays of the previous stages of the circuits.

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From the above said scaling methods, various important outcomes

appear to explain them in the very deep submicron region. As we are
moving towards the very deep submicron re- gion the supply voltage as
well as threshold voltage must be scaled in proper ratio to maintain the
correct operation of the logic circuit. Power dissipation is the important
term in the deep submicron region because of reduction in threshold
volt- age and effects of various other parameters to increase the leak-
age current components. As the technology node scales down below 65
nm node, many reliability problems are coming into being as a
resultŒ14]. The above discussions tell that power dis- sipation and
parameter variations are the main issues as technology scales down
below 65 nm. To reduce the power dissipation a number of leakage
reduction techniques are used. These techniques have their own
advantages and disadvantages. In this section we have proposed a
reliable leakage reduction technique for a CMOS buffer circuit.
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Our proposed low power transmission gate (LPTG) ap- proach is a

circuit level approach for reducing the leakage current and hence,
leakage power directly affected the total power dissipation of the logic
circuit. This approach is very effectively reducing both the active as well
as the standby mode leakage current. Through a literature survey we
know that many leakage reduction techniques are there in low power
design but one simple and effective technique called LEC- TORŒ15], is
the single threshold voltage circuit level technique. The drawback of
this technique is its low output swing volt- age. Our proposed approach
gives full output swing voltage as well as lower power dissipation as
compared to LECTOR technique. The proposed approach used the extra
insertion of transmission gates between the pull-up to output and
output to pull-down network for minimizing the leakage current. These
extra inserted transmission gates are called low power trans- mission
gates (LPTG). LPTG provides a high conducting path when this block is
on and a high resistive path when this block is off. The LPTG circuit
block contains one NMOS and one PMOS transistor. The schematic of
the CMOS LPTG buffer circuit is shown in Fig. 12. Here con and conbar
are the control signals which are complementary to each other. These
signals are used for activation or deactivation of the LPTG blocks. These
signals depend on the output functionality of the buffer circuit. These
signals must be precisely defined to give the re-

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liable and accurate performance of the circuit. If input voltage is

uniformly on/off periodic pulse with time period tp then con and
conbar are given as:

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These control signals also depend on the logic states of input voltage.
Control signals con and conbar are assigned with appropriate potential
based on the logic states of the input voltage.

Results and discussion

 Voltage scaling for CMOS conventional buffer

HSPICE EDA tool is used for calculating power dissipa- tion and
propagation delay for the conventional CMOS buffer at 65 nm, 45 nm
and 32 nm technology nodes. For making a fine comparison, other
parameters except supply voltage of these particular technology nodes
are taken the same through- out the scaling of supply voltage. The
supply voltage range for different technology nodes is precisely defined
before an- alyzing the logic circuit because it is related to reliability of
the circuit. The supply
˙ voltages for different technologies are chosen so
as to maintain the high noise margin with proper output function while
keeping the effective work of process parameters. According to ITRS
the nominal supply voltage for 65 nm is 1.0 V, for 45 nm it is 0.9 V, and
for 32 nm node it is 0.8 V. The supply voltage range is 20% of the
nominal value and it is 0.80 to 1.20 V for 65 nm technology node, 0.72
to 1.08 V for 45 nm technology node and 0.64 to 0.96 V for 32 nm
technology node for precise and reliable operation of the circuit. Figure
6 depicts the supply voltage scaling at different technology nodes.

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It is observed from Fig. 6 that power dissipation is reduced with the

reduction of supply voltage but propagation delay increases. For 65 nm
technology, where supply voltage range is 0.80 to 1.20 V, % reduction
in power dissipation is 86.73% while propagation delay increases by
112.14%. For 45 nm technology, where supply voltage range is 0.72 to
1.08 V, % reduction in power dissipation is 85.28% while propagation
delay increases by 114.66%. For 32 nm technology, the supply voltage
range is 0.64 to 0.96 V, % reduction in power dissipation is 91.64%
while propagation delay increases by 155.31%. It is concluded from the
above results that the voltage scaling is more efficient when technology
scaled in terms of power dissipation saving, while it is challenging to
reduce the propagation delay.

Figure 7 shows the decrease in propagation delay with corresponding

increasing in supply voltage and technology node of the conventional

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buffer. As the power dissipation increases in direct proportion with the

supply voltage, so a compromise is to be made between the
propagation delay and power dissipation of the conventional buffer
depending upon the application requirements. A figure of merit is
utilized to decide the acceptable level of propagation delay in low
power VLSI circuit design. Figure of merit is the product of leakage
power and propagation delay of the logic circuits. The supply voltage
scaling improves the figure of merit by 78.70% when scaling from 0.96
to 0.64 V for 32 nm technology node.

Load scaling for CMOS conventional buffer

With the reduction in the load capacitance, both power dissipation and
propagation delay are reduced as shown in Figs. 8 and 9 at 65 nm, 45
nm and 32 nm technology nodes. For making a fine comparison, other
parameters, except load capacitance, of these particular technology
nodes are taken as the same for scaling of load capacitance. The load
capacitance range for different technology nodes are precisely defined
before analyzing the logic circuit because it is related to stability of the
circuit. The ranges of load capacitances are chosen so as to optimize
the power dissipation and propagation delay, while controlling the
good input output characteristics of the logic circuit. Total power
dissipation is the summation of dynamic and static power dissipation,
where dynamic power is directly pro-

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portional to the load capacitance CL. It is concluded that power

dissipation is reducing as load capacitance is decreased, as power
dissipation directly depends on the load capacitance. Figure 9 shows
that reduction in the load capacitance is reduc- ing the propagation
delay. As load capacitance is decreased, the output signal is changed
rapidly and hence reduces the transi- tion times at the output of
conventional buffer. At 65 nm tech- nology node the propagation delay
is increasing with increase in the load capacitance values.

The load capacitance scaling improves the figure of merit by 71.54%

when scaling from 2.0 to 0.1 fF for 32 nm technology node.

 Technology scaling for CMOS conventional buffer

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The results for technology scaling are presented in Fig. 10 at different

technology nodes. It is concluded that power dis- sipation and
propagation delay are increased with technology scaling. The
incremental change in power dissipation with technology is due to
leakage current components which are more dominant at lower
technology node. Sub-threshold and gate leakage are the dominant
components of leakage current in the very deep sub-micron region. The
energy efficiency

Fig. 10. Power dissipation and propagation delay for conventional buffer at
different technologies.

of the logic circuit is evaluated by the figure of merit. The lower value of
figure of merit is desirable for energy efficient operation of the logic
circuit. Figure 10 shows the power dissipation and propagation delay
curves at different technology nodes.

It is clear that as technology scaled down from 65 to 32 nm, 356.48%

power dissipation and 18.64% propagation delay is increased. Figure of
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merit increases with reduction of technology node. It increases very

rapidly below 45 nm technology node. The technology scaling degrades
the figure of merit by 516% when scaling from 65 nm to 32 nm
technology node. A good VLSI designer wants to minimize the figure of
merit to optimize the logic circuit design. It is the challenging task of the
designers in the very deep submicron region and it requires the
effective architecture, technique or algorithm to optimize both power
dissipation and propagation delay of the circuit.

 Transistor width scaling for CMOS conventional buffer

The results for width scaling at 32 nm technology node are given in Fig.
11. The nominal supply voltage is 0.8 V at 32 nm node. The nominal
width of NMOS device is twice of the corresponding channel length and
it is six times in PMOS device. The width ratio of PMOS to NMOS device
is increasing from 1 to 5. The power dissipation of conventional buffer
is increased by 438.47% while propagation delay reduces by 66.28%
from width ratio scaling of 1 to 5. It is inferred that with decreasing
width ratio of the transistors, the power dissipation decreases with
increment in the propagation delay penalty. By taking the appropriate
transistor’s sizing, the designer made his design very valuable. The
transistor’s width scaling improves the figure of merit by 44.90% when
scaling from 5 to 1 for 32 nm technology node.

 LPTG CMOS buffer

The above discussions for a conventional CMOS buffer are presented

for different scaling methods. Technology scaling is the prime
requirement of the future nanoscale devices due to scaling of the
various device parameters. The limitation of technology scaling is its
poor figure of merit. We have proposed a low power transmission gate
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CMOS buffer circuit for improving the figure of merit of the technology
scaling method.

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The generalized schematic of the LPTG CMOS buffer is shown in Fig. 12.
In the proposed design, eight extra transistors are employed for
providing the path resistance from power supply to ground. The area
requirement is reduced by choosing a fitting width scaling.

Comparison of the conventional buffer and the LPTG CMOS buffer on

power dissipation and propagation delay performance at different
technologies is shown in Fig. 13. The LPTG approach reduces the power
dissipation effectively when moving towards low technology nodes. In
the LPTG approach we used the MOS devices which have accurate and
efficient turning on/off characteristic. The number of off MOS devices
between power supply to ground provides the greater body bias of
these MOS devices, thus reducing the power dissipation. At 32 nm
technology node LPTG approach reduces 95.16% power dissipation

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while increasing the propagation delay by 226.19%. The increments in

propagation delays are of less concern because the LPTG approach has
the better figure of merit. The figure of merit at 32 nm technology
reduces by 84.23%. Our proposed approach is more valuable in the very
deep nanoscale region as it reduces the figure of merit by 44.10% to
84.23% when moving from 65 nm to 32 nm technology node.

The graph clarifies that the power dissipation of the LPTG

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buffer circuit is very low and less influenced at low technology node in
the very deep submicron region as compared to the conventional
buffer. On the basis of propagation delay, the LPTG buffer circuit having
the greater delay because of the number of transistors used in the LPTG
buffer, increases the propagation delay of the circuit.

Now we consider the effect of width ratio variation of the LPTG buffer
circuit at 32 nm technology node while taking power supply voltage 0.8
V. A width comparison of the conventional CMOS buffer and LPTG
CMOS buffer is shown in Fig. 14. The LPTG CMOS buffer circuit reduces
the power dissipation by nearly 90.98% at width ratio 1. The sub-
threshold leakage current component directly affected the power
dissipation of the CMOS buffer circuit while larger width ratio causes
larger chip area and proportionally reduces the speed of the circuit. An
important result is reduction of the propagation delay with increment
in width as compared to the conventional CMOS buffer. At normal
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width calculation, the % change in propagation delay is 196.83% while

it is 259.83% at width ratio 5. The LPTG approach diminishes normally
70.70% figure of merit as width ratio varies from 1 to 5 as compared to
the conventional CMOS buffer.

The power dissipation and delay vs. temperature effects are analyzed
as explained in Fig. 15. The temperature range is taken from 25 to 125
0
C. Power dissipation and propagation

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delay for both circuits are increased with increasing the temperature.
The increment in power dissipation is due to thermal voltage
dependency of the leakage current. If we calculate the % change of
these two parameters then % saving of power dissipation is decreasing
while propagation delay increases as temperature increasing. Leakage
uncertainty is less in the LPTG approach as compared to the
conventional. The LPTG approach is less affected, normally 64.10%
figure of merit with temperature varying from 25 to 125 0C as
compared to the conventional CMOS buffer.
˙ effect of voltage
The ˙ scaling of ±20% variations from nominal value is

analyzed for LPTG and conventional CMOS buffer circuit. The output
results are illustrated in Fig. 16 at 32 nm technology node. The rising
rate of performance parameters are very slow in the LPTG approach
with increasing in VDD as compared to conventional circuit.

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The ±20% power supply voltage variations are less influenced, normally
73.20% figure of merit as compared to conventional CMOS buffer.

The summation of leakage current components under various process,

voltage and temperature variations are distributed as shown in Fig. 17.
These leakage current components are responsible for power
dissipation and reliability issues in buffer circuit.

Figure 17 is plotted by taking ±10% variations in pro-

cess, voltage and temperature parameters with Monte–Carlo 1000 runs

at 32 nm node. The LPTG approach is less susceptible to the process
variations as compared to conventional circuit. The value of mean and
standard deviation of leakage current components are 86.83 nA and
79.05 nA respectively for conventional CMOS buffer while in LPTG
CMOS buffer, these are 72.86 nA and 31.50 nA respectively. The
leakage current uncertainty is 0.91 in conventional while it is 0.43 in
LPTG CMOS buffer. Thus our proposed approach mitigates 2.12X
reliability issues in CMOS buffer circuit.

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Conclusion

Low power design is drawing a huge deal of awareness in VLSI digital

design, principally for portable high performance systems. The quick
switching of billions of transistors dissipates tremendous power and
overheats the chip, reducing the reliability of the chip and necessitating
expensive and large cooling systems. In this article, scaling methods like
voltage scaling, load scaling, technology scaling and width scaling for a
nanoscale CMOS buffer circuit have been analyzed. Based on the
analysis of these scaling methods we proposed a reliable low power
transmission gate approach which effectively reduces the power
dissipation and enhances the reliability. Different scaling variations are
used to analyze the power dissipation and propagation delay behavior
in the CMOS buffer circuit. The necessity of future nanoscale circuits is
mitigation of the energy consumption per cycle. The least value of
figure of merit provides the energy efficient design at future nanoscale
nodes. Our proposed approach saves power dissipation by 95.16% with
84.20% progress in figure of merit in the CMOS buffer at 32 nm
technology node. The LPTG approach decreases the leakage current
uncertainty from 0.91 to 0.43 in the CMOS buffer for reliable operation
of the logic circuit in the very deep submicron region.

CMOS (Complementary Metal-Oxide Semiconductor)

The first working point contact transistor developed by John Bardeen,

Walter Brattain and William Shockley at Bell laboratories in 1947
initiated the rapid growth of the information technology industry. In
1958, J Kilby invented the first integrated circuit flip flop at Texas and
soon after this; Frank Wanlass at Fairchild described the first CMOS
logic gate (nMOS and pMOS) in 1963.

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The most common description of the evolution of CMOS technology is

known as Moore’s law. In 1963 Gordon Moore predicted that as a
result of continuous miniaturization, transistor count would double
every 18 months. The observation made by Gordon Moore was that the
number of components on the most complex integrated circuit chip
would double each year for the next 10 years. This doubling was based
on a 50 – 60-component chip produced at that point of time compared
with those produced in preceding years. Looks surprising, but his
prediction has turned true and is being treated as a law. The speed of
transistors increases and their cost decreases as their size is reduced.
The transistors manufactured today are 20 times faster and occupy less
than 1% of the area of those built 20-30 years ago. In 1971, Intel 4004
had transistors with minimum dimension of 10um and in 2003; Pentium
4 had transistors with minimum dimension of 130 nm. Having crossed
90nm, 65nm technological nodes, 32 nm and 22nm technology is in the
pipeline. 53% compound annual growth rate is achieved over 45 years.
No other technology has grown so fast so long. Transistors have
become smaller, faster, consume less power, and are cheaper to
manufacture. It seems intuitively obvious that scaling cannot go on
forever because transistors cannot be smaller than atoms.

The first integrated circuits hitting the markets in the seventies had a
few 100 transistors integrated in bipolar technology. Even though the
principles were well known, MOS arrived in the markets several years
later. One of the reasons behind this was the inherent instability of the
MOS transistors due to the presence of minute amounts of alkali
elements in the gate dielectric. This caused the threshold voltage of the
transistor to shift during the operation.

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However, soon the problems of high power consumption by bipolar

circuits became dominant. Even in the case of all transistors being
‘OFF’, the sum of the leakage current in bipolar transistors is fairly
large. To provide a solution for the problem of power
consumption, MOS technology eventually made its way. Dimensions of
MOS devices can be scaled down more easily than other transistor
types.

In principle, MOS is better in terms of power consumption. MOS

devices work with only switching voltages; current per se is not needed
for the operation. MOS circuits do have lower power consumption; but
they are also slower than their bipolar colleagues. Initially, NMOS got
wider acceptance but with the increase in integration density, power
consumption again became a problem. Afterwards, in eighties, CMOS
processes were widely adopted. Present day chips would not exist if
the CMOS technique would not have been implemented around the
late eighties.

IC TECHNOLOGIES

Silicon IC technologies can be primarily classified under three types:

 Bipolar

Bipolar transistors have npn or pnp silicon structure. In these

transistors, small current into very thin base layer controls large
currents between emitter and collector. Base currents limit integration
density of bipolar devices.

 Metal Oxide Semiconductor(MOS)

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MOS is further classified under PMOS (P-type MOS), NMOS (N-type

MOS) and CMOS (Complementary MOS). MOS derives its name from
the basic physical structure of these devices; MOS devices comprise of
a semiconductor, oxide and a metal gate. Nowadays, polySi is more
widely used as gate. Voltage applied to the gate controls the current
between source and drain. Since they consume very low power, MOS
allows very high integration.

 BiCMOS(Bipolar CMOS technology)

BiCMOS Technology utilizes both CMOS and Bipolar Junction transistors

integrated on the same semiconductor chip.

CMOS offers high, symmetrical noise margins, high input and low
output impedance, high packing density, and low power dissipation but
speed is the only restricting factor. In contrast, the ECL gate has a high
current drive per unit area, high switching speed, smaller propagation
delay, but high power consumption makes very large scale integration
difficult.

BiCMOS has made it possible to combine CMOS transistors and bipolar

devices in a single process at a reasonable cost to achieve the high-
density integration of MOS logic with the current-driving capabilities of
bipolar transistors.

Some other variants of FETs have also come up, viz., Si-TFT, polySi-TFT,
MESFET, etc. These are used for different applications.

CMOS BASICS

Before exploring CMOS look into NMOS and PMOS.

NMOS
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The first letter ‘N’ refers to the kind of carrier that carries current flow
between source and drain as soon as the threshold voltage is crossed.
Thus, NMOS stands for transistors where negatively charged carriers,
i.e., electrons are the current carriers between source and drain.

Physical structure of NMOS device is shown below

Fig. 1: A Diagram Representing Physical Structure of NMOS Device

Operation of the device is listed below

– Body is commonly tied to ground (0 V)

– When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
– When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Channel under gate gets “inverted” to n-type

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– Now current can flow through n-type silicon from source

through channel to drain, transistor is ON

NMOS operation is depicted pictorially in the following figure.

Fig. 2: A Diagram Illustrating Operation of NMOS

Fig. 3: A Diagram Illustrating Multiple Operation of NMOS

Cons of NMOS

– Output Low consumes power

– Pull-up “weaker” than pull-down
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– Need resistors

Pros of NMOS

For X inputs: X NMOS Transistors

PMOS

PMOS stands for transistors where positively charged carriers flow, i.e.
holes are the current carriers. This implies that source and drain must
be p-doped areas in an n-doped substrate; the current flow begins as
soon as inversion sets in, i.e. the n-type Si between source and drain is
inverted to Si with holes as the majority carriers.

Physical structure of PMOS device is shown below

Fig. 4: A Figure Representing Physical Structure of PMOS

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Operation of PMOS device is similar to that of NMOS but doping and

voltages reversed

 Body tied to high voltage (VDD)

 When Gate is low: transistor is ON
 When gate is high: transistor is OFF
 Bubble indicates inverted behavior

VGS > VTN

VGS <= VTN, VDS<= VDSAT

CMOS & its Fabrication

CMOS has characteristics very close to that of an ideal logic family. Ideal
logic family should dissipate no power, should have zero propagation
delay, controlled rise and fall times, and have good noise immunity.

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NMOS and PMOS transistors are not ideal switches. NMOS pass strong
‘0’ but a degraded or weak ‘1’ (pull no higher than VDD-Vtn); whereas
PMOS pass strong ‘1’ but a degraded or weak ‘0’ (pull no lower than
|Vtp|). Hence, NMOS are best for pull-down network, whereas PMOS
are best for pull-up network.

CMOS takes the merits of both, NMOS and PMOS. CMOS technology
uses NMOS and PMOS transistors. The transistors are arranged in a
structure formed by two complementary networks, viz. Pull Up
Network and Pull Down Network (PDN). Since there is no static current
flow; only a small amount of dynamic current exists while switching
takes place, CMOS device consume very small amount of power.

– PUN: Pull Up Network

– PDN: Pull Down Network

Pull Up
Pull Up ON
OFF

Pull
Down Z(float) 1
OFF

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Pull
Down 0 X(Crowbar)
ON

CMOS gates always produce ‘0’ or ‘1’. Depending on the right polarities,
the PMOS transistor will be closed if there is a gate voltage – the output
then is zero. For gate voltage zero, the NMOS transistor will be closed,
the PMOS transistor is open – the output will be VDD.

Pros of CMOS

– No static power consumption

– Pull-up symmetric with pull-down. Output swings to full range
– Both high to low and low-to-high transitions are fast because of
low resistance of pull-up transistors unlike the load resistors in
NMOS logic

Cons of CMOS

For X inputs: 2X CMOS Transistors are needed.

CMOS FABRICATION

Complexity and the cost of fabrication are governed by the number of

masks fabrication technology uses. CMOS process requires seven
masks, & 34 process steps. Minimum dimensions of masks determine
transistor size (and hence speed, cost, and power)

Technology nodes are defined by the feature size; Feature size f =

distance between source and drain is set by minimum width of
polysilicon. While describing design rules, feature size is normalized.
Design rules are expressed in terms of l = f/2, e.g. l = 0.3 mm in 0.6 mm
process
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Major fabrication steps for a CMOS process are as follows:

a) Growth of SiO2 on p-type wafer

b) Creation of p and n wells

CMOS technology requires fabrication of two different transistors-

NMOS and PMOS on a single chip substrate. Actually, NMOS and PMOS
needs substrates with different kind of doping in one integrated circuit
but such substrates do not exist; a Silicon wafer always has one doping
type and doping level. Hence, to accommodate both NMOS and PMOS
transistors, CMOS technology requires creation of special regions by
impurity implantation in the substrate; semiconductor type in these
regions is opposite to the base substrate type. These regions are called
wells or tubs. A p-well is created in an n-type substrate or, alternatively,
an n- well is created in a p-type substrate. Thus, if base substrate is p-
type, NMOS transistor is created in the p-type substrate while PMOS
transistor is created in the n-well built in the p-type base substrate.

It involves three steps

(a) Photolithography to define n-well area

(b) Ion Implantation to create n-well
(c) Removal of PR and oxide layer.

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c) Channel Stop Implant

It is required to prevent conduction between unrelated transistor

sources and drains.

Region between two n+ regions is covered with field oxide and

metallization on top of it. This forms a transistor, though with large
threshold, and introduces parasitics.

Channel stop implantations are done with the help of 5 process steps.

(d) Create a stack of Silicon Oxide, Silicon Nitride and

positive photoresist layers.
(e) Photolithography to define channel implant areas
(f) Channel Stop Ion Implantation
(g) Removal of PR. Growth of thick oxide layer in areas
where Silicon Nitride is not there.
(h) Removal of Thin Silicon Oxide, Silicon Nitride layers.

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CMOS Fabrication contd.

d) Growth of Gate Oxide to serve as gate dielectric

Thickness of gate dielectric affects number of parameters of MOSFETs,

viz., current handling, transconductance, reliability. Uniform thickness
of this layer is pretty important.

e) Threshold adjust implant

Native threshold value typically is far from the desired values (VTHN~ 0V
and VTHP~ -1 V). Hence thin layer of dopants are implanted to adjust it.

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f) Create PolySi Layer

It involves two steps

(i) Deposit PolySi on top of Gate Oxide

(j) Photolithography to remove SiO2 using ‘PolySi’
mask

g) N-type Implant

It involves three process steps

(k) Photolithography using ‘N Drain/Source mask’

(l) Ion implantation to form Source & Drain regions

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(m) Removal of PR

h) P-type Implant

In similar fashion, p+ regions are created

i) Silicidation

Silicidation is done to reduce sheet resistance of doped PolySi and

source/drain regions. This process involves deposition of thin layer of
highly conductive material (titanium silicide and tungsten). It involves
two process steps

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(n) Creation of oxide spacers at edges of PolySi gate.

(o) Deposition of conductive material through CVD
process.

j) Contact Windows

It involves following steps

b) Cover wafer with a thick layer of oxide

c) Photolithography using contact mask
d) Plasma etching

k) Metal Interconnect
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It involves following steps

e) Deposit a layer of metal

f) Photolithography using Metal Mask

l) Via Windows

It involves following steps

g) Deposit a layer of SiN3

h) Photolithography using Via Mask

m) Metallization

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a) Passivation & Bond Pads

Wafer is covered with a layer of glass to protect the surface against the
damages. Finally bond pads are created.

CMOS v/s BJT and CMOS Logic

COMPARISION OF THE FEATURES OF CMOS & BJT DEVICES

– Compared to BJT CMOS devices are low power consumption

device. Power is drawn only during switching of states in CMOS.
– CMOS is uni-polar but BJT is bipolar.
– Manufacturing is easier for CMOS rather than BJT.
– CMOS is voltage controlled device, BJT is current controlled
device.
– CMOS has very high input impedance; BJT is having relatively low
input impedance. Hence, CMOS devices will have less loading
effect

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– CMOS is more sensitive to electrostatic discharge compared to

BJT.
– MOSFET has higher immunity towards radiation compared to BJT
– BJT is very high speed switching device and hence can be used at
higher frequencies compared to CMOS
– CMOS have high noise margin rather than BJT.
– Integration density is better in CMOS
– CMOS produce less amount of heat

CMOS LOGIC

Different logic families use different voltage levels for logic ‘high’ and
logic ‘low’. For 5V CMOS family, voltage levels are VIL = 1.5 V, VOL = 0.5
V, VIH = 3.5 V, VOH = 4.4 V & for 2.5 V CMOS family, voltage levels are
VIL = 1.5 V, VOL = 0.5 V, VIH = 3.5 V, VOH = 4.4 V. In 5V TTL logic family
voltage levels for logic ‘high’ and logic ‘low’ are VIL = 0.8 V, VOL = 0.4 V,
VIH = 2 V, VOH = 2.4 V. Similarly, voltage levels are different for ETL,
TTL/CMOS, etc logic devices.

5V CMOS 5V TTL 2.5 V CMOS

The CMOS have different input and output switching levels than the TTL
logic devices. The output switching levels from CMOS ICs is higher than
a TTL IC, which happens to result in a better design and does not have a

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negative effect. However the difference in input logic switching level

does affect the design. The TTL output does not correctly switch a
CMOS input. The switching difference between a TTL IC output and a
CMOS IC input has to be accounted for. In CMOS the floating input is
interpreted as an uncertain and In TTL the floating input is interpreted
as a logical low.

Also, TTL (Transistor-Transistor Logic) need a narrow range of supply

voltage (around 5V) but CMOS (metal oxide semiconductor field effect
transistor) devices have a wider voltage range between 3-12 V.

BASIC CMOS CIRCUITS

Inverter

A Y

0 1

1 1

NAND Gate A B Y

0 0 1

0 1 1

1 0 1

1 1 0

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NOR GATE A B Y

0 0 1

0 1 0

1 0 0

1 1 0

NMOS IC Fabrication Process

There are a large number and variety of basic fabrication steps used in
the production of modern MOS ICs. The same process could be used for
the designed of NMOS or PMOS or CMOS devices. The gate material
could be either metal or poly-silicon (as described in this article for
NMOS device). The most commonly used substrate is bulk silicon or
silicon-on-sapphire (SOS). Inorder to avoid the presence of parasitic
transistors, variations are brought in the techniques that are used to
isolate the devices in the wafer.

The fabrication sequence of n-channel MOS IC is shown in the figure

below.

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Nmos IC Fabrication Process

NMOS structures

MOSFET Transistors

MOSFET Transistors or Metal Oxide-Semiconductor (MOS) are field

effect devices that use the electric field to create a conduction channel.

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MOSFET transistors are more important than JFETs because almost

all Integrated Circuits (IC) are built with the MOS technology.

There are two kinds of MOSFET transistors:

– N channel MOSFET Transistor or NMOS

– P channel MOSFET Transistor or PMOS

At the same time they can be enhancement transistors or depletion

transistors. In the present days the last ones are not used. In these
tutorials we will describe only the enhancement MOS transistor.

NMOS and PMOS Symbols

The following image shows the different symbols used to describe

the MOS transistor.

MOSFET transistors (NMOS) physical structure

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The next image shows the N channel MOSFET transistor physical

structure with its four terminals: Gate, Drain, Source and Substrate.
Normally the Source and the substrate are connected together.

The Gate with W and L dimensions is separated from the substrate by a

dielectric (SiO2), creating a similar structure of the capacitor plates.

If a positive voltage is applied to the gate, negative charges are induced

(inversion layer) on the substrate surface and they create a conduction
path between the Drain and Source terminals.

The minimum voltage needed to create the inversion layer is called

threshold voltage (VT). This is a characteristic feature of the transistor.
If VGS < VT, the drain-source current is zero. Typical values for this
voltage are between 0.5 and 3 volts.

NMOSFET operating regions

JFET and MOSFET transistors have a very different physical structure,

but their analytical equations are very similar. In the MOSFET
transistors, there are defined the same regions of operation: cutoff,
linear, saturation and breakdown.

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The image shows the curves of electrical characteristics of an NMOS

transistor with the different regions of operation. These regions of
operation are briefly described below.

NMOS FET Cutoff region

We can verify that VGS < VT and the current ID is zero.

NMOS FET Linear region

The transistor behaves as a nonlinear resistive element, controlled by

voltage. Check the following equations:

where:

is a characteristic parameter of the MOS transistor, which depends on

the k constant and the size of the transistor gate (width W and length
L).

NMOS FET Saturation region

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The NMOSFET transistor behaves as a voltage controlled current source

VGS. Check the following equations:

where ß = K (W/L)

In this region, the quadratic relationship between VGS and ID is shown

in the left part of the picture. In a similar way to the JFET transistors, it
can be used to identify, by graphical methods, the bias point of the
transistors. This method is rarely used.

NMOS FET Breakdown region

A MOS transistor can be affected by the avalanche phenomena in the

drain and source terminals. The MOS transistor can also be affected by
breaks in the thin oxide layer of the gate that may destroy the device.

Finally, note that the table above shows the differences in sign and
direction of the currents and voltages
between NMOS and PMOS transistors.

NMOS Fabrication Steps

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1. By the process of Chemical Vapour Deposition (CVD), a thin layer

of Si3N4 is deposited on the entire wafer surface. With the first
photolithographic step, the areas where the transistors are to be
fabricated are clearly defined. Through chemical etching, Si3N4 is
removed outside the transistor areas. In order to suppress the
unwanted conduction between transistor sites, an impurity such
as Boron is implanted in the exposed regions. Next, SiO2 layer of
about 1 micro meters thickness is grown in these inactive, or field
regions by exposing the wafer to oxygen in an electric furnace.
This is known as selective or local oxidation process. The Si3N4 is
impervious to oxygen and thus inhibits growth of the thick oxide
in the transistor regions.

2. Next, the Si3N4 is removed by an etchant that does not attack

SiO2. A layer of oxide about 0.1 micro meters thick is grown in the
transistor areas. Then a layer of poly-Silicon is grown over the
entire wafer by CVD process. The second photolithographic step
shows the desired patterns for gate electrodes. The unwanted
poly-Silicon is removed by chemical or plasma etching. In order to
introduce a source and drain in particular regions for the MOS
device, an n-type dopant, such as phosphorus or arsenic, is
introduced. This is done by either Diffusion or Ion
Implantation method. The thick field oxide and the poly- silicon
gate are barriers to the dopant, but in this process, the poly-Si
becomes heavily n-type.

3. Again, through CVD process, an insulating layer, SiO2, is deposited.

As shown in the figure above, the third photolithographic step
shows the areas in which contacts to the transistors are to be

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made. Chemical or plasma etching selectively exposes bare silicon

or poly-Si in the contact areas.

4. Al is used for the interconnection. As shown in the figure above,

the fourth masking step shows the Al as desired for the circuit
connections.

The final steps of the process are identical to those described for
bipolar transistor ICs. Above process is the simplest possible. For
advanced processing of NMOS and CMOS, 7 to 12 masking steps are
required.

Characteristics of MOS transistors

Introduction

The metal–oxide–semiconductor field-effect transistor (MOSFET) is a

transistor used for amplifying or switching electronic signals. In
MOSFETs, a voltage on the oxide-insulated gate electrode can induce a
conducting channel between the two other contacts called source and
drain. The channel can be of n-type or p-type, and is accordingly called
an nMOSFET or a pMOSFET. Figure 1 shows the schematic diagram of
the structure of an nMOS device before and after channel formation.

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Fig. (1a): nMOSFET before channel formation

Fig. (1b): nMOSFET structure after channel formation

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Figure 2 shows symbols commonly used for MOSFETs where the bulk
terminal is either labeled (B) or implied (not drawn).

Fig. (2): Circuit symbols for nMOS and pMOS respectively

Output Characteristics

MOSFET output characteristics plot ID versus VDS for several values of

VGS.

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The characteristics of an nMOS transistor can be explained as follows.

As the voltage on the top electrode increases further, electrons are
attracted to the surface. At a particular voltage level, which we will
shortly define as the threshold voltage, the electron density at the
surface exceeds the hole density. At this voltage, the surface has
inverted from the p-type polarity of the original substrate to an n-type
inversion layer, or inversion region, directly underneath the top plate as
indicated in Fig. 1(b). This inversion region is an extremely shallow
layer, existing as a charge sheet directly below the gate. In the MOS
capacitor, the high density of electrons in the inversion layer is supplied
by the electron–hole generation process within the depletion layer. The
positive charge on the gate is balanced by the combination of negative
charge in the inversion layer plus negative ionic acceptor charge in the
depletion layer. The voltage at which the surface inversion layer just
forms plays an extremely important role in field-effect transistors and is
called the threshold voltage Vtn. The region of output characteristics
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where VGS<vtn</v and no current flows is called the cutt-off region.

When the channel forms in the nMOS (pMOS) transistor, a positive
(negative) drain voltage with respect to the source creates a horizontal
electric field moving the electrons (holes) toward the drain forming a
positive (negative) drain current coming into the transistor. The positive
current convention is used for electron and hole current, but in both
cases electrons are the actual charge carriers. If the channel horizontal
electric field is of the same order or smaller than the vertical thin oxide
field, then the inversion channel remains almost uniform along the
device length. This continuous carrier profile from drain to source puts
the transistor in a bias state that is equivalently called either the non-
saturated, linear, or ohmic bias state. The drain and source are
effectively short-circuited. This happens when VGS > VDS + Vtn for
nMOS transistor and VGS < VDS +Vtp for pMOS transistor. Drain current
is linearly related to drain-source voltage over small intervals in the
linear bias state.

But if the nMOS drain voltage increases beyond the limit, so that VGS <
VDS + Vtn, then the horizontal electric field becomes stronger than the
vertical field at the drain end, creating an asymmetry of the channel
carrier inversion distribution shown in Figure 4.

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If the drain voltage riseswhile the gate voltage remains the same, then
VGD can go below the threshold voltage in the drain region. There can
be no carrier inversion at the drain-gate oxide region, so the inverted
portion of the channel retracts from the drain, and no longer “touches”
this terminal. The pinched-off portion of the channel forms a depletion
region with a high electric field. The n-drain and p-bulk form a pn
junction. When this happens the inversion channel is said to be
“pinched-off” and the device is in the saturation region. The
characteristics can be loosely modelled by the following equations.

Transfer Characteristics

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The transfer characteristic relates drain current (ID) response to the

input gate-source driving voltage (VGS). Since the gate terminal is
electrically isolated from the remaining terminals (drain, source, and
bulk), the gate current is essentially zero, so that gate current is not
part of device characteristics. The transfer characteristic curve can
locate the gate voltage at which the transistor passes current and
leaves the OFF-state. This is the device threshold voltage (Vtn). Figure 5
shows measured input characteristics for an nMOS and pMOS
transistor with a small 0.1V potential across their drain to source
terminals.

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The transistors are in their non-saturated bias states. As VGS increases

for the nMOS transistor in Figure 5a, the threshold voltage is reached
where drain current elevates. For VGS between 0V and 0.7V, ID is nearly
zero indicating that the equivalent resistance between the drain and
source terminals is extremely high. Once VGS reaches 0.7V, the current
increases rapidly with VGS indicating that the equivalent resistance at
the drain decreases with increasing gate-source voltage. Therefore, the
threshold voltage of the given nMOS transistor is about Vtn ≈ 0.7V. The
pMOS transistor input characteristic in Figure 5b is analogous to the
nMOS transistor except the ID and VGS polarities are reversed.

MOS Field-Effect-Transistors: Threshold voltage

Threshold voltage calculation

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The threshold voltage equals the sum of the flatband voltage, twice
the bulk potential and the voltage across the oxide due to the
depletion layer charge, or:

(7.4.1)

where the flatband voltage, VFB, is given by:

(7.4.2)

With

(7.4.3)

and

(7.4.4)

The threshold voltage of a p-type MOSFET with an n-type substrate is

obtained using the following equations:

(7.4.5)

where the flatband voltage, VFB, is given by:

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(7.4.6)

With

(7.4.7)

and

(7.4.8)

The threshold voltage dependence on the doping density is

illustrated with Figure 7.4.1 for both n-type and p-type MOSFETs
with an aluminum gate metal.

Figure Threshold voltage of n-type (upper curve) and p-type (lower curve)
7.4.1 : MOSFETs versus substrate doping density.

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The threshold of both types of devices is slightly negative at low doping

densities and differs by 4 times the absolute value of the bulk potential.
The threshold of nMOSFETs increases with doping while the threshold of
pMOSFETs decreases with doping in the same way. A variation of the
flatband voltage due to oxide charge will cause a reduction of both
threshold voltages if the charge is positive and an increase if the charge
is negative.

The substrate bias effect

The voltage applied to the back contact affects the threshold voltage of
a MOSFET. The voltage difference between the source and the
bulk, VBS changes the width of the depletion layer and therefore also the
voltage across the oxide due to the change of the charge in the
depletion region. This results in a modified expression for the threshold
voltage, as given by:

(7.4.9)

The threshold difference due to an applied source-bulk voltage can

therefore be expressed by:

(7.4.10)

Where g is the body effect parameter given by:

(7.4.11)

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The variation of the threshold voltage with the applied bulk-to-source

voltage can be observed by plotting the transfer curve for different
bulk-to-source voltages. The expected characteristics, as calculated
using the quadratic model and the variable depletion layer model, are
shown in Figure 7.4.2.

Figure Square root of ID versus the gate-source voltage as calculated using

7.4.2 : the quadratic model (upper curves) and the variable depletion layer
model (lower curves).

First, we observe that the threshold shift is the same for both models.
For a device biased at the threshold voltage, drain saturation is
obtained at zero drain-to-source voltage so that the depletion layer
width is constant along the channel. As the drain-source voltage at
saturation is increased, there is an increasing difference between the
drain current as calculated with each model. The difference however
reduces as a more negative bulk-source voltage is applied. This is due
to the larger depletion layer width, which reduces the relative variation

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of the depletion layer charge along the channel.

Example Calculate the threshold voltage of a silicon nMOSFET when

7.3 applying a substrate voltage, VBS = 0, -2.5, -5, -7.5 and -10 V.
The capacitor has a substrate doping Na = 1017 cm-3, a 20 nm
thick oxide (eox = 3.9 e0) and an aluminum gate (FM = 4.1 V).
Assume there is no fixed charge in the oxide or at the oxide-
silicon interface.

Solution The threshold voltage at VBS = -2.5 V equals:

Where the flatband voltage without substrate bias, VT0, was

already calculated in example 6.2. The body effect
parameter was obtained from:

The threshold voltages for the different substrate voltages

are listed in the table below.

NMOS Inverter

VLSI Design - MOS Inverter

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The inverter is truly the nucleus of all digital designs. Once its operation
and properties are clearly understood, designing more intricate
structures such as NAND gates, adders, multipliers, and
microprocessors is greatly simplified. The electrical behavior of these
complex circuits can be almost completely derived by extrapolating the
results obtained for inverters.

The analysis of inverters can be extended to explain the behavior of

more complex gates such as NAND, NOR, or XOR, which in turn form
the building blocks for modules such as multipliers and processors. In
this chapter, we focus on one single incarnation of the inverter gate,
being the static CMOS inverter — or the CMOS inverter, in short. This is
certainly the most popular at present and therefore deserves our
special attention.

Principle of Operation

The logic symbol and truth table of ideal inverter is shown in figure
given below. Here A is the input and B is the inverted output
represented by their node voltages. Using positive logic, the Boolean
value of logic 1 is represented by Vdd and logic 0 is represented by 0.
Vth is the inverter threshold voltage, which is Vdd /2, where Vdd is the
output voltage.

The output is switched from 0 to Vdd when input is less than Vth. So, for
0<Vin<Vth output is equal to logic 0 input and Vth<Vin< Vdd is equal to
logic 1 input for inverter.

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The characteristics shown in the figure are ideal. The generalized circuit
structure of an nMOS inverter is shown in the figure below.

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From the given figure, we can see that the input voltage of inverter is
equal to the gate to source voltage of nMOS transistor and output
voltage of inverter is equal to drain to source voltage of nMOS
transistor. The source to substrate voltage of nMOS is also called driver
for transistor which is grounded; so VSS = 0. The output node is
connected with a lumped capacitance used for VTC.

Resistive Load Inverter

The basic structure of a resistive load inverter is shown in the figure

given below. Here, enhancement type nMOS acts as the driver
transistor. The load consists of a simple linear resistor RL. The power
supply of the circuit is VDD and the drain current ID is equal to the load
current IR.

Circuit Operation

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When the input of the driver transistor is less than threshold voltage
VTH (Vin < VTH), driver transistor is in the cut – off region and does not
conduct any current. So, the voltage drop across the load resistor is
ZERO and output voltage is equal to the VDD. Now, when the input
voltage increases further, driver transistor will start conducting the
non-zero current and nMOS goes in saturation region.

Mathematically,

Increasing the input voltage further, driver transistor will enter into the
linear region and output of the driver transistor decreases.

VTC of the resistive load inverter, shown below, indicates the operating
mode of driver transistor and voltage points.

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Inverter with N type MOSFET Load

The main advantage of using MOSFET as load device is that the silicon
area occupied by the transistor is smaller than the area occupied by the
resistive load. Here, MOSFET is active load and inverter with active load
gives a better performance than the inverter with resistive load.

Enhancement Load NMOS

Two inverters with enhancement-type load device are shown in the

figure. Load transistor can be operated either, in saturation region or in
linear region, depending on the bias voltage applied to its gate
terminal. The saturated enhancement load inverter is shown in the fig.
(a). It requires a single voltage supply and simple fabrication process
and so VOH is limited to the VDD − VT.

The linear enhancement load inverter is shown in the fig. (b). It always
operates in linear region; so VOH level is equal to VDD.

Linear load inverter has higher noise margin compared to the saturated
enhancement inverter. But, the disadvantage of linear enhancement

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inverter is, it requires two separate power supply and both the circuits
suffer from high power dissipation. Therefore, enhancement inverters
are not used in any large-scale digital applications.

Depletion Load NMOS

Drawbacks of the enhancement load inverter can be overcome by using

depletion load inverter. Compared to enhancement load inverter,
depletion load inverter requires few more fabrication steps for channel
implant to adjust the threshold voltage of load.

The advantages of the depletion load inverter are - sharp VTC

transition, better noise margin, single power supply and smaller overall
layout area.

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As shown in the figure, the gate and source terminal of load are
connected; So, VGS = 0. Thus, the threshold voltage of the load is
negative. Hence,

VGS,load>VT,load

is satisfied

Therefore, load device always has a conduction channel regardless of

input and output voltage level.

When the load transistor is in saturation region, the load current is

given by

When the load transistor is in linear region, the load current is given by

The voltage transfer characteristics of the depletion load inverter is

shown in the figure given below −

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NMOS Inverter

NMOS Inverter

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CMOS Inverters

Introduction

CMOS inverters (Complementary NOSFET Inverters) are some of the

most widely used and adaptable MOSFET inverters used in chip design.
They operate with very little power loss and at relatively high speed.
Furthermore, the CMOS inverter has good logic buffer characteristics,
in that, its noise margins in both low and high states are large.

This short description of CMOS inverters gives a basic understanding of

the how a CMOS inverter works. It will cover input/output
characteristics, MOSFET states at different input voltages, and power
losses due to electrical current.

A CMOS inverter contains a PMOS and a NMOS transistor connected at

the drain and gate terminals, a supply voltage VDD at the PMOS source
terminal, and a ground connected at the NMOS source terminal, were
VIN is connected to the gate terminals and VOUT is connected to the

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drain terminals.(See diagram). It is important to notice that the CMOS

does not contain any resistors, which makes it more power efficient
that a regular resistor-MOSFET [Link] the voltage at the input of
the CMOS device varies between 0 and 5 volts, the state of the NMOS
and PMOS varies accordingly. If we model each transistor as a simple
switch activated by VIN, the inverter’s operations can be seen very
easily:

Transistor "switch model"

The switch model of the MOSFET transistor is defined as follows:

When VIN is low, the NMOS is "off", while the PMOS stays "on":
instantly charging VOUT to logic high. When Vin is high, the NMOS is
"on and the PMOS is "on: draining the voltage at VOUT to logic low.
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This model of the CMOS inverter helps to describe the inverter

conceptually, but does not accurately describe the voltage transfer
characteristics to any extent. A more full description employs more
calculations and more device states.

Multiple state transistor model

The multiple state transistor model is a very accurate way to model the
CMOS inverter. It reduces the states of the MOSFET into three modes
of operation: Cut-Off, Linear, and Saturated: each of which have a
different dependence on Vgs and Vds. The formulas which govern the
state and the current in that given state is given by the following tabel:

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In order to simplify calculations, use of an internet circuit simulation

device called "MoHAT." This tool allows the user to simulate circuits
containing a few transistors in a simple and visually appealing way. The
circuits shown below show the state of each transistor (black for cut-
off, red for linear, and green for saturation) accompanied by the
voltage transfer characteristic curve (VOUT vs. VIN). The vertical line
plotted on the VTC corresponds to the value of VIN on the circuit
diagram. The following series of diagrams depict the CMOS inverter in
varying input voltages ranging from low to high in ascending order.

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Power dissapation analysis of CMOS inverter

As mentioned before, the CMOS inverter shows very low power

dissipation when in proper operation. In fact, the power dissipation is
virtually zero when operating close to VOH and VOL. The following
graph shows the drain to source current (effectively the overall current
of the inverter) of the NMOS as a function of input voltage. Note that
the current in the far left and right regions (low and high VIN
respectively) have low current, and the peak current in the middle is
only .232mA (a 1.16mW power dissipation).

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Conclusion

The CMOS inverter is an important circuit device that provides quick

transition time, high buffer margins, and low power dissipation: all
three of these are desired qualities in inverters for most circuit design.
It is quite clear why this inverter has become as popular as it is.

Charge Coupled Device (CCD)

Charge Coupled Devices can be defined in different ways according to

the application for which they are used or based on the design of the
device.

It is a device used for the movement of electrical charge within it for

the charge manipulation, which is done by changing the signals through
stages within the device one at a time.

It can be treated as CCD sensor, which is used in the digital and video
cameras for taking images and recording videos through photoelectric

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effect. It is used for converting the captured light into digital data,
which is recorded by the camera.

It can be defined as a light-sensitive integrated circuit imprinted on a

silicon surface to form light-sensitive elements called pixels, and each
pixel is converted into an electrical charge.

It is termed as a discrete-time device used for continuous or analog

signal sampling at discrete times.

A charge-coupled device (CCD) is a light-sensitive integrated circuit that

stores and displays the data for an image in such a way that
each pixel (picture element) in the image is converted into an electical
charge the intensity of which is related to a color in the color spectrum.
For a system supporting 65,535 colors, there will be a separate value
for each color that can be stored and recovered. CCDs are now
commonly included in digital still and video cameras. They are also used
in astronomical telescopes, scanners, and bar code readers. The devices
have also found use in machine vision for robots, in optical character
recognition (OCR), in the processing of satellite photographs, and in the
enhancement of radar images, especially in meteorology.

A CCD in a digital camera improves resolution compared with older

technologies.

Some digital cameras produce images having more than one million
pixels, yet sell for under $1,000. The term megapixel has been coined in
reference to such cameras. Sometimes a camera with an image of
1,024 by 768 pixels is given the label "megapixel," even though it
technically falls short of the mark.

Another asset of the CCD is its high degree of sensitivity.

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A good CCD can produce an image in extremely dim light, and its
resolution does not deteriorate when the illumination intensity is low,
as is the case with conventional cameras.

The CCD was invented in 1969 at Bell Labs, now part of Lucent
Technologies, by George Smith and Willard Boyle.

Types of Charge-Coupled Devices with their Working Principles

The scientists Williard Boyle and George E. Smith from AT&T Bell Labs,
while working on semiconductor -bubble-memory designed a device,
and termed it as ‘Charge Bubble Device’, which can be used as a Shift
Register.

Charge Coupled Device

According to the fundamental nature of the device, it has the ability to

transfer charge from one storage capacitor to the next, along the
surface of the semiconductor, and this principle is similar to the Bucket-
Brigade Device (BBD), which was invented in the 1960s at Phillips
Research Labs. Eventually, from all such experimental research
activites, the Charge Coupled Device (CCD) was invented in AT&T Bell
Labs in 1969.

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Types of CCD

There are different CCDs such as electron multiplying CCDs, intensified

CCD, frame-transfer CCD and buried-channel CCD. A CCD can be simply
defined as Charge Transfer Device. The inventors of the CCD, Smith and
Boyle also discovered a CCD with greatly enriched performance than a
general Surface Channel CCD and other CCDs; it is known as Buried
channel CCD and is majorly used for practical applications.

Charge Coupled Device’s Working Principle

The silicon epitaxial layer acting as a photoactive region and a shift-

register-transmission region are used for capturing images using a CCD.

Through the lens image is projected onto the photo active region
consisting of capacitor array. Thus, the electric charge proportional to
the light intensity of the image pixel color in the color spectrum at that
location is accumulated at each capacitor.

If the image gets detected by this capacitor array, then the electrical
charge accumulated in each capacitor is transferred to its neighbor
capacitor by performing as a shift register controlled by the control
circuit.

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Working of Charge Coupled Device

In the above figure, from a, b and c, the transfer of charge packets is

shown according to the voltage applied to the gate terminals. At last, in
the array electrical charge of last capacitor is transferred into the
charge amplifier in which the electric charge is converted into a voltage.
Thus, from the continuous operation of these tasks, entire charges of
the capacitor array in the semiconductor are converted into a sequence
of voltages.

This sequence of voltages is sampled, digitized and then stored in

memory in case of digital devices such as digital cameras. In case of
analog devices such as analog video cameras, this sequence of voltages
is fed to a low-pass filter to produce a continuous analog signal, and
then the signal is processed for transmission, recording and for other
purposes. To understand the charge coupled device principle and
charge coupled device working in depth, primarily the following
parameters need to be understood.

Charge Transfer Process

The charge packets can be moved from cell to cell by using many
schemes in Bucket Brigade style. There are various techniques such as
two phase, three phase, four phase, and so on. Every cell consists of n-
wires passing through it in n-phase scheme. The height of the potential
wells is controlled by using each wire connected to transfer clock.
Charge packets can be pushed and pulled along the line of the CCD by
varying the height of the potential well.

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Charge Transfer Process

Consider a three-phase charge transfer, in the above figure, the three

clocks (C1, C2 and C3) which are identical in shape but in different
phases are shown. If gate B goes high and gate A goes low, then the
charge will move from space A to space B.

Architecture of CCD

The pixels can be transferred through the parallel vertical registers or

vertical CCD (V-CCD) and parallel horizontal registers or horizontal CCD
(H-CCD). The charge or image can be transferred using different
scanning architectures such as full frame readout, frame transfer and
interline transfer. The charge coupled device principle can be easily
understandable with the following transfer schemes:

1. Full-Frame Readout

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Full Frame Readout

It is the simplest scanning architecture which requires a shutter in a

number of applications to cut off the light input and to avoid smearing
during the passage of charges through parallel-vertical registers or
vertical CCD and parallel-horizontal registers or horizontal CCD and
then transferred to output in serial.

2. Frame Transfer

Frame Transfer

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By using the bucket brigade process the image can be transferred from
image array to opaque frame storage array. As it does not use any serial
register, it is a fast process compared to other processes.

3. Interline transfer

Interline Transfer

Each pixel consists of a photodiode and opaque charge storage cell. As

shown in the figure, the image charge is first transferred from light
sensitive PD to the opaque V-CCD. This transfer, as the image is hidden,
in one transfer cycle produces a minimum image smear; hence, the
fastest optical shuttering can be achieved.

MOS Capacitor of CCD

Every CCD cell has metal oxide semiconductor, even though both
surface channel and buried channel MOS capacitors are used in
manufacturing the CCD. But frequently CCDs are fabricated on a P-
type substrate and manufactured by using buried channel MOS
capacitors; for this a thin N-type region is formed on its surface. A
silicon dioxide layer is grown as an insulator on the top of the N-region,

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and gates are formed by placing one or more electrodes on this

insulating layer.

CCD Pixel

Free electrons are formed from photoelectric effect when the photons
strike the silicon surface, and because of the vacuum, simultaneously,
positive charge or the hole will be generated. Instead of choosing
difficult process of counting the thermal fluctuations or heat formed by
the recombining of hole and electron, it is preferred to collect and
count electrons to produce an image. This can be achieved by attracting
electrons generated by striking photons on silicon surface towards the
positively biased distinct areas.

CCD Pixel

Full well capacity can be defined as the maximum number of electrons

that can be held by each CCD pixel and, typically, a CCD pixel can hold
10ke to 500ke, but it depends on the size of the pixel (the bigger the
size more electrons can be accumulated).

CCD Cooling

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CCD Cooling

Generally CCDs work at low temperature, and thermal energy can be

used for exciting inappropriate electrons into image pixels which
cannot be differentiated from the real-image photoelectrons. It is called
as a dark current process, which generates noise. The total dark current
generation can be reduced by two times for every 6 to 70 of cooling
with certain limits. The CCDs do not work below -1200 and the total
noise generated from the dark current can be removed by cooling it
around -1000, by thermally isolating it in an evacuated environment.
CCDs are frequently cooled by using liquid nitrogen, thermo-electric
coolers and mechanical pumps.

Quantum Efficiency of CCD

The rate of generation of photoelectrons depends on the light incident

on the surface of the CCD. The conversion of the photons into electric
charge is contributed by many factors and is termed as Quantum
Efficiency. It is in the better range of 25% to 95% for CCDs compared to
other light- detection technique.
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Quantum Efficiency of Front Illuminated Device

The front- illuminated device generates a signal after the light passes
through the gate structure by attenuating the incoming radiation.

Quantum Efficiency of Back Illuminated Device

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The back-illuminated or back-thinned CCD consists of excess silicon on

the underside of the device, which is imprinted in a way that
unrestrictedly allows generation of photoelectrons.

CCD Detector

A CCD or Charge Coupled Device is a highly sensitive photon detector. It

is divided up into a large number of light-sensitive small areas known as
pixels, which can be used to assemble an image of the area of interest.

A CCD is a silicon-based multi-channel array detector of UV, visible and

near-infra light. These are used for spectroscopy, since they are
extremely sensitive to light. That makes these detectors suitable for
analysis of the inherently weak Raman signal. It also allows multi-
channel operation, meaning the entire spectrum can be detected in a
single acquisition.

CCDs are widely used beyond sensors in digital cameras. Versions that
are used for scientific spectroscopy are of a considerably higher grade,
to give the best possible sensitivity, uniformity, and noise
characteristics.

CCD detectors are typically one dimensional, referred to as linear, or

two dimensional, referred to as area arrays of thousands or millions of
individual detector elements. Those elements are known as pixels.
Each element interacts with light to build up a charge. The brighter the
light, and/or the longer the interaction, the more charge is registered.
At the end of the measurement, readout electronics pull the charge
from the elements, and each individual charge reading is measured.

In a typical Raman spectrometer, the Raman scattered light is dispersed

using a diffraction grating. This dispersed light is projected onto the
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long axis of the CCD array. The first element will detect light from the
low cm-1 edge of the spectrum. The second element will detect light
from the next spectral position, and so on. The last element will detect
light from the high cm-1 edge of the spectrum.

CCDs require some degree of cooling to make them suitable for high-
grade spectroscopy. This is typically done using either Peltier cooling,
which is suitable for temperatures down to -90oC, and liquid nitrogen
cryogenic cooling. Most Raman systems use Peltier cooled detectors,
but liquid nitrogen cooled detectors still have advantages for certain
specialized applications.

Electron Multiplying Charge-Coupled Device (EMCCD)

An Electron Multiplying Charge-Coupled Device (EMCCD) is an image

sensor. It is able to detect single photon events without an image
intensifier, using a unique electron multiplying structure built into the
chip.

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EMCCD cameras are designed to overcome a fundamental physical

constraint to deliver high sensitivity with high speed. Traditional CCD
cameras offered high sensitivity, with low readout noises, but at the
expense of slow readout. These were often referred to as ‘slow scan’
cameras.

EMCCD overcame this by amplifying the signal. That means that the
readout noise is effectively by-passed and is no longer is a limit on
sensitivity.

What distinguishes EMCCD technology is the addition of a specialized

extended serial register on the CCD chip. It produces multiplication gain
through the process of impact ionization in silicon.

When photons are scarce, the signal reaching the imaging device may
be weak enough to blend with the background noise. EMCCD
technology is designed to reduce the inherent electronic noise of the
readout process.

EMCCD cameras overcome most low light imaging. These detectors also
support faster frame acquisition rates than their CCD counterparts,
making them highly suitable for live imaging. Additionally, EMCCD
cameras can offer ultimate sensitivity for the observation of the darkest
scenes. It accomplishes this by becoming wide-field real-time photon-
counting imaging devices.

CCD operation

The basics

A Charge Coupled Device (CCD) is a highly sensitive photon detector.

The CCD is divided up into a large number of light-sensitive small areas

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(known as pixels) which can be used to build up an image of the scene

of interest. A photon of light which falls within the area defined by one
of the pixels will be converted into one (or more) electrons and the
number of electrons collected will be directly proportional to the
intensity of the scene at each pixel. When the CCD is clocked out, the
number of electrons in each pixel are measured and the scene can be
reconstructed.

The picture here shows a "typical" CCD. The CCD itself is primarily made
of silicon and the structure has been altered so that some of the silicon
atoms have been replaced with impurity atoms.

The figure below shows a very simplified cross section through a CCD. It
can be seen that the Silicon itself is not arranged to form individual
pixels. In fact, the pixels are defined by the position of electrodes
above the CCD itself. If a positive voltage is applied to the electrode,
then this positive potential will attract all of the negatively charged
electrons close to the area under the electrode. In addition, any
positively charged holes will be repulsed from the area around the
electrode. Consequently a "potential well" will form in which all the
electrons produced by incoming photons will be stored.

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As more and more light falls onto the CCD, then the potential well
surrounding this electrode will attract more and more electrons until
the potential well is full (the amount of electrons that can be stored
under a pixel is known as the full well capacity). To prevent this
happening the light must be prevented from falling onto the CCD for
example, by using a shutter as in a camera. Thus, an image can be made
of an object by opening the shutter, "integrating" for a length of time to
fill up most of the electrons in the potential well, and then closing the
shutter to ensure that the full well capacity is not exceeded.

An actual CCD will consist of a large number of pixels (i.e, potential

wells), arranged horizontally in rows and vertically in columns. The
number of rows and columns defines the CCD size, typical sizes are
1024 pixels high by 1024 pixels wide. The resolution of the CCD is
defined by the size of the pixels, also by their separation (the pixel
pitch). In most astronomical CCDs the pixels are touching each other
and so the CCD resolution will be defined by the pixel size, typically 10-
20µm. Thus, a 1024x1024 sized CCD would have a physical area image
size of about 10mm x 10mm.

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How is a CCD clocked out?

The figure below shows a cross section through a row of a CCD. Each
pixel actually consists of three electrodes IØ1, IØ2, and IØ3. Only one of
these electrodes is required to create the potential well, but other
electrodes are required to transfer the charge out of the CCD. The
upper section of the figure (section 1) shows charge being collected
under one of the electrodes. To transfer the charge out of the CCD, a
new potential well can be created by holding IØ3 high, the charge is
now shared between IØ2 and IØ3 (section 2). If IØ2 is now taken low,
the charge will be fully transferred under electrode IØ3 (section 3). To
continue clocking out the CCD, taking IØ1 high and then taking IØ3 low
will ensure that the charge cloud now drifts across under the IØ1
electrodes. As this process is continued, the charge cloud will progress
either down the column, or across the row, depending upon the
orientation of the electrodes.

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The figure below (called a clocking diagram) shows the progression

under which each electrode is held high and low to ensure that charge
is transferred through the CCD.

Initially, IØ2 is high - usually to around 12V, and the charge is held
under that electrode as in (1) previously. When IØ3 is held high, and
IØ2 is taken low (usually 0 V), the charge migrates under the IØ3
electrode (as in (2)). Finally, taking IØ1 high and IØ3 low transfers the
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charge under IØ1 (as in (3)). This process is repeated in transfer 2 and
transfer 3, the charge has now been moved three pixels along. This
process is known as charge coupling (hence CCD).

For most of the CCD, the electrodes in each pixel are arranged so that
the charge is transferred downwards along the columns. Hence, during
the CCD clocking operation, rows are transferred downwards to the
final row (the readout register) which is used to transfer the charge in
each pixel out of the CCD so it can be measured.

In the read out register, the electrodes are arranged so that the charge
is transferred in the horizontal direction, along the readout register.

How the charge is measured

The final process on the CCD is the reading of each pixel so that the size
of the associated charge cloud can be measured. At the end of the
readout register is an amplifier which measure the value of each charge
cloud and converts it into a voltage, a typical conversion factor being

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around 5-10µV per electron with "typical" full well values being about
100,000 electrons or so.

A CCD camera will consist of the CCD chip, and associated electronics,
which is used at this point to amplify the small voltage on the CCD,
remove noise components, digitise the pixel values and output the
values of each pixel for example, to a PC, where the image can be
processed in software and the image displayed. The CCD is an analogue
device, and the analogue voltage values are converted into a digital
form by the camera electronics.

Some aspects of CCD behaviour

Quantum Efficiency

Not every photon falling onto a detector will actually be detected and
converted into an electrical impulse. The percentage of photons that
are actually detected is known as the Quantum Efficiency (QE). For
example, the human eye only has a QE of about 20%, photographic film
has a QE of around 10%, and the best CCDs can achieve a QE of over
80%. Quantum efficiency will vary with wavelength.

Wavelength range

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CCDs can have a wide wavelength range ranging from about 400nm
(blue) to about 1050nm (Infra-red) with a peak sensitivity at around
700nm. However, using a process known as backthinning, it is possible
to extend the wavelength range of a CCD down into shorter
wavelengths such as the Extreme Ultraviolet and X-ray.

Dynamic Range

The ability to view bright and faint sources correctly in the same image
is a very useful property of a detector. The difference between a
brightest possible source and the faintest possible source that the
detector can accurately see in the same image is known as the dynamic
range. When light falls onto a CCD the photons are converted into
electrons. Consequently, the dynamic range of a CCD is usually
discussed in terms of the minimum and maximum number of electrons
that can be imaged. As more light falls onto the CCD, more and more
electrons are collected in a potential well, and eventually no more
electrons can be accommodated within the potential well and the pixel
is said to be saturated. For a typical scientific CCD this may occur at
around 150,000 electrons or so. The minimum signal that can be
detected is not necessarily one electron (corresponding to one photon
at visible wavelengths). In fact, there is a minimum amount of
electronic noise which is associated with the physical structure of the
CCD and is usually around 2-4 electrons for each pixel. Thus, the
minimum signal that can be detected is determined by this readout
noise.

In the example above, the CCD would have a dynamic range of

150,000:4 (taking the upper noise level). But - this dynamic range is also

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dependent on the ability of the electronics to be able fully digitise all of

this dynamic range.

Linearity

On the whole, the eye is not a linear detector (except over very small
variations in intensity) and has a logarithmic response. An important
consideration in a detector is its ability to respond linearly to any image
it views. By this we mean that if it detects 100 photons it will convert
these to 100 electrons (if we had 100% QE) and if it detects 10000
photons, it will convert these to 10000 electrons. In such a situation, we
say that the detector has a linear response. Such a response is
obviously very useful as there is no need for any additional processing
on the image to determine the 'true' intensity of different objects in an
image.

Noise

One of the most important aspects of CCD performance is its noise

response. There are a number of contributions to the noise
performance of a CCD, these are briefly listed here:

 Dark current - i.e thermally generated noise. At room

temperature, the noise performance of a CCD can be as much as
thousands of electrons per pixel per second. Consequently, the
full well capacity of each pixel will be reached in a few seconds
and the CCD will be saturated. Dark current can be massively
reduced by cooling. For example, the noise performance of the
CCD could be reduced from thousands of electrons at room
temperature to only tens of electrons per pixel per second at -40
degrees C. By cooling down to temperatures below about -70

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degrees C dark current can be virtually eliminated (substantially

below one electron per pixel per second). A second way of
reducing noise is to slightly alter the CCD processing technique to
produce a Multi-Pinned -Phase (MPP) CCD. This technique can
reduce the dark current to very low levels (a few hundred
electrons per pixel per second at room temperature).

 Readout noise - the ultimate noise limit of the CCD is the readout
noise. The readout noise originates from the conversion of the
electrons in each pixel to a voltage on the CCD output node (a
typical value would be around 4µV per electron). The magnitude
of this noise depends on the size of the output node. A large
amount of effort has been dedicated to reducing the CCD readout
noise, as this noise value will ultimately determine the dynamic
range and should be as low as possible, particularly when
detecting very faint sources for example, detecting photons at X
ray energies such as in the XMM-Newton mission. Noise values of
2-3 electrons rms (root mean square) are now typical for many
CCDs but some companies have recently claimed a noise
resolution of under 1 electron rms.

When the CCD is used as part of a camera for astronomical imaging,

other sources of noise must also be included such as the random (shot)
noise present on the image itself, along with noise introduced by the
camera electronics. However, these noise sources are discussed
elsewhere.

Power

CCDs themselves consume very little power. During integration, only a

very small current is flowing and the CCD consumes only 50mW or so.
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Whilst the CCD is being clocked out more power can be consumed but
this is typically only several Watts or so. Of course, the electronics
required to operate the CCD and process images can consume much
more power.

Why are scientific CCDs so expensive ?

A Video camera using a CCD can be bought for as little as 400-500

pounds. However, a scientific grade CCD may cost up to 100 times this
price, sometimes more. Some of the reasons why scientific CCDs are
much more expensive than CCDs in consumer electronics are outlined
below:

Cost and complexity

Scientific grade CCDs are much more expensive than the basic type of
CCDs that are usually found in devices such as commercially available
Video cameras. Commercially available video cameras normally have a
number of disadvantages that make them unsuitable for scientific use.
For example:

 Commercial CCDs may contain a larger number of defects and

blemishes which will degrade the image quality. For the sort of
images usually viewed by a video camera these blemishes are not
a problem as they can be removed by software in the camera. For

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scientific use however, the image quality would be unacceptably

degraded;

 The noise of commercial CCDs and their camera systems is much

higher than for specially built scientific systems;

 The dynamic range of the camera system is much lower than for
scientific cameras.

Charge Coupled Device (CCD) – Applications

 Astronomy

CCD’s are used in astronomy because of their high linearity in outputs.

CCD is used in all the astronomical Ultra violet and infrared
applications. They are also highly efficient in quantum applications.
Though the CCD characteristics may be affected by thermal noise and
cosmic rays, astronomers have taken several counter measures to
reduce this. One method includes the timing of the CCD shutter. With
the shutter closed the number of images taken will determine the
random noise. After tking the mage with the shutter closed, the result
is then differed with the open-shutter image so as to remove the dead
and hot pixels.

Application in astronomy also includes a method called drift scanning.

This method is mainly used to follow the motion of the sky. This is done
by converting a fixed telescope into a tracking telescope with the
application of CCD.

 Colour Cameras

For the use of CCD in cameras, a much more advanced for called 3CCD
is used commonly. By using 3CCD devices, the colour separation
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becomes much improved, thus increasing the quantum efficiency as

well. The image resolution of a camera completely depends on the CCD
chip. When the photons hit the sensor, the sensor counts their number.
So, the brighter the image at a given point on the sensor, the larger the
value that is ready for that pixel.

HISTORY

Invention of CCD – Smith & Boyle 1969

As the story goes, George Smith and Willard Boyle were working in a
Bell Labs group interested in creating a new kind of semiconductor
memory for computers[6]. Also great hope was then held for the video
telephone service, which needed inexpensive solid-state cameras. On
October 17, 1969 Smith and Boyle mapped out the plan for what was to
become the miracle we know of as the CCD. On that fateful day in 1969
Smith and Boyle not only described the basic structure and principles of
operation, they also predicted its applications in imaging as well as
memory.

Buried channel CCD – Smith & Boyle 1974

Smith and Boyle are also credited with inventing the buried channel
CCD, which greatly enhanced the performance of the original surface
channel CCD[6]. As a result of the work of researchers like Smith and
Boyle, Bell-Labs now holds many of the relevant patents for charge-
coupled devices.

Early Video Camera Developments 1970 and 1975

Using the Smith & Boyle CCD, Bell Labs researchers built the world's
first solid-state video camera in 1970[6]. In 1975, they demonstrated

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the first solid-state camera with image quality sharp enough for
broadcast television.

CCD’s Replace Photographic Plates in Telescopes 1983

In the beginning astronomers looked though telescopes with their eyes.

Later photographic plates and film generally took over for serious work.
In 1983, telescopes were first outfitted with CCD cameras. For the last
ten years we have been receiving amazing pictures from the Hubble
Space Telescope’s CCD cameras.

Digital Cameras Invade the Consumer Market 1995

CCD still cameras have been around since about 1985. In 1991 Kodak
released the first professional digital camera system (DCS), aimed at
photojournalists. It was a Nikon F-3, 35 millimeter, camera equipped by
Kodak with a 1.3 mega-pixel CCD sensor. By 1995, inexpensive, high
resolution CCDs made possible the consumer digital cameras that are
ubiquitous today.

VLSI Design

VLSI chiefly comprises of Front End Design and Back End design these
days. While front end design includes digital design using HDL, design
verification through simulation and other verification techniques, the
design from gates and design for testability, backend design comprises
of CMOS library design and its characterization. It also covers the
physical design and fault simulation.

Very-large-scale integration (VLSI) is the process of creating

an integrated circuit (IC) by combining thousands of transistors into a
single chip. VLSI began in the 1970s when

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complex semiconductor and communication technologies were being

developed. The microprocessor is a VLSI device.

Before the introduction of VLSI technology, most ICs had a limited set
of functions they could perform. An electronic circuit might consist of
a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of
these into one chip.

The electronics industry has achieved a phenomenal growth over the

last few decades, mainly due to the rapid advances in large scale
integration technologies and system design applications. With the
advent of very large scale integration (VLSI) designs, the number of
applications of integrated circuits (ICs) in high-performance computing,
controls, telecommunications, image and video processing, and
consumer electronics has been rising at a very fast pace.

The current cutting-edge technologies such as high resolution and low

bit-rate video and cellular communications provide the end-users a
marvelous amount of applications, processing power and portability.
This trend is expected to grow rapidly, with very important implications
on VLSI design and systems design.

While Simple logic gates might be considered as SSI devices and

multiplexers and parity encoders as MSI, the world of VLSI is much
more diverse. Generally, the entire design procedure follows a step by
step approach in which each design step is followed by simulation
before actually being put onto the hardware or moving on to the next
step. The major design steps are different levels of abstractions of the
device as a whole:

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1. Problem Specification: It is more of a high level representation of

the system. The major parameters considered at this level are
performance, functionality, physical dimensions, fabrication technology
and design techniques. It has to be a tradeoff between market
requirements, the available technology and the economical viability of
the design. The end specifications include the size, speed, power and
functionality of the VLSI system.

2. Architecture Definition: Basic specifications like Floating point

units, which system to use, like RISC (Reduced Instruction Set
Computer) or CISC (Complex Instruction Set Computer), number of
ALU’s cache size etc.

3. Functional Design: Defines the major functional units of the

system and hence facilitates the identification of interconnect
requirements between units, the physical and electrical specifications
of each unit. A sort of block diagram is decided upon with the number
of inputs, outputs and timing decided upon without any details of the
internal structure.

4. Logic Design: The actual logic is developed at this level. Boolean

expressions, control flow, word width, register allocation etc. are
developed and the outcome is called a Register Transfer Level (RTL)
description. This part is implemented either with Hardware Descriptive
Languages like VHDL and/or Verilog. Gate minimization techniques are
employed to find the simplest, or rather the smallest most effective
implementation of the logic.

5. Circuit Design: While the logic design gives the simplified

implementation of the logic,the realization of the circuit in the form of
a netlist is done in this step. Gates, transistors and interconnects are
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put in place to make a netlist. This again is a software step and the
outcome is checked via simulation.

6. Physical Design: The conversion of the netlist into its geometrical

representation is done in this step and the result is called a layout. This
step follows some predefined fixed rules like the lambda rules which
provide the exact details of the size, ratio and spacing between
components. This step is further divided into sub-steps which are:

6.1 Circuit Partitioning: Because of the huge number of transistors

involved, it is not possible to handle the entire circuit all at once due to
limitations on computational capabilities and memory requirements.
Hence the whole circuit is broken down into blocks which are
interconnected.

6.2 Floor Planning and Placement: Choosing the best layout for each
block from partitioning step and the overall chip, considering the
interconnect area between the blocks, the exact positioning on the chip
in order to minimize the area arrangement while meeting the
performance constraints through iterative approach are the major
design steps taken care of in this step.

6.3 Routing: The quality of placement becomes evident only after this
step is completed. Routing involves the completion of the
interconnections between modules. This is completed in two steps.
First connections are completed between blocks without taking into
consideration the exact geometric details of each wire and pin. Then, a
detailed routing step completes point to point connections between
pins on the blocks.

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6.4 Layout Compaction: The smaller the chip size can get, the better it
is. The compression of the layout from all directions to minimize the
chip area thereby reducing wire lengths, signal delays and overall cost
takes place in this design step.

6.5 Extraction and Verification: The circuit is extracted from the layout
for comparison with the original netlist, performance verification, and
reliability verification and to check the correctness of the layout is done
before the final step of packaging.

7. Packaging: The chips are put together on a Printed Circuit Board

or a Multi Chip Module to obtain the final finished product.

Initially, design can be done with three different methodologies which

provide different levels of freedom of customization to the
programmers. The design methods, in increasing order of
customization support, which also means increased amount of
overhead on the part of the programmer, are FPGA and PLDs, Standard
Cell (Semi Custom) and Full Custom Design.

While FPGAs have inbuilt libraries and a board already built with
interconnections and blocks already in place; Semi Custom design can
allow the placement of blocks in user defined custom fashion with
some independence, while most libraries are still available for program
development. Full Custom Design adopts a start from scratch approach
where the programmer is required to write the whole set of libraries
and also has full control over the block development, placement and
routing. This also is the same sequence from entry level designing to
professional designing.

Basics of VLSI Design

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Very-large-scale integration (VLSI) is the process of creating

an integrated circuit (IC) by combining thousands of transistors into a
single chip. VLSI began in the 1970s when
complex semiconductor and communication technologies were being
developed. The microprocessor is a VLSI device.

Before the introduction of VLSI technology, most ICs had a limited set
of functions they could perform. An electronic circuit might consist of
a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of
these into one chip.

The electronics industry has achieved a phenomenal growth over the

last few decades, mainly due to the rapid advances in large scale
integration technologies and system design applications. With the
advent of very large scale integration (VLSI) designs, the number of
applications of integrated circuits (ICs) in high-performance computing,
controls, telecommunications, image and video processing, and
consumer electronics has been rising at a very fast pace.

The current cutting-edge technologies such as high resolution and low

bit-rate video and cellular communications provide the end-users a
marvelous amount of applications, processing power and portability.
This trend is expected to grow rapidly, with very important implications
on VLSI design and systems design.

VLSI Design Flow

The VLSI IC circuits design flow is shown in the figure below. The
various levels of design are numbered and the blocks show processes in
the design flow.

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Specifications comes first, they describe abstractly, the functionality,

interface, and the architecture of the digital IC circuit to be designed.

Behavioral description is then created to analyze the design in terms of

functionality, performance, compliance to given standards, and other
specifications.

RTL description is done using HDLs. This RTL description is simulated to

test functionality. From here onwards we need the help of EDA tools.

RTL description is then converted to a gate-level netlist using logic

synthesis tools. A gatelevel netlist is a description of the circuit in terms
of gates and connections between them, which are made in such a way
that they meet the timing, power and area specifications.

Finally, a physical layout is made, which will be verified and then sent to
fabrication.

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Y Chart

The Gajski-Kuhn Y-chart is a model, which captures the considerations

in designing semiconductor devices.

The three domains of the Gajski-Kuhn Y-chart are on radial axes. Each
of the domains can be divided into levels of abstraction, using
concentric rings.

At the top level (outer ring), we consider the architecture of the chip; at
the lower levels (inner rings), we successively refine the design into
finer detailed implementation −

Creating a structural description from a behavioral one is achieved

through the processes of high-level synthesis or logical synthesis.

Creating a physical description from a structural one is achieved

through layout synthesis.

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Design Hierarchy-Structural

The design hierarchy involves the principle of "Divide and Conquer." It

is nothing but dividing the task into smaller tasks until it reaches to its
simplest level. This process is most suitable because the last evolution
of design has become so simple that its manufacturing becomes easier.

We can design the given task into the design flow process's domain
(Behavioral, Structural, and Geometrical). To understand this, let’s take
an example of designing a 16-bit adder, as shown in the figure below.

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Here, the whole chip of 16 bit adder is divided into four modules of 4-
bit adders. Further, dividing the 4-bit adder into 1-bit adder or half
adder. 1 bit addition is the simplest designing process and its internal
circuit is also easy to fabricate on the chip. Now, connecting all the last
four adders, we can design a 4-bit adder and moving on, we can design
a 16-bit adder.

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Stick Diagrams

A stick diagram is a kind of diagram which is used to plan the layout of a

transistor cell. The stick diagrams uses "sticks" or lines to represent the
devices and conductors.

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 VLSI design aims to translate circuit concepts onto silicon.

 stick diagrams are a means of capturing topography and layer
information using simple diagrams.
 Stick diagrams convey layer information through colour codes (or
monochrome encoding).
 Acts as an interface between symbolic circuit and the actual
layout.
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 Does show all components/vias.

 It shows relative placement of components.
 Goes one step closer to the layout
 Helps plan the layout and routing

 Does not show

 Exact placement of components

 Transistor sizes
 Wire lengths, wire widths, tub boundaries.
 Any other low level details such as parasitics..

Stick Diagrams – Notations

Metal
1

Stick Diagrams – Rules

Rule 1. When two or more ‘sticks’ of the same type cross or touch each
other that represents electrical contact.

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Rule 2. When two or more ‘sticks’ of different type cross or touch each
other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).

Rule 3. When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff

with n-diff. All pMOS must lie on one side of the line and all nMOS will
have to be on the other side.

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How to draw Stick Diagrams

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Layout design rules

Layout design rules are introduced in order to create reliable and

functional circuits on a small area. Main terms in design rules are
feature size (width), separation and overlap. Design rules does
represent geometric limitations for for an engineer to create correct
topology and geometry of the design.

The layout design rules provide a set of guidelines for constructing the
various masks needed in the fabrication of integrated circuits. Design
rules are consisting of the minimum width and minimum spacing
requirements between objects on the different layers.

The most important parameter used in design rules is the minimum line
width. This parameter indicates the mask dimensions of the
semiconductor material layers. Layout design rules are used to
translate a circuit concept into an actual geometry in silicon.

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The design rules is the media between circuit engineer and the IC
fabrication engineer. The Circuit designers requires smaller designs with
high performance and high circuit density whereas the IC fabrication
engineer requires high yield process.

Minimum line width (MLW) is the minimum MASK dimension that can
be safely transferred to the semiconductor material. For the minimum
dimension design rules differ from company to company and from
process to process.

m.' equals 0.125 m process technology ' e.g. for a 0.25 ' is set to a
value and the design dimensions are converted in the form of numbers.
Typically a minimum line width of a process is set to 2'. For an IC
process 'To address this issue scalable design rule approach is used. In
this approach rules are defined as a function of single parameter called'

Layered Representation of Layout:

The layer representation of layout converts the masks used in CMOS

into a simple layout levels that are easier to visualise by the designers.
The CMOS design layouts are based on following components :

(1) Substrates or Wells: These wells are p type for NMOS

devices and n type for PMOS devices.
(2) Diffusion regions: At these regions the transistors are
formed and also called as active layer. These are defined by
n+ for NMOS and p+ for PMOS transistors.
(3) Polysilicon layers: These are used to form the gate
electrodes of the transistors.

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(4) Metal interconnects layers : These are used to form the

power supply and ground rails as well as input and output
rails.
(5) Contact and Via layers : These are used to form the inter
layer connections.

Design rules are based on MOSIS rules. The main term of MOSIS rules is
parameter.

There is several levels of design rules:

 well rules;
 transistor rules;
 contact rules;
 metal rules;
 via rules;
 other rules.

Layout design rules: Well rules

 N-well is deeper mounted than any other transistor implants.

Clearance between n-well edges and n+ diffusion should be good
enough.

 This clearance is usually determined by the oxide transition time

across the well boundary.

 The other rule is grounding n-well, providing sufficient number of

well taps. This will prevent significant voltage drops due to well
current.

Layout design rules: Transistor rules

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Transistor is designed with at least for masks:

 active mask – defines where p- or n-diffusion type or gates will

be placed;
 n-implant mask – defines areas where n-type diffusion is
required; n-type diffusion in p-wells define nMOS transistors;
p-type diffusion in n-wells defines pMOS transistors;
 p-implant mask – defines where p-type diffusion is required;p-
type diffusion in n-wells define n-type contacts.; p-type
diffusion in p-wells define p-well contacts
 polysilicon mask – crossing of polysilicon and diffusion mask
defines the gates of transistor.

Polysilicon mask should cover active mask and extend beyond that
area, otherwise transistor will be shorted with the diffusion path
between source and drain. Crossing of polisilicon and active mask
create gate of transistors. Polysilicon and active masks that does not
form a transistor should be kept separately.

Layout design rules: Contacts rules

Types of contacts:

 metal to p-active (p-diffusion)

 metal to n-active (n-diffusion)
 metal to polysilicon
 metal to well or substrate

Metal rules

Metal spacing can be different depending on the metal line. But there is
certain width applied to small and thick wires. So if there is a need of

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wider wires, they can be made of several small wires connected

together. Spacing rules can be applied to a long parallel wires.

Via (vertical interconnect access) rules

Modern planar technology allows stacked vias.

Other structures

Usually ready chip is marked with scribe lines, where it should be cut.
Manufacturer define the construction of the scribe line.

Alignment mark is placed on the mask to align one mask to another.

Critical dimension test structures are measured after processing to

check proper etching of narrow polysilicon or metal lines.

Vernier structures are used to check alignment between layers.

MOSIS scalable design rules

MOSIS CMOS design rules are -scallable. MOSIS CMOS design rules also
include SCMOS, SUBM and DEEP rules variations. For example for
SUBM rule.

CMOS-Layout-Design

Layout of Logic gates:

Three Input NAND Gate:

Figure below shows, the schematic, stick diagram and layout of three
input NAND gate.

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Two Input NAND Gate:

Figure below shows the schematic, stick diagram and layout of two
input NAND gate implemented using complementary CMOS logic.

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Two Input NOR Gate:

Figure below shows the schematic, stick diagram and layout of two
input NOR gate implemented using complementary CMOS logic.

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Transmission Gate:

Figure below shows the schematic, stick diagram and layout of the
transmission gate.

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ELECTRONIC SCIENCE UNIT-2 MCQs

THE LEARN WITH

EXPERTIES

As per updated syllabus

DIWAKAR EDUCTION HUB
 ELECTRONIC SCIENCE UNIT-2 MCQs

1. Find the basic chemical reaction 3. Where are the silicon wafers
used for Epitaxial growth? placed in the reaction chamber for
the epitaxial growth process?
a) Cup
b) Boats
c) Ingots
d) Crucible

Answer: b
Explanation: The silicon rods are not
Answer: c directly placed in the reaction
Explanation: The basic chemical chamber instead they are placed on a
reaction used for epitaxial growth of rectangular graphite rod called boats
pure silicon is the hydrogen reduction and then it is heated to 1200oc.
of silicon tetrachloride.
4. Which of the following is used to
2. Which component is added to the obtain silicon crystal structure while
p-type material in order to get the fabricating Integrating Circuits?
impurity concentration in epitaxial a) Oxidation
films? b) Epitaxial growth
a) Bi-borane (B2H2) c) Photolithography
b) Phosphine (PH3) d) Silicon wafer preparations
c) Boron chloride (BCl3)
Answer: b
d) Phosphorous pentoxide (P2O5)
Explanation: Epitaxial growth is
Answer: a arranging of atoms in single crystal
Explanation: Bi-Borane is used for fashion upon a single crystal
doping p-type materials and substrate, so that the resulting layer
Phosphine is used for doping n-type is an extension of the substrate
materials whereas Boron chloride crystal structure.
and Phosphorous pentoxide are used
5. Why oxidation process is required?
for doping during diffusion process.
a) To protect against contamination
b) To use it for fabrication various

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 ELECTRONIC SCIENCE UNIT-2 MCQs

components Answer: b
c) To prevent diffusion of impurities Explanation: Silicon wafers are raised
d) All of the mentioned to a high temperature in the range
950-1115oc and are exposed to gas.
Answer: d
The thickness of layer is governed by
Explanation: Oxidation provides
time, temperature and its moisture
extreme hard protective coating, thus
content.
protecting against contamination and
by selective etching, it can be made 8. Oxidation process in silicon planar
to fabricate components. technology is also called as
a) Photo oxidation
6. Mention the chemical reaction for
b) Silicon oxidation
oxidation process
c) Vapour oxidation
a) Si + 2H2O –> SiO2 + 2H2
d) Thermal oxidation
b) Si + O2 –> SiO2
c) 2Si + 2H2O –> 2SiO2 + 2H2 Answer: d
d) 2Si + 2H2O + 2O2 –> 2SiO2 + 2H2 + Explanation: The oxidation process is
O2 called thermal oxidation process
because high temperature is used to
Answer: a
grow the oxide layer.
Explanation: For oxidation process,
silicon wafers are heated to a high 9. In Crzochralski crystal growth
temperature and simultaneously they process, the materials are heated up
are exposed to a gas containing H2O to
or O2 or both. a) 950oc
b) 1000 oc
7. At what temperature should the
c) 1420oc
oxidation process be carried out to
d) 1200oc
get an oxide film of thickness 0.02 to
2µm? Answer: c
a) 0-105oc Explanation: The materials are
b) 950-1115oc heated above 1420oc which is greater
c) 200-850oc than the silicon melting point.
d) 350-900oc

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 ELECTRONIC SCIENCE UNIT-2 MCQs

10. How to obtain silicon ingots of 10- 12. The process involved in
15cm diameter? photolithography is
a) By crystal pulling process a) Making of a photographic mask
b) By crystal melting process only
c) By crystal growing process b) Photo etching
d) All of the mentioned c) Both photo etching and making of
photographic mask
Answer: a
d) None of the mentioned
Explanation: During crystal pulling
process, the seed crystal and the Answer: c
crucible rotate in opposite direction, Explanation: Photolithographic
in order to produce ingots of circular involves both processes in sequence.
cross section (diameter of 10/15cm First photographic mask is used for
normally obtained). artwork and reduction. Then Photo
etching for removal of SiO2 from
11. If the thickness of wafer after all
designed region.
polishing steps in silicon wafer
preparation is 23-40 mils. Find its raw 13. How will be the initial artwork
cut slice thickness? done for a normal IC?
a) 16-32 mils a) Smaller than the final dimension of
b) 23-40 mils chip
c) 8-12 mils b) Same as that of final dimension of
d) None of the mentioned chip
c) Larger than the final dimension of
Answer: a
chip
Explanation: Usually the silicon wafer
d) None of the mentioned
obtained has a very rough surface
due to slicing operation. So, these Answer: c
wafers undergo a number of Explanation: The initial artwork of an
polishing steps to produce flat and IC is done at a scale several hundred
smooth polished surface. Therefore, times longer than the final
the thickness of wafers will be dimensions. This is because for a tiny
reduced from its raw cut slice. chip, larger the artwork, more
accurate is the final mask.

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 ELECTRONIC SCIENCE UNIT-2 MCQs

14. Find the area of artwork done for c) hundred logic gates
a monolithic chip of area 30mil × d) thousands logic gates
30mil.
Answer: c
a) 16 cm × 16 cm
Explanation: Small scale integration
b) 60 cm × 60 cm
has one or more logic gate. Further
c) 12 cm × 12 cm
improved technology is medium scale
d) 36 cm × 36 cm
integration which consists of hundred
Answer: d logic gates. Large scale integration
Explanation: Drawings are magnified has thousand logic gates.
by a factor 500.
17. The difficulty in achieving high
=> 1mil = 25µm
doping concentration leads to
Therefore, 500mil = 1.2cm.
____________
In an area of 30mil × 30mil, the area
a) error in concentration
for artwork required = 30mil × 1.2cm
b) error in variation
= 36cm × 36cm.
c) error in doping
15. VLSI technology uses ________ to d) distribution error
form integrated circuit.
Answer: b
a) transistors
Explanation: As photolithography
b) switches
comes closer to the fundamental law
c) diodes
of optics, achieving high accuracy in
d) buffers
doping concentration becomes
Answer: a difficult, which leads to error due to
Explanation: Very large scale variation.
integration is the process of creating
18. _________ is used to deal with
an integrated circuit with thousands
effect of variation.
of transistors into one single chip.
a) chip level technique
16. Medium scale integration has b) logic level technique
____________ c) switch level technique
a) ten logic gates d) system level technique
b) fifty logic gates

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: d i. architecture design

Explanation: Designers must simulate
ii. market requirement
multiple fabrication process or use
system level technique for dealing iii. logic design
with effects of variation.
iv. HDL coding
19. As die size shrinks, the complexity
a) ii-i-iii-iv
of making the photomasks
b) iv-i-iii-ii
____________
c) iii-ii-i-iv
a) increases
d) i-ii-iii-iv
b) decreases
c) remains the same Answer: a
d) cannot be determined Explanation: The order of the design
flow of VLSI circuit is market
Answer: a
requirement, architecture design,
Explanation: As the die size shrinks
logic design, HDL coding and then
due to scaling, the number of die per
verification.
wafer increases and the complexity
of making the photomasks increases 22. ______ is used in logic design of
rapidly. VLSI.
a) LIFO
20. ______ architecture is used to
b) FIFO
design VLSI.
c) FILO
a) system on a device
d) LILO
b) single open circuit
c) system on a chip Answer: b
d) system on a circuit Explanation: First in first out (FIFO)
technique and finite state machine
Answer: c
technique is used in the logic design
Explanation: SoC that is system on a
of the VLSI circuits.
chip architecture is used to design
the very high level integrated circuit. 23. Which provides higher integration
density?
21. What is the design flow of VLSI
a) switch transistor logic
system?

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 ELECTRONIC SCIENCE UNIT-2 MCQs

b) transistor buffer logic and physical dimensions are

c) transistor transistor logic considered here.
d) circuit level logic
26. Gate minimization technique is
Answer: c used to simplify the logic.
Explanation: Transistor-transistor a) true
logic offers higher integration density b) false
and it became the first integrated
Answer: a
circuit revolution.
Explanation: Gate minimization
24. Physical and electrical technique is used to find the
specification is given in simplest, smallest and effective
____________ implementation of the logic.
a) architectural design
27. nMOS fabrication process is
b) logic design
carried out in ____________
c) system design
a) thin wafer of a single crystal
d) functional design
b) thin wafer of multiple crystals
Answer: d c) thick wafer of a single crystal
Explanation: Functional design d) thick wafer of multiple crystals
defines the major functional units of
Answer: a
the system, interconnections,
Explanation: nMOS fabrication
physical and electrical specifications.
process is carried out in thin wafer of
25. Which is the high level a single crystal with high purity.
representation of VLSI design?
28. ______________ impurities are
a) problem statement
added to the wafer of the crystal.
b) logic design
a) n impurities
c) HDL program
b) p impurities
d) functional design
c) siicon
Answer: a d) crystal
Explanation: Problem statement is a
Answer: b
high level representation of the
Explanation: p impurities are
system. Performance, functionality

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 ELECTRONIC SCIENCE UNIT-2 MCQs

introduced as the crystal is grown. b) polysilicon

This increases the hole concentration c) boron
in the device. d) phosphorus

29. What kind of substrate is Answer: b

provided above the barrier to Explanation: In nMOS device, the
dopants? gate material could be metal or
a) insulating polysilicon. This polysilicon layer has
b) conducting heavily doped polysilicon deposited
c) silicon by CVD.
d) semiconducting
32. Which is the commonly used bulk
Answer: a substrate in nMOS fabrication?
Explanation: Above a layer of silicon a) silicon crystal
dioxide which acts as a barrier, an b) silicon-on-sapphire
insulating layer is provided upon c) phosphorus
which other layers may be deposited d) silicon-di-oxide
and patterned.
Answer: c
30. The photoresist layer is exposed Explanation: In nMOS fabrication, the
to ____________ bulk substrate used can be either
a) Visible light bulk silicon or silicon-on-sapphire.
b) Ultraviolet light
33. In nMOS fabrication, etching is
c) Infra red light
done using ____________
d) LED
a) plasma
Answer: b b) hydrochloric acid
Explanation: The photoresist layer is c) sulphuric acid
exposed to ultraviolet light to mark d) sodium chloride
the regions where diffusion is to take
Answer: a
place.
Explanation: In nMOS fabrication,
31. In nMOS device, gate material etching is done using hydrofluoric
could be ____________ acid or plasma. Etching is a process
a) silicon

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 ELECTRONIC SCIENCE UNIT-2 MCQs

used to remove layers from the c) metal layer

surface. d) diffusion layer

34. Heavily doped polysilicon is Answer: a

deposited using ____________ Explanation: Contact cuts are made in
a) chemical vapour decomposition the desired polysilicon area, source
b) chemical vapour deposition and gate. COntact cuts are those
c) chemical deposition places where connection has to be
d) dry deposition made.

Answer: b 37. Interconnection pattern is made

Explanation: The polysilicon layer on ____________
consists of heavily doped polysilicon a) polysilicon layer
deposited by chemical vapour b) silicon-di-oxide layer
deposition. c) metal layer
d) diffusion layer
35. In diffusion process ______
impurity is desired. Answer: c
a) n type Explanation: The metal layer is
b) p type masked and etched to form
c) np type interconnection pattern. The metal
d) none of the mentioned layer was formed using aluminium
deposited over the formed surface.
Answer: a
Explanation: Diffusion is carried out 38. SIlicon-di-oxide is a good
by heating the wafer to high insulator.
temperature and passing a gas a) true
containing the desired ntype b) false
impurity.
Answer: a
36. Contact cuts are made in Explanation: SIlicon-di-oxide is a very
____________ good insulator so a very thin layer is
a) source required in the fabrication of MOS
b) drain transistor.

9
 ELECTRONIC SCIENCE UNIT-2 MCQs

39. _______ is used to suppress used in developing microcontrollers,

unwanted conduction. microprocessors, digital logic circuits
a) phosphorus and other integrated circuits.
b) boron
42. CMOS has __________
c) silicon
a) high noise margin
d) oxygen
b) high packing density
Answer: b c) high power dissipation
Explanation: Boron is used to d) high complexity
suppress the unwanted conduction
Answer: b
between transistor sites. It is
Explanation: Some of the properties
implanted in the exposed regions.
of CMOS are that it has low power
40. Which is used for the dissipation, high packing density and
interconnection? low noise margin.
a) boron
43. In CMOS fabrication, nMOS and
b) oxygen
pMOS are integrated in same
c) aluminium
substrate.
d) silicon
a) true
Answer: c b) false
Explanation: Aluminium is the
Answer: a
suitable material used for the circuit
Explanation: In CMOS fabrication,
interconnection or connecting two
nMOS and pMOS are integrated in
layers.
the same chip substrate. n-type and
41. CMOS technology is used in p-type devices are formed in the
developing which of the following? same structure.
a) microprocessors
44. P-well is created on __________
b) microcontrollers
a) p substrate
c) digital logic circuits
b) n substrate
d) all of the mentioned
c) p & n substrate
Answer: d d) none of the mentioned
Explanation: CMOS technology is

10
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: b __________
Explanation: P-well is created on n a) visible light
substrate to accommodate n-type b) ultraviolet light
devices whereas p-type devices are c) infra red light
formed in the ntype substrate. d) fluorescent

45. Oxidation process is carried out Answer: b

using __________ Explanation: The photoresist layer is
a) hydrogen exposed to ultraviolet light to mark
b) low purity oxygen the regions where diffusion is to take
c) sulphur place.
d) nitrogen
48. Few parts of photoresist layer is
Answer: a removed by using __________
Explanation: Oxidation process is a) acidic solution
carried out using high purity oxygen b) neutral solution
and hydrogen. Oxidation is a process c) pure water
of oxidizing or being oxidised. d) diluted water

46. Photoresist layer is formed using Answer: a

__________ Explanation: Few parts of photoresist
a) high sensitive polymer layer is removed by treating the
b) light sensitive polymer wafer with basic or acidic solution.
c) polysilicon Acidic solutions are those which have
d) silicon di oxide pH less than 7 and basic solutions
have greater than 7.
Answer: b
Explanation: Light sensitive polymer 49. P-well doping concentration and
is used to form the photoresist layer. depth will affect the __________
Photoresist is a light sensitive a) threshold voltage
material used to form patterned b) Vss
coating on a surface. c) Vdd
d) Vgs
47. In CMOS fabrication, the
photoresist layer is exposed to

11
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: a process in which net movement of

Explanation: Diffusion should be ions or molecules plays a major role.
carried out very carefully, as doping
52. _______ is sputtered on the
concentration and depth will affect
whole wafer.
both threshold voltage and
a) silicon
breakdown voltage.
b) calcium
50. Which type of CMOS circuits are c) potassium
good and better? d) aluminium
a) p well
Answer: d
b) n well
Explanation: Aluminium is sputtered
c) all of the mentioned
on the whole wafer before removing
d) none of the mentioned
the excess metal from the wafer.
Answer: b
53. MOS technology has more load
Explanation: N-well CMOS circuits are
driving capability.
better than p-well CMOS circuits
a) true
because of lower substrate bias
b) false
effect.
Answer: b
51. N-well is formed by __________
Explanation: One of the
a) decomposition
disadvantages of MOS technology is it
b) diffusion
has limited load driving capabilities.
c) dispersion
d) filtering 54. What is the disadvantage of the
MOS device?
Answer: b
a) limited current sourcing
Explanation: N-well is formed by
b) limited voltage sinking
using ion implantation or diffusion.
c) limited voltage sourcing
Ion implantation is a process by
d) unlimited current sinking
which ions of a material are
accelerated in an electrical field and
impacted into a solid. Diffusion is a Answer: a
Explanation: MOS devices have

12
 ELECTRONIC SCIENCE UNIT-2 MCQs

limited current sourcing and current dissipation and CMOS has low power
sinking abilities. dissipation.

55. What are the advantages of 58. CMOS is __________

BiCMOS? a) unidirectional
a) higher gain b) bidirectional
b) high frequency characteristics c) directional
c) better noise characteristics d) none of the mentioned
d) all of the mentioned
Answer: a
Answer: d Explanation: BiCMOS is unidirectional
Explanation: BiCMOS provides higher and CMOS is bidirectional.
gain, better noise and high frequency
59. In bipolar transistor, its quality
characteristics than MOS transistors.
can be improved by __________
56. What are the features of a) increasing collector resistance
BiCMOS? b) decreasing collector resistance
a) low input impedance c) collector resistance does not affect
b) high packing density the quality
c) high input impedance d) decreasing gate resistance
d) bidirectional
Answer: b
Answer: a Explanation: The quality of bipolar
Explanation: Some of the features of transistor can be improved by
BiCMOS are low input impedance, reducing the collector resistance,
low packing density, unidirectional, which can be done by using the
high output drive current, etc. additional layer of n+ subcollector.

57. BiCMOS has low power 60. BiCMOS can be used in

dissipation. __________
a) true a) amplifyig circuit
b) false b) driver circuits
c) divider circuit
Answer: b
d) multiplier circuit
Explanation: BiCMOS has high power

13
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: b c) easy handling

Explanation: BiCMOS is more d) very simple design
advantageous and improved than
Answer: a
CMOS and it can be used in I/O and
Explanation: Vector scanning is faster
driver circuits.
but data handling involved is more
61. What are the advantages of E- complex. Vector scanning is done
beam masks? between the end points.
a) small feature size
64. Which has high input resistance?
b) larger feature size
a) nMOS
c) looser layer
b) CMOS
d) complex design
c) pMOS
Answer: a d) BiCMOS
Explanation: The advantages of E-
Answer: b
beam masks are it has tighter layer to
Explanation: CMOS technology has
layer registration and it has smaller
high input resistance and is best for
feature sizes.
constructing simple low-power logic
62. Which process is used in E-beam gates.
machines?
66. BiCMOS has lower standby
a) raster scanning
leakage current.
b) vector scanning
a) true
c) raster & vector scanning
b) false
d) none of the mentioned
Answer: b
Answer: c
Explanation: BiCMOS has the
Explanation: The two approaches to
potential for high standby leakage
the design of E-beam machines are
current and has high power
raster scanning and vector scanning.
consumption compared to CMOS.
63. What is the feature of vector
67. What is Lithography?
scanning?
a) Process used to transfer a pattern
a) faster
to a layer on the chip
b) slow

14
 ELECTRONIC SCIENCE UNIT-2 MCQs

b) Process used to develop an c) Negative photo resists are less

oxidation layer on the chip sensitive to light
c) Process used to develop a metal d) Positive photo resists are less
layer on the chip sensitive to light
d) Process used to produce the chip
Answer: a
Answer: a Explanation: Negative photo resists
Explanation: Lithography is the are more sensitive to light, but their
process used to develop a pattern to photo lithographic resolution is not
a layer on the chip. as high as that of the positive photo
resists. Therefore, negative photo
67. Silicon oxide is patterned on a
resists are-used less commonly in the
substrate using ____________
manufacturing of high-density
a) Physical lithography
integrated circuits.
b) Photolithography
c) Chemical lithography 69. The ______ is used to reduce the
d) Mechanical lithography resistivity of poly silicon.
a) Photo resist
Answer: b
b) Etching
Explanation: Silicon oxide is
c) Doping impurities
patterned on a substrate using
d) None of the mentioned
Photolithography.
Answer: c
68. Positive photo resists are used
Explanation: The resistivity of poly
more than negative photo resists
silicon is reduced by Doping
because ___________
impurities.
a) Negative photo resists are more
sensitive to light, but their photo 70. The isolated active areas are
lithographic resolution is not as high created by technique known as
as that of the positive photo resists ___________
b) Positive photo resists are more a) Etched field-oxide isolation
sensitive to light, but their photo b) Local Oxidation of Silicon
lithographic resolution is not as high c) Etched field-oxide isolation or Local
as that of the negative photo resists

15
 ELECTRONIC SCIENCE UNIT-2 MCQs

Oxidation of Silicon Answer: d

d) None of the mentioned Explanation: Two ways to add
dopants are diffusion and ion
Answer: c
implantation.
Explanation: To create isolated active
areas both the techniques can be 73. To grow the polysilicon gate layer,
used. Among them Local Oxidation of which of the following chemical is
Silicon(LOCOS) is most efficient. used for chemical vapour deposition?
a) Silicon Nitride(Si3N4)
71. The chemical used for shielding
b) Silane gas(SiH4)
the active areas to achieve selective
c) Silicon oxide
oxide growth is?
d) None of the mentioned
a) Silver Nitride
b) Silicon Nitride Answer: b
c) Hydrofluoric acid Explanation: Silicon Wafer is placed in
d) Polysilicon a reactor with silane gas (SiH4), and
they are heated again to grow the
Answer: b
polysilicon layer by chemical vapor
Explanation: Selective oxide growth is
deposition.
achieved by shielding the active
areas. Silicon nitride (Si3N4) is used 74. The process by which Aluminium
for shielding the active areas during is grown over the entire wafer, also
oxidation, which effectively inhibits filling the contact cuts is?
oxide growth. a) Sputtering
b) Chemical vapour deposition
72. The dopants are introduced in the
c) Epitaxial growth
active areas of silicon by using which
d) Ion Implantation
process?
a) Diffusion process Answer: a
b) Ion Implantation process Explanation: Aluminum is sputtered
c) Chemical Vapour Deposition over the entire wafer, it also fills the
d) Either Diffusion or Ion contact cuts.
Implantation Process
75. Which process is involved in
growing the shaded region?

16
 ELECTRONIC SCIENCE UNIT-2 MCQs

produced using chemical vapor

deposition (CVD) and it is patterned
by dry (plasma) etching.

76. Chemical Mechanical Polishing is

used to ___________
a) Remove silicon oxide
b) Remove silicon nitride and pad
oxide
c) Remove polysilicon gate layer
d) Reduce the size of the layout

Answer: b
Explanation: The pad oxide and
nitride are removed using a Chemical
Mechanical Polishing (CMP) step.

77. Gate oxide layer consists of

___________

a) Chemical vapor deposition (CVD)

b) Sputtering and patterned by
etching
c) Chemical vapor deposition (CVD) a) SiO2 layer, overlaid with a few
and patterned by HF acid etching layers of an oxynitrided oxide
d) Chemical vapor deposition (CVD) b) Only SiO2 Layer
and patterned by dry (plasma) c) SiO2 layer with Polysilicon Layer
etching d) SiO2 layer and stack of epitaxial
Answer: d layers of Polysilicon
Explanation: The poly silicon layer is

17
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: a hydrogen peroxide that is used to

Explanation: Current processes clean silicon wafers of metal and
seldom use a pure SiO2 gate oxide, organic contaminants or photo-resist
but prefer to produce a stack that after metal patterning.
consists of a few atomic layers, each
79. The work function difference is
3–4 Å thick, of SiO2 for reliability,
negative for ____________
overlaid with a few layers of oxy-
a) silicon substrate
nitrided oxide (one with nitrogen
b) polysilicon gate
added).
c) silicon substrate & polysilicon gate
78. What is Piranha Solution? d) none of the mentioned
a) It is a 3:1 to 5:1 mix of nitric acid
Answer: c
and hydrogen peroxide that is used
Explanation: The work function
to develop the oxide layer on silicon
difference between gate and Si
substrate
(Φms) is negative for silicon substrate
b) It is a 3:1 to 5:1 mix of sulphuric
and polysilicon gate.
acid and hydrofluoric acid that is used
to clean silicon wafers removing 80. Substrate bias voltage is positive
organic and metal contaminants or for nMOS.
photo resist after metal patterning a) true
c) It is a 3:1 to 5:1 mix of sulphuric b) false
acid and hydrogen peroxide that is
Answer: b
used to grow the oxide layer on the
Explanation: Substrate bias voltage
silicon
Vsb is positive for pMOS and negative
d) It is a 3:1 to 5:1 mix of sulphuric
for nMOS.
acid and hydrogen peroxide that is
used to clean wafers of organic and 81. According to body effect,
metal contaminants or photo resist substrate is biased with respect to
after metal patterning ___________
a) source
Answer: d
b) drain
Explanation: Piranha solution is a 3:1
c) gate
to 5:1 mix of sulfuric acid and
d) Vss

18
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: a a) decreasing the width

Explanation: According to body b) increasing the width
effect, the substrate is biased with c) increasing the length
respect to the source. Body effect can d) decreasing the length
be seen as a change in the threshold
Answer: b
voltage.
Explanation: Transconductance gm of
82. Increasing Vsb _______ the a MOS device can be increased by
threshold voltage. increasing its width and it does not
a) does not effect depend on length.
b) decreases
85. Increasing the transconductance
c) increases
___________
d) exponentially increases
a) increases input capacitance
Answer: c b) decreasing area occupied
Explanation: Increasing the substrate c) decreasing input capacitance
bias voltage Vsb, increases the d) decrease in output capacitance
threshold voltage because it depletes
Answer: a
the channel of charge carriers.
Explanation: Increasing the
83. Transconductance gives the transconductance gm results in an
relationship between ___________ increase in input capacitance and
a) input current and output voltage area occupied as it is directly
b) output current and input voltage proportional.
c) input current and input voltage
86. Ids is _______ to length L of the
d) output current and output voltage
channel.
Answer: b a) directly proportional
Explanation: Transconductance b) inversely proportional
expresses the relationship between c) not related
output current Ids and input voltage d) logarithmically related
Vgs.
Answer: b
84. Transconductance can be Explanation: Ids is inversely
increased by ___________ proportional to the length L of the

19
 ELECTRONIC SCIENCE UNIT-2 MCQs

channel and using this relationship a) effective drain voltage

strong dependence of output b) effective gate voltage
conductance on channel length can c) channel length
be demonstrated. d) effective source voltage

87. Switching speed of a MOS device Answer: b

depends on ___________ Explanation: Surface mobility is
a) gate voltage above a threshold dependent on the effective gate
b) carrier mobility voltage (Vgs-Vt). Electron mobility on
c) length channel oriented n-type inversion layer
d) all of the mentioned surface is larger than that on an
oriented surface.
Answer: d
Explanation: Switching speed of a 90. What is a MOS transistor?
MOS device depends on gate voltage a) minority carrier device
above a threshold and on carrier b) majority carrier device
mobility and inversely as the square c) majority & minority carrier device
of channel length. d) none of the mentioned

88. A fast circuit requires Answer: b

___________ Explanation: MOS transistor is a
a) high gm majority carrier device, in which
b) low gm current in a conducting channel
c) does not depend on gm between the source and drain is
d) low cost modulated by a voltage.

Answer: a 91. The MOS transistor is non

Explanation: A fast circuit requires gm conducting when?
as high as possible as the switching a) zero source bias
speed depends on gate voltage above b) zero threshold voltage
threshold and on carrier mobility and c) zero gate bias
inversely to square of channel length. d) zero drain bias

89. Surface mobility depends on Answer: c

___________ Explanation: The MOS transistor

20
 ELECTRONIC SCIENCE UNIT-2 MCQs

normally is at cut-off or becomes b) depletion mode

non-conducting with zero gate bias c) all of the mentioned
(gate voltage-source voltage). d) none of the mentioned

92. Inverters are essential for Answer: b

________ Explanation: Depletion mode
a) NAND gates transistors are preferred to be used
b) NOR gates as load in inverter circuits as it
c) sequential circuits occupies a lesser area and are
d) all of the mentioned produced on silicon substrate unlike
resistors.
Answer: d
Explanation: Inverters are needed for 95. For depletion mode transistor,
restoring logic levels for NAND and gate should be connected to
NOR gates, sequential and memory ________
circuits. a) source
b) drain
93. In basic inverter circuit
c) ground
_____________ is connected to
d) positive voltage rail
ground.
a) source Answer: a
b) gates Explanation: For the depletion mode
c) drain transistor, gate is connected to
d) resistance source so it is always on and only the
characteristic curve Vgs=0 is relevant.
Answer: a
Explanation: A basic inverter circuit 96. In nMOS inverter configuration
consists of transistor with a source depletion mode device is called as
connected to ground and a load ________
resistor connected from drain to a) pull up
positive supply rail Vdd. b) pull down
c) all of the mentioned
94. In inverter circuit ________
d) none of the mentioned
transistors is used as load
a) enhancement mode

21
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: a
Explanation: In nMOS inverter
configuration, depletion mode
devices are called as pull up and
enhancement mode devices are
called as pull down transistor.

97. How is nMOS inverter

represented?

c)

a)

d)

Answer: b
Explanation: nMOS inverter can be
represented using two transistors,
depletion mode pMOS transistor
followed by nMOS transistor. Input is
given to the nMOS.

b) 98. What is the ratio of Zp.u/Zp.d?

a) 1/4
b) 4/1

22
 ELECTRONIC SCIENCE UNIT-2 MCQs

c) 1/2 one or more pass transistors has the

d) 2/1 ratio of 8/1.

Answer: b 101. In depletion mode pull-up,

Explanation: The ratio of Zp.u/Zp.d, dissipation is high since current flows
where Z is determined by the length when?
to width ratio of the transistor, is a) Vin = 1
given by 4/1. b) Vin = 0
c) Vout = 1
99. Pass transistors are transistors
d) Vout = 0
used as ________
a) switches connected in series Answer: a
b) switches connected in parallel Explanation: In nMOS depletion
c) inverters used in series mode pull-up, dissipation is high since
d) inverter used in parallel current flows Vin = logical 1.

Answer: a 102. In complementary transistor

Explanation: Pass transistors are pull-up, current flows when?
transistor used as switches in series a) Vin = 1
with lines carrying logic levels due to b) Vin = 0
its isolated nature of the gate. c) current doesn’t flow
d) Vout = Vin
100. An inverter driven through one
or more pass transistors has Answer: c
Zp.u/Zp.d ratio of ________ Explanation: In complementary
a) 1/4 transistor pull-up no current flows
b) 4/1 either for logical 1 or 0, full logical 1
c) 1/8 and 0 levels are presented at the
d) 8/1 output.

Answer: d 103. CMOS inverter has ______

Explanation: An inverter driven regions of operation.
directly from output of another has a) three
the ratio of 4/1 and if driven through b) four

23
 ELECTRONIC SCIENCE UNIT-2 MCQs

c) two between source and drain, then it is

d) five said to be in unsaturated resistive
region.
Answer: d
Explanation: CMOS inverter has five 106. In the region where inverter
distinct regions of operation which exhibits gain, the two transistors are
can be determined by plotting CMOS in _______ region.
inverter current versus Vin. a) linear
b) cut-off
104. If n-transistor conducts and has
c) non saturation
large voltage between source and
d) saturation
drain, then it is said to be in _____
region. Answer: d
a) linear Explanation: In the region where the
b) saturation inverter exhibits gain, the two
c) non saturation transistors n and p operates in
d) cut-off saturation region.

Answer: b 107. If both the transistors are in

Explanation: If n-transistor conducts saturation, then they act as ________
and has large voltage between source a) current source
and drain, then it is in saturation. b) voltage source
c) divider
105. If p-transistor is conducting and
d) buffer
has small voltage between source
and drain, then it is said to work in Answer: a
________ Explanation: When both the
a) linear region transistors are in saturation, then act
b) saturation region as current sources so that the
c) non saturation resistive region equivalent circuit is two current
d) cut-off region sources between Vdd and Vss.

Answer: c 108. If βn = βp, then Vin is equal to

Explanation: If p-transistor is ________
conducting and has small voltage a) Vdd

24
 ELECTRONIC SCIENCE UNIT-2 MCQs

b) Vss 111. CMOS inverter has ______

c) 2Vdd output impedance.
d) 0.5Vdd a) low
b) high
Answer: d
c) very high
Explanation: If βn = βp, then Vin =
d) none of the mentioned
0.5Vdd which implies that the
changeover between logic levels is Answer: a
symmetrically disposed about the Explanation: CMOS inverter has low
point. output impedance and this makes it
less prone to noise and disturbance.
109. Mobility depends on ________
a) Transverse electric field 112. What is the input resistance of
b) Vg CMOS inverter?
c) Vdd a) high
d) Channel length b) low
c) very low
Answer: a
d) none of the mentioned
Explanation: Mobility is affected by
the transverse electric field and thus Answer: a
also depends on Vgs and the mobility Explanation: Input resistance of
of p-device and n-device are CMOS inverter is extremely high as it
inherently unequal. is a perfect insulator and draws no dc
input source.
110. In CMOS inverter, transistor is a
switch having ________ 113. Increasing fan-out
a) infinite on resistance ____________ the propagation delay.
b) finite off resistance a) increases
c) buffer b) decreases
d) infinite off resistance c) does not affect
d) exponentially decreases
Answer: b
Explanation: In CMOS inverter, Answer: a
transistor is a switch having finite on Explanation: In CMOS inverter,
resistance and infinite off resistance. increasing the fan-out also increases

25
 ELECTRONIC SCIENCE UNIT-2 MCQs

the propagation delay. Fan-out is a 116. Transconductance depends on

term that defines the maximum the process.
number of digital inputs that the a) true
output of a single logic gate can feed. b) false

114. Fast gate can be built by keeping Answer: b

________ Explanation: Transconductance gm is
a) low output capacitance independent of process.
b) high on resistance
117. gm is ______ on input voltage
c) high output capacitance
Vbe.
d) input capacitance does not affect
a) inversely proportional
speed of the gate
b) proportional
Answer: a c) exponentially dependent
Explanation: Fast gate can be built by d) is not dependent
keeping the output capacitance small
Answer: c
and by decreasing the on resistance
Explanation: Transconductance gm is
of the transistor.
exponentially dependent on input
115. The transconductance of a voltage Vbe (base to emitter voltage).
bipolar is given by ______________
118. gm is _______ to Ic.
a) (kT/q)/Ic
a) directly proportional
b) Ic/(kT/q)
b) inversely proportional
c) (q/KT)/Ic
c) not dependent
d) Ic/(q/KT)
d) exponentially proportional
Answer: b
Answer: a
Explanation: Transconductance gm of
Explanation: Transconductance gm is
a bipolar transistor is given by gm =
directly proportional to Ic, collector
Ic/(kT/q). Transconductance is the
current.
electrical characteristic relating the
current through the output of a 119. Transconductance is a
device to the voltage across the input __________
of a device. a) weak function

26
 ELECTRONIC SCIENCE UNIT-2 MCQs

b) strong function 122. Which has better I/A?

c) weak and strong function a) CMOS
d) none of the mentioned b) bipolar
c) nMOS
Answer: a
d) pMOS
Explanation: Transconductance gm is
a weak function of transistor size. Answer: b
Explanation: Current/Area (I/A) of
120. gm of bipolar is less than gm of
bipolar is five times better than
MOS.
CMOS and this can be calculated
a) true
using base resistance and base transit
b) false
time.
Answer: b
123. Bipolar transistor exhibits
Explanation: Transconductance gm of
_______ delay.
bipolar is greater than gm of MOS if
a) turn on
inputs are controlled by equal
b) turn off
amounts of charge.
c) storage
121. Which of the following is true d) all of the mentioned
when inputs are controlled by equal
Answer: d
amounts of charge?
Explanation: Bipolar transistors
a) Cg(MOS) = Cbase(bipolar)
exhibits turn-on, turn-off, storage
b) Cg(MOS) greater than
delays.
Cbase(bipolar)
c) Cg(MOS) lesser than Cbase(bipolar) 124. In bipolar transistor, which is
d) Cs(MOS) lesser than Cbase(bipolar) heavily doped?
a) base region
Answer: a
b) emitter region
Explanation: Cg(MOS) =
c) collector region
Cbase(bipolar) when inputs are
d) base and emitter
controlled by equal amounts of
charge, and then gm(bipolar) >> Answer: b
gm(MOS). Explanation: In bipolar transistor,

27
 ELECTRONIC SCIENCE UNIT-2 MCQs

emitter region is heavily doped and switches are used to perform logic
the base region is lightly doped. functions. The ability to turn the
power MOS “ON” and “OFF” allows
125. Bipolar transistor is a
the device to be used as a very
symmetrical device.
efficient switch with switching speeds
a) true
much faster than standard bipolar
b) false
junction transistors.
Answer: b
128. The nMOS and pMOS transistors
Explanation: Bipolar transistor is not
used in BiCMOS is ____________
symmetrical like other transistors.
a) depletion mode
126. In BiCMOS, bipolar transistors b) enhancement mode
are used to ___________ c) only pMOS
a) drive input loads d) only nMOS
b) drive output loads
Answer: b
c) to perform logic functions
Explanation: The nMOS and pMOS
d) to amplify the input voltage
transistors used in BiCMOS device
Answer: b operates in enhancement mode.
Explanation: In BiCMOS, bipolar Enhancement mode devices are
transistors are used to drive output mostly common switching elements
loads. Bipolar transistor can also be in MOS.
used as amplifier, switch or as an
129. The inverter has __________
oscillator.
a) low input impedance
127. In BiCMOS, MOS switches are b) high input impedance
used to __________ c) high output impedance
a) drive input loads d) high input and output impedance
b) drive output loads
Answer: a
c) to perform logic functions
Explanation: The inverter has low
d) to amplify the input voltage
input impedance. The basic inverter
Answer: c circuit requires a transistor with
Explanation: In BiCMOS circuits, MOS source connected to ground and a

28
 ELECTRONIC SCIENCE UNIT-2 MCQs

load resistor connected from the performance BiCMOS circuit, the

drain to positive supply Vdd. output voltage swing should be
reduced. The possible maximum
130. The inverter has __________
output peak-to-peak voltage
a) low output impedance
obtained without clipping is called as
b) low input impedance
output voltage swing.
c) low power dissipation
d) high input and output impedance 133. BiCMOS inverter requires high
load current sourcing.
Answer: a
a) true
Explanation: The inverter has low
b) false
output impedance and low input
impedance. These are some of the Answer: a
properties of a BiCMOS inverter. Explanation: BiCMOS inverter needs
high load current sinking and
131. The inverter has __________
sourcing. Sinking provides a grounded
a) high current driving capability
connection to the load, whereas
b) occupies smaller area
sourcing provides a voltage source to
c) high noise margin
the load.
d) all of the mentioned
134. BiCMOS has _______ standby
Answer: d
leakage current.
Explanation: The inverter has high
a) higher
current driving capability, occupies
b) lower
smaller area and has high noise
c) very low
margins.
d) none of the mentioned
132. Output voltage swing should be
Answer: a
reduced for a better performance of
Explanation: BiCMOS has higher
BiCMOS circuit.
standby leakage current and thus has
a) true
high power consumption.
b) false
135. For improved base current
Answer: a
discharge ________ enhancement
Explanation: For a better
type nMOS devices have to be added.

29
 ELECTRONIC SCIENCE UNIT-2 MCQs

a) two static power dissipation and high

b) three input impedance.
c) one
138. In latch-up condition, parasitic
d) four
component gives rise to __________
Answer: a conducting path.
Explanation: For improved base a) low resistance
current discharge, two enhancement b) high resistance
type nMOS transistors have to be c) low capacitance
added. d) high capacitance

136. The BJTs in the BICMOS circuit is Answer: a

in _____________ configuration. Explanation: In latch-up condition,
a) Push-pull the parasitic component gives rise to
b) Totem pole low resistance conducting path
c) Active high between Vdd and Vss with disastrous
d) Active low results. Careful control during
fabrication is necessary to avoid this
Answer: b
problem.
Explanation: In BiCMOS circuit, the
BJT transistors are in Totem pole 139. Latch-up can be induced by
configuration. __________
a) incident radiation
137. The MOSFETS are arranged in
b) reflected radiation
this configuration to provide
c) etching
__________
d) diffracted radiation
a) Zero static power dissipation
b) High Input impedance Answer: a
c) Both zero static power dissipation Explanation: Latch-up can be induced
and high input impedance by glitches on the supply rail or by
d) None of the mentioned incident radiation.

Answer: c 140. How many transistors might

Explanation: MOSFETs provide zero bring up latch up effect in p-well
structure?

30
 ELECTRONIC SCIENCE UNIT-2 MCQs

a) two diffusions which decouple the

b) three parasitic bipolar transistors.
c) one
143. Which process produces a circuit
d) four
which is less prone to latch-up effect?
Answer: a a) CMOS
Explanation: Two transistors and two b) nMOS
resistances might bring up the latch- c) pMOS
up effect in p-well structure. These d) BiCMOS
are associated with p-well and with
Answer: d
regions of the substrate.
Explanation: BiCMOS process
141. Substrate doping level should be produces circuits that are less likely
decreased to avoid the latch-up to suffer from latch-up problems
effect. where as CMOS circuits are very
a) true highly prone to latch-up problems.
b) false
144. Which one of the following is the
Answer: b main factor for reducing the latch-up
Explanation: An increase in substrate effect?
doping level with a consequent drop a) reduced p-well resistance
in the value of Rs can be used as a b) reduced n-well resistance
remedy for latch-up problem. c) increased n-well resistance
d) increased p-well resistance
142. What can be introduced to
reduce the latch-up effect? Answer: b
a) latch-up rings Explanation: One of the main factors
b) guard rings in reducing the latch-up effect is
c) latch guard rings reduced n-well resistance Rw.
d) substrate rings Reduction in Rw means that a larger
lateral current is necessary to invite
Answer: b
latch-up and higher value of holding
Explanation: The introduction of
current is also required.
guard rings can reduce the effect of
latch-up problem. Guard rings are

31
 ELECTRONIC SCIENCE UNIT-2 MCQs

145. The parasitic PNP transistor has means that larger lateral current is
the effect of _______ carrier lifetime. necessary to invite latch-up.
a) increasing
148. Latch-up is the generation of
b) decreasing
__________
c) exponentially decreasing
a) low impedance path
d) exponentially increasing
b) high impedance path
Answer: b c) low resistance path
Explanation: The parasitic PNP d) high resistance path
transistor has the effect of reducing
Answer: a
carrier lifetime in the n-base region.
Explanation: Latch-up is the
146. The reduction in carrier lifetime generation of low-impedance path in
brings about __________ CMOS chips between the power
a) reduction in alpha supply and ground rails.
b) reduction in beta
149. Latch-up is brought about by
c) reduction in current
BJTs __________
d) reduction in voltage
a) with positive feedback
Answer: b b) with negative feedback
Explanation: The parasitic PNP c) with no feedback
transistor has the effect of reducing d) without BJT
carrier lifetime in the n-base region
Answer: a
which results in radiation in beta.
Explanation: Latch-up occurs due to
147. To reduce latch-up effect BJTs for silicon-controlled rectifiers
substrate resistance should be high. with positive feedback and virtually
a) true short circuit the power and ground
b) false rail.

Answer: b 150. Sudden transient in power can

Explanation: To reduce the latch-up cause latch-up.
effect, substrate resistance Rs should a) true
be low. Reduction of Rs and Rw b) false

32
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: a 153. Which color is used for n-

Explanation: Sudden transient in diffusion?
power and ground buses are also a) red
among the reason which causes b) blue
latch-up effect. c) green
d) yellow
151. BJT gain should be ______ to
avoid latch-up effect. Answer: c
a) increased Explanation: Green color is used to
b) decreased show the presence of n-diffusion
c) should be maintained constant layer. The n-type diffusion will dope
d) changed randomly the source or drain region in the p-
well region.
Answer: b
Explanation: BJT gain should be 154. Which color is used for implant?
reduced by lowering the minority a) red
carrier lifetime through doping of the b) blue
substrate to lower the latch-up c) green
effect. d) yellow

152. Stick diagrams are those which Answer: d

convey layer information through? Explanation: Yellow color is used to
a) thickness represent implant layer.
b) color
155. Which color is used for contact
c) shapes
areas?
d) layers
a) red
Answer: b b) brown
Explanation: Stick diagrams are those c) black
which convey layer information d) blue
through color codes. Thickness is not
Answer: c
considered in this stick diagram
Explanation: Black color is used to
representation.
represent contact areas. This is the

33
 ELECTRONIC SCIENCE UNIT-2 MCQs

part where two different touch or 159. n and p transistors are separated
cross each other. by using __________
a) differentiation line
156. Which color is used for
b) separation line
polysilicon?
c) demarcation line
a) brown
d) black line
b) red
c) white Answer: c
d) orange Explanation: Demarcation line
separates n and p transistors.
Answer: b
Demarcation line is similar to dotted
Explanation: Red is used to represent
line in brown.
polysilicon layers. It is a semi-
conductor like material and is a hyper 160. _______ layer should be over
pure form of silicon. ______ layer.
a) ntype, polysilicon
157. Which color is used for
b) polysilicon, ntype
polysilicon 2?
c) ptype, ntype
a) blue
d) ntype, ptype
b) brown
c) orange Answer: b
d) white Explanation: Polysilicon layer should
be over n-type layer. This is the
Answer: c
standard pattern used in stick
Explanation: Orange color is used to
diagram representation.
represent polysilicon-2 layer.
161. How is nMOS depletion mode
158. Which color is used for buried
transistor represented?
contact?
a) black
b) white
c) green
d) brown

a)
34
 ELECTRONIC SCIENCE UNIT-2 MCQs

c) yellow, dark line

d) yellow, dotted line

Answer: d
Explanation: Implant is represented
using yellow color dotted lines. It is
b) drawn in the middle of the nMOS or
pMOS wherever the implant is used.

163. Stick diagram gives the position

of placement of the element.
a) true
b) false

c) Answer: b
Explanation: Stick diagram does not
show exact placement of
components, transistor length, wire
length and width, tub boundaries,
etc.

d) 164. When two or more cuts of same

type cross or touch each other, that
represents ____________
Answer: c
a) contact cut
Explanation: nMOS depletion mode
b) electrical contact
transistor can be represented by
c) like contact
using polysilicon over ntype layer and
d) cross contact
with an implant.
Answer: b
162. Implant is represented using
Explanation: When two or more
___________
sticks of same type cross or touch
a) black, dark line
each other, then that forms a contact
b) black, dotted line
called electrical contact.

35
 ELECTRONIC SCIENCE UNIT-2 MCQs

165. Circuit design concepts can also Answer: c

be represented using a symbolic Explanation: Process engineers want
diagram. design rules which are controllable
a) true and reproducible process.
b) false
168. Maturity level of the process line
Answer: a affects design rules.
Explanation: Circuit design concepts a) true
can be represented using stick b) false
diagrams and symbolic diagrams.
Answer: a
Stick diagrams represents different
Explanation: Yes, the maturity level of
layers with color codes. Symbolic
the process line affects design rules.
diagram represents the structure
with symbols with color codes. 169. Design rules does not specify
__________
166. Circuit designers need _______
a) linewidths
circuits.
b) separations
a) tighter
c) extensions
b) smaller layout
d) colours
c) decreased silicon area
d) all of the mentioned Answer: d
Explanation: Design rules specify line
Answer: d
widths, separations and extensions in
Explanation: Circuit designers in
terms of lambda.
general prefer tighter, smaller layouts
for improved performance and 170. The width of n-diffusion and p-
decreased silicon area. diffusion layer should be?
a) 3λ
167. Process engineers want ______
b) 2λ
process.
c) λ
a) smaller
d) 4λ
b) tighter
c) reproducible Answer: b
d) non reproducible Explanation: The width of n-diffusion

36
 ELECTRONIC SCIENCE UNIT-2 MCQs

and p-diffusion should be 2λ Answer: a

according to design rules. Explanation: Implant for a n-mos
depletion mode transistor should
171. What should be the spacing
extend minimum of 2λ from the
between two diffusion layers?
channel in all the directions.
a) 4λ
b) λ 174. Which type of contact cuts are
c) 3λ better?
d) 2λ a) buried contacts
b) butted contacts
Answer: c
c) butted & buried contacts
Explanation: The spacing between
d) none of the mentioned
two diffusion layers should be 3λ
according to design rules and Answer: a
standards. Explanation: Buried contacts are
much better than butted contacts. In
172. What should be the width of
butted contacts the two layers are
metal 1 and metal 2 layers?
joined together or binded together
a) 3λ, 3λ
using adhesive type of material
b) 2λ, 3λ
where as in buried contact one layer
c) 3λ, 4λ
is interconcted or fitted into another.
d) 4λ, 3λ
175. Which design method occupies
Answer: c
or uses lesser area?
Explanation: The width of the metal 1
a) lambda rules
layer should be 3λ and metal 2 should
b) micron rules
be 4λ.
c) layer rule
173. Implant should extend _______ d) source rule
from all the channels.
Answer: b
a) 2λ
Explanation: Micron rules occupies or
b) 3λ
consumes lesser area. 50% of the
c) 4λ
area usage can be reduced by using
d) λ
micron rules over lambda rules.

37
 ELECTRONIC SCIENCE UNIT-2 MCQs

176. Which gives scalable design butting contact. In butting contact

rules? the two layers are joined or binded
a) lambda rules together.
b) micron rules
179. Which is a more complex
c) layer rules
process?
d) thickness rules
a) buried contact
Answer: a b) butting contact
Explanation: Lambda rules gives c) buried & butting contact
scalable design rules and micron rules d) none of the mentioned
gives absolute dimensions.
Answer: a
177. Devices designed with lambda Explanation: Butting contact is a
design rules are prone to shorts and complex process whereas buried
opens. contact is simple process because
a) true butting contact should be done more
b) false carefully to serve well and be strong.

Answers: b 180. Which contact cut occupies

Explanation: Lambda design rules smaller area?
prevent shorting, opens, contact a) buried contact
from slipping out of the area to be b) butting contact
contacted. c) buried & butting contact
d) none of the mentioned
178. Diffusion and polysilicon layers
are connected together using Answer: a
__________ Explanation: Buried contact occupies
a) butting contact smaller area than butting contact as
b) buried contact in buried contacts one layer will be
c) separate contact completely within or almost within
d) cannot be connected the another layer.

Answer: a 181. Isolation layer between two

Explanation: Diffusion and polysilicon metal layers must be thinner.
layer are joined together using

38
 ELECTRONIC SCIENCE UNIT-2 MCQs

a) true Answer: a
b) false Explanation: Metal layers are used for
power and signal lines as metals has
Answer: b
good thermal and electrical
Explanation: Isolation layer between
conductivity.
two metal layers should be thicker.
Metal to metal separation is large 184. Minimum feature size for thick
and is brought about mainly by oxide is?
difficulties in defining metal edges a) 2λ
accurately. b) 3λ
c) 4λ
182. The oxide layer below the first
d) λ
metal layer is deposited using
__________ Answer: b
a) diffusion method Explanation: The minimum feature
b) chemical vapour deposition size for thick oxide is 3λ and
c) solid deposition minimum separation between thin
d) scattering method oxide regions is also 3λ.

Answer: b 185. Hatching is compatible with

Explanation: The oxide layer below __________
the first metal layer is depostied a) monochrome encoding
using chemical vapour deposition b) bicode encoding
method. This is a chemical process c) tricode encoding
used to produce high quality high d) not compatible with any encoding
performance solid materials.
Answer: a
183. Which layer is used for power Explanation: Hatching is compatible
and signal lines? with monochrome encoding and also
a) metal may be added to color mask coding.
b) polysilicon It is designed using closely spaced
c) n-diffusion lines or sticks.
d) p-diffusion
186. Minimum n-well width should
be ____________ micro meter.

39
 ELECTRONIC SCIENCE UNIT-2 MCQs

a) 2 occurs. And this is caused by oxide

b) 3 thickness, ion implantation and poly
c) 4 variations.
d) 6
189. What are the advantages of
Answer: b design rules?
Explanation: The minimum width of a) durable
n-well is 3 micro meter because n- b) scalable
well should be with little thickness c) portable
and in it p-type devices are formed. d) all of the mentioned

187. The minimum spacing between Answer: d

two n-well is _____ micro meter. Explanation: Some of the advantages
a) 4 of generalised design rules are those
b) 5 are durable, scalable, portable,
c) 8 increases designer efficiency and
d) 8.5 automatic translation to final layout
can be done.
Answer: d
Explanation: The minimum spacing 190. Minimum diffusion space is
between two n-well is 8.5 micro __________
meter according to the lambda based a) 2λ
design rules. b) 3λ
c) 4λ
188. Which can bring about variations
d) λ
in threshold voltage?
a) oxide thickness Answer: b
b) ion implantation Explanation: Minimum diffusion
c) poly variations space is 3λ to avoid the possibility of
d) all of the mentioned their associated regions overlapping
and conducting current.
Answer: d
Explanation: One of the problems in 191. Contact cuts should be ____
the manufacture using design rule is apart.
that variation in threshold voltage a) 2λ

40
 ELECTRONIC SCIENCE UNIT-2 MCQs

b) 3λ 194. For 2 micron technology, what is

c) 4λ the Rs value for polysilicon?
d) λ a) 10-40
b) 20-50
Answer: a
c) 15-30
Explanation: Two contact cuts should
d) 15-100
be 2λ apart to prevent holes from
merging. Answer: c
Explanation: For 2 micron technology,
192. Area A of a slab can be given as
the Rs value for polysilicon is 15-30.
____________
a) t * W 195. Which has higher Rs values?
b) t / W a) n-diffusion
c) L * W b) p-diffusion
d) L * t c) n-diffusion & p-diffusion
d) none of the mentioned
Answer: a
Explanation: Area A of a uniform slab Answer: b
is given as the product of thickness t Explanation: The Rs values for p-
and width W of the slab. Its unit is diffusion is 2.5 times greater than
(micrometer)2. that of the n-diffusion.

193. For 5 micron technology, What 196. For 1.2 micron technology, what
is the Rs value for a metal? is the Rs value for diffusion?
a) 0.03 a) 20-40
b) 0.04 b) 20-45
c) 0.02 c) 15-30
d) 0.01 d) 25-50

Answer: a Answer: b
Explanation: For a 5 micron Explanation: For 1.2 micron
technology, the Rs value for a metal technology, the Rs value for diffusion
is 0.03. It is the standard typical sheet is 20-45.
resistance values.

41
 ELECTRONIC SCIENCE UNIT-2 MCQs

197. What is the relationship c) sputtering and evaporation

between channel resistance and d) deposition should not be made
sheet resistance?
Answer: c
a) R = Rs
Explanation: Deposition of metal or
b) R = Z*Rs
silicon alloy can be done by either
c) R = Z/Rs
sputtering or evaporation. Sputtering
d) R = Rs/Z
is a process whereby particles are
Answer: b ejected from a solid target material
Explanation: The relationship due to bombardment of the target by
between channel resistance and energetic particles.
sheet resistance can be given as R =
200. Deposition of metal can be done
Z*Rs. Sheet resistance is a measure of
by co-evaporation.
the resistance of thin films that are
a) true
nominally uniform in thickness.
b) false
198. Z can be given as the ration of
Answer: a
___________
Explanation: Deposition of metal or
a) lower channel by upper channel
silicon alloy can also be done by co-
b) upper channel by lower channel
evaporation from the elements.
c) all of the mentioned
d) none of the mentioned 10. Processing of the device is better
using ___________
Answer: b
a) polysilicon
Explanation: Z (length to width) ratio
b) silicides
can be given as the ratio of upper
c) polysilicon & silicides
channel to lower channel. It is just a
d) none of the mentioned
numerical quantity and has no unit.
Answer: a
199. Deposition of metal or silicon
Explanation: Processing of the device
alloy can be done by ___________
is better using polysilicon than
a) sputtering
silicides even though the properties
b) evaporation
of silicides are better than polysilicon.

42
 ELECTRONIC SCIENCE UNIT-2 MCQs

201. The resistance of uniform slab of resistance parameter

the conducting material is? c) Sheet resistance is dimensionless
a) Linear(proportional) with length quantity
b) Inversely proportional to thickness d) Sheet resistance is equal to
c) Inversely proportional to width resistivity
d) All of the mentioned
Answer: b
Answer: d Explanation: It is convenient to use
Explanation: The resistance of a Sheet resistance instead of resistivity
uniform slab of conducting material because Resistivity and thickness are
can be expressed as characteristics which cannot be
R = (ρ.l)/(t.w). controlled by the circuit designer, and
it is expressed as the single sheet
202. The sheet resistance of the
resistance parameter.
conducting material is?
a) RS = resistivity/length 204. Compute the sheet resistance of
b) RS = resistivity/width a 0.17 µm thick Cu wire if resistivity
c) RS = resistivity/thickness of Cu wire is 1.7 µΩ-cm.
d) None of the mentioned a) 0.01 Ω/square
b) 0.001 Ω/square
Answer: c
c) 10.0 Ω/square
Explanation: The sheet resistance of
d) 0.10 Ω/square
the conducting material is given by RS
= resistivity/thickness. Answer: d
Explanation: Sheet resistance of
203. In CMOS manufacturing process
copper is = (1.7*10-8)/(0.17*10-
Sheet resistance is used instead of 6
)=0.10 Ω/square.
resistivity because _______________
a) Resistivity is same for all doped 205. For semiconductors doped
regions through diffusion or through surface
b) Resistivity and thickness are peaked ion implantation we derive
characteristics which cannot be the sheet resistance as ___________
controlled by the circuit designer, and a) Average resistivity of
it is expressed as the single sheet semiconductor/thickness

43
 ELECTRONIC SCIENCE UNIT-2 MCQs

b) Resistivity/thickness testing device

c) Conductivity/thickness d) Any of the mentioned
d) None of the mentioned
Answer: b
Answer: a Explanation: Sheet resistance of
Explanation: For semiconductors semiconductor is directly measured
doped through diffusion or through using Four point probe measurement.
surface peaked ion implantation we
208. The resistance of the
derive the sheet resistance using the
semiconductor material is 800Ω. The
average resistivity of the material.
sheet resistance if the dimensions of
206. Sheet resistance of a the material is 0.125µm wide and 1
semiconductor is ___________ mm long is?
a) Inherent property of the material a) 10 Ω/square
b) Function of thickness of the b) 0.01 Ω/square
material c) 0.10 Ω/square
c) Also called as Specific Resistance d) 1 Ω/square
d) All of the mentioned
Answer: c
Answer: b Explanation: We know that
Explanation: Resistivity is the R=Rs(L/W).
inherent property of any conducting Therefore Rs=R x W/L
material. It is also called Specific Substituting the values of R, W and L,
Resistance. Sheet resistance is Rs is found to be 0.10 Ω/square.
function of thickness as resistivity for
209. The typical values of sheet
a material is fixed.
resistance for the n-well
207. Sheet resistance of semiconductor is ____________
semiconductor is directly measured a) 1-5 KΩ/square
using ___________ b) 10-50 KΩ/square
a) Ohmmeter c) 1-5 Ω/square
b) Four point probe measurement d) 100-500 Ω/square
c) Non-contact eddy current based
Answer: a
Explanation: The n-well

44
 ELECTRONIC SCIENCE UNIT-2 MCQs

semiconductors have high sheet c) 90oCg

resistance in the range of 1-5 d) 4oCg
KΩ/square.
Answer: b
210. The typical values of sheet Explanation: 30λ x 6λ/2λ x 2λ =
resistance for polysilicon 45 oCg.
semiconductor is?
213. The capacitances in MOSFET
a) 15-30 Ω/square
occurs due to _____________
b) 150-300 Ω/square
a) Interconnects
c) 1.5-3 KΩ/square
b) Difference in Doping concentration
d) 0.15-0.3 Ω/square
c) Difference in dopant materials
Answer: a d) All of the mentioned
Explanation: The typical values of
Answer: d
polysilicon semiconductor is 15-30
Explanation: The on-chip
Ω/square.
capacitances found in MOS circuits
211. For λ based design, what is the are due to interconnects, difference
standard unit of capacitance, in Doping concentration, difference in
(λ=5µm)? dopant materials.
a) 0.01pF
214. The parasitic capacitances found
b) 0.0032pF
in MOSFET are ___________
c) 0.0023pF
a) Oxide related capacitances
d) All of the mentioned
b) Inter electrode capacitance
Answer: a c) Electrolytic capacitance
Explanation: 5 µm x 5 µm x 4 pF x 10- d) All of the mentioned
4/µm2 = 0.01pF.
Answer: a
212. If standard area is 2λ x 2λ, then Explanation: The parasitic device
the standard capacitance of a gate of capacitances can be classified into
length 30λ and width 6λ is? two major groups: oxide-related
a) 180oCg capacitances and junction
b) 45oCg capacitances.

45
 ELECTRONIC SCIENCE UNIT-2 MCQs

215. The proper DC model of MOSFET

with capacitances is?
a)

d) None of the mentioned

Answer: c
b) Explanation: The capacitances exist
between all the regions of the
MOSFET.

216. The capacitance that exist

between Gate and Bulk is called as
___________
a) Oxide parasitic capacitance
b) Metal oxide capacitance
c) MOS capacitance
d) None of the mentioned

Answer: a
Explanation: The capacitance that
c)
exist between Gate and Bulk is called
as an oxide parasitic capacitance.

217. In Cut-off Mode, the capacitance

Cgs will be equal to ___________
46
 ELECTRONIC SCIENCE UNIT-2 MCQs

a) 2Cgd c) Zero gate to substrate capacitance

b) 0 d) All of the mentioned
c) Cgb
Answer: d
d) All of the mentioned
Explanation: In linear-mode
Answer: b operation, the conducting channel
Explanation: In cut-off mode, the exists, therefore there will be a finite
conducting channel does not exist, so amount of gate to source and gate to
gate-to-source and the gate-to-drain drain capacitances. Since the
capacitances are both equal to zero. conducting channel exists, gate to
substrate capacitance is reduced to
218. In cut-off mode, the value of
zero.
gate to substrate capacitance is equal
to ___________ 220. In saturation mode operation,
a) Cox .(W- L) gate to drain capacitance is zero due
b) Cox W/ L to ___________
c) Cox* W*L a) Gate and drain are interconnected
d) 0 b) Channel length is reduced
c) Inversion layer doesn’t exist
Answer: c
d) Drain is connected to ground
Explanation: In Cut-off mode, the
conducting channel does not exist, so Answer: b
gate-to-source and the gate-to-drain Explanation: Due to the pinched off
capacitances are both equal to zero. channel, the capacitance between
Therefore, the gate to substrate source to drain is reduced to zero.
capacitance is equal to Cox* W*L.
221. When MOSFET is operating in
219. In linear mode operation, the saturation region, the gate to source
parasitic capacitances that exists are capacitance is?
___________ a) 1/2*Cox*W*L
a) Nonzero Gate to source b) 2/3*Cox*W*L
capacitance c) Cox*W*L
b) Nonzero Gate to drain capacitance d) 1/3*Cox*W*L

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: b exist only in saturation region.

Explanation: Due to the reduction in Hint: the graph can be analyzed from
channel length, gate to drain and the gate to source voltage on x axis
gate to substrate capacitance are and regions can be determined.
zero, the gate to channel capacitance
223. The load capacitance is
as seen between the gate and the
measured between ___________
source is approximately defined as
a) Output node and input node
2/3*Cox*W*L.
b) Output node and Vcc
222. In the below graph, the regions c) Output node and ground
marked as A,B,C are? d) Input node and ground

Answer: c
Explanation: The load capacitance is
measured at output node and
ground.

224. The load capacitance is

equivalent to ___________
a) Sum of all lumped linear
capacitances between input and
output node
b) Sum of all junction capacitance
between Vcc and ground
c) Sum of all junction capacitance
between input and output
a) A : Saturation, B : Linear, C : Cut-off
d) Sum of all lumped linear
b) A :Cut-off, B : Linear, C : Saturation
capacitances between output node
c) A : Linear, B : Saturation, C : Cut-off
and ground
d) None of the mentioned
Answer: a
Answer: b
Explanation: The load capacitance is
Explanation: The gate to substrate
measured by sum of all lumped linear
capacitance exists only in cut-off
region, and gate to drain capacitance

48
 ELECTRONIC SCIENCE UNIT-2 MCQs

capacitances between input and 227. Which of the following

output node. parameters are found using load
capacitance?
225. Interconnect capacitance
a) Delay time
contributes to the load capacitance
b) Power consumption
when the CMOS inverters are
c) Speed of the CMOS logic
connected in cascade configuration.
d) All of the mentioned
a) True
b) False Answer: d
Explanation: Using load capacitance,
Answer: a
delay time, power consumption,
Explanation: In cascade configuration
speed of the CMOS logic can be
the load capacitance is measured by
measured.
sum of all the lumped capacitances
and interconnect capacitance. 228. Microelectronic technology
cannot be characterized by
226. Interconnect capacitance is
a) minimum feature size
formed due to ___________
b) power dissipation
a) Junction capacitance between gate
c) production cost
and substrate
d) designing cost
b) Wire connecting the gates of 2
different inverters Answer: d
c) Parasitic capacitance existing Explanation: Microelectronic
between metal and polysilicon technology can be characterized by
connection between 2 inverters minimum feature size, number of
d) All of the mentioned gates on one chip, power dissipation,
die size, production cost, etc and not
Answer: c
by designing cost.
Explanation: Parasitic capacitance
existing between metal and 229. Which model is used for scaling?
polysilicon connection between 2 a) constant electric scaling
inverters causes the interconnect b) constant voltage scaling
capacitance. c) costant electric and voltage scaling
d) costant current model

49
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: c Answer: a
Explanation: Constant electric scaling Explanation: For constant voltage
model and constant voltage scaling model, β = α.
model is used for scaling.
233. Gate area can be given as
230. α is used for scaling a) L/W
a) linear dimensions b) L * W
b) vdd c) 2L/W
c) oxide thickness d) L/2W
d) non linear
Answer: b
Answer: a Explanation: Gate area Ag can be
Explanation: α is used as the scaling given as the product of length and
factor for linear dimensions where as the width of the channel.
β is used for supply voltage Vdd, gate
234. Gate area is scaled by
oxide thickness etc.
a) α
231. For constant voltage model, b) 1/α
a) α = β c) 1/α2
b) α = 1 d) α2
c) α = 1/β
Answer: c
d) β = 1
Explanation: Gate area is given as the
Answer: d product of length and width of the
Explanation: For constant voltage channel and it can be scaled by 1/α2.
model, β = 1 and 1/β is chosen for the
235. Gate capacitance per unit area is
scaling for all voltages.
scaled by
232. For constant electric field model, a) α
a) β = α b) 1
b) α = 1 c) 1/β
c) α = 1/β d) β
d) β = 1
Answer: d
Explanation: Gate capacitance per

50
 ELECTRONIC SCIENCE UNIT-2 MCQs

unit area is scaled by β and this is channel Qon is scaled by 1. Carrier

given by €ox/D. density is given by C0*Vgs where C0
is scaled by β and Vgs is scaled by
236. Parasitic capacitance is given by
1/β.
a) Ax/d
b) Ax * d 239. Channel resistance Ron is scaled
c) d/Ax by
d) Ax a) α
b) β
Answer: a
c) 1
Explanation: Parasitic capacitance is
d) α2
given by Ax/d where Ax is the area of
the depletion region and d is the Answer: c
depletion width. Explanation: Channel resistance Ron
is scaled by 1. Channel resistance is
237. Parasitic capacitance is scaled by
given by (L/W)*(1/Qonµ).
a) β
b) 1/β 240. Gate delay is given by
c) α a) Ron/Cg
d) 1/α b) Ron * Cg
c) Cg/Ron
Answer: d
d) Cg2 /Ron
Explanation: Parasitic capacitance is
scaled by 1/α because area is scaled Answer: b
by 1/α2 and d by 1/α. Thus Explanation: Gate delay Td is given as
(1/α2)/(1/α) we will get 1/α. the product of Ron, channel
resistance and Cg the gate
238. Carrier density is scaled by
capacitance.
a) α
b) β 241. Maximum operating frequency
c) 1 is scaled by
d) α2 a) α/β
b) β/α
Answer: c
c) α2 /β
Explanation: Carrier density in
d) β2 /α

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: c scaled by α^2/β. Current density is

Explanation: Maximum operating given by Idss/A where Idss is scaled
frequency f0 is scaled by α2/β. This is by 1/β and area A by 1/α^2.
given by (W/L)*(µ*C0*Vdd/Cg).
245. Power dissipation per gate is
242. Saturation current is scaled by scaled by
a) α a) 1/α
b) β b) 1/β
c) 1/α c) 1/α2
d) 1/β d) 1/β2

Answer: d Answer: d
Explanation: Saturation current Idss is Explanation: Power dissipation per
scaled by 1/β. This is given by gate is scaled by 1/β^2. This is the
(Co*µ/2)*W/L*(Vgs-Vt)2 . sum of static component Pgs and
dynamic component Pgd.
243. Vgs is scaled by
a) α 246. Power dissipation per unit area
b) β is scaled by
c) 1/α a) 1/α
d) 1/β b) 1/β
c) β2/α2
Answer: d
d) α2/β2
Explanation: Gate to source voltage
Vgs is scaled by 1/β. All voltages are Answer: d
scaled by 1/β. Explanation: Power dissipation per
unit area Pa is scaled by α2/β2. This is
244. Current density J is scaled by
given by Pg/Ag where Pg is scaled by
a) α/β
1/β2 and Ag by 1/α2.
b) β/α
c) α2/β 247. In constant voltage model, the
d) β2/α saturation current is scaled by
a) α
Answer: c
b) β
Explanation: Current density J is

52
 ELECTRONIC SCIENCE UNIT-2 MCQs

c) 1 unit area is scaled by 1 in constant

d) β2 electric field model. This is scaled by
α2/β2 and here in constant electric
Answer: c
field model β = α.
Explanation: Saturation current is
scaled by 1 in constant voltage 250. Built-in junction potential Vb
model. This is because saturation depends on
current is scaled by 1/β and here in a) Vdd
constant voltage model β is 1. b) Vgs
c) substrate doping level
248. In constant field model,
d) oxide thickness
maximum operationg frequency is
scaled by Answer: c
a) α Explanation: Built-in junction
b) β potential Vb depends on the
c) α2 substrate doping level and this will be
d) β2 acceptable so long as Vb is small
compared with Vdd.
Answer: a
Explanation: In constant field model, 251. As the channel length is reduced
maximum operating frequency is in a MOS transistor, depletion region
scaled by α. Maximum operating width must be
frequency is scaled by α2/β and here a) increased
in this model β = α. b) decreased
c) must not vary
249. In constant electric field model,
d) exponentially decreased
power dissipation per unit area is
scaled by Answer: b
a) α Explanation: As the channel length is
b) β reduced in a MOS transistor,
c) 1 depletion width must also be scaled
d) β2 down to prevent the source and drain
depletion regions from meeting.
Answer: c
Explanation: Power dissipation per

53
 ELECTRONIC SCIENCE UNIT-2 MCQs

252. Vdd is scaled by 255. The size of a transistor is usually

a) α defined in terms of its
b) β a) channel length
c) 1/α b) feature size
d) 1/β c) width
d) thickness ‘d’
Answer: d
Explanation: Supply voltage Vdd is Answer: a
scaled by 1/β. All voltages are scaled Explanation: The size of a transistor is
by 1/β. usually defined in terms of its channel
length L because feature size only
253. If doping level of substrate Nb
gives area capacitance etc.
increases then depletion width
a) increases 256. What is the minimum value of L
b) decreases to maintain transistor action?
c) does not change a) d
d) increases and then decreases b) d/2
c) 2d
Answer: b
d) d2
Explanation: If the substrate doping
length Nb increases then depletion Answer: c
width decreases because depletion Explanation: The channel length L
width is inversely proportional to Nb. should be atleast 2d to maintain the
transistor action and to prevent
254. Maximum electric field can be
punch-through.
given as
a) V/d 257. L depends on
b) d/V a) substrate concentration
c) 2V/d b) Vgs
d) d/2V c) Vt
d) Vds
Answer: c
Explanation: Maximum electric field Answer: a
can be given by 2V/d and this is Explanation: Channel length L
induced in one-sided step junction.

54
 ELECTRONIC SCIENCE UNIT-2 MCQs

depends on the supply voltage Vdd Answer: d

and substrate concentration Nb. Explanation: All the mentioned are
the basic figures of merit for MOS
258. Drift velocity can be given as
devices.
a) E/µ
b) µ/E 261. For the constant field model, the
c) µ * E scaling factors β and α are related as:
d) E a) β = α
b) α = 2β
Answer: c
c) β = 1
Explanation: Carrier drift velocity can
d) β = α = 0
be given as the product of µ and E
and the maximum carrier drift Answer: a
velocity is approximately equal to Explanation: In Constant field model,
Vsat regardless of the supply voltage. β = α.

259. The transit time can be given as 262. In Constant Voltage model, the
a) 2d scaling factors β and α are related as:
b) 2d/µE a) β = α
c) µE/d b) α = 2β
d) µE/2d c) β = 1
d) β = α = 1
Answer: b
Explanation: The transit time can be Answer: c
given by L/Vdrift which is equivalent Explanation: In Constant Voltage
to 2d/µE as L = 2d and Vdrift is µE. model, β = 1.

260. The basic figures of merit for 263. The scaling factor for the supply
MOS devices are voltage VDD is:
a) Minimum Feature size a) 1
b) Low Power dissipation b) 0
c) Maximum operational frequency c) 1/α
d) All of the mentioned d) 1/β

55
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: d c) 1
Explanation: The supply voltage VDD d) All of the mentioned
has the scaling factor of 1/β.
Answer: a
264. The scaling factor of length and Explanation: The gate area = L.W,
width of the channel are: therefore scaling factor = 1/α2.
a) 1, 1
266. The scaling factor of Gate
b) 1/α, 1/β
Capacitance per unit area is:
c) 1/α, 1/α
a) 1/β
d) 1/β, 1/β
b) 1/α
Answer: c c) β
Explanation: The scaling factor of d) α
length is 1/α, and scaling factor for
Answer: c
width is 1/α.
Explanation: Gate capacitance per
265. The third type of scaling model unit area has the scaling factor of β.
is:
267. The scaling factor of Gate
a) λ-based model
capacitance is:
b) µm based model
a) 1/β
c) combined voltage and dimension
b) 1/α
model
c) β/α2
d) combined voltage and electric field
d) α/β2
model
Answer: c
Answer: c
Explanation: The scaling factor of
Explanation: The third model is
Gate capacitance is β/α2.
known as the combined voltage and
dimensions model proposed by 268. In Constant voltage model the
Bergmann in 1991. gate capacitance is scaled by a factor
of:
265. The scaling factor of gate area in
a) 1/β2
constant voltage model is:
b) 1/α2
a) 1/α2
b) 1/β2

56
 ELECTRONIC SCIENCE UNIT-2 MCQs

c) β/α2 gate oxide

d) α/β2 d) None of the mentioned

Answer: b Answer: b
Explanation: Since β is 1. Explanation: Carrier density is the
Average charge per unit area in the
269. The parasitic Capacitance has
channel in ‘ON’ state.
the scaling factor:
a) Equal to gate capacitance 272. Channel resistance is scaled as:
b) 1/α2 a) 1/α2
c) 1/α b) 1/β
d) 1/β c) 1/α
d) 1
Answer: c
Explanation: Parasitic capacitance is Answer: d
scaled by 1/α. Explanation: Channel resistance is
scaled by the factor of 1.
270. The carrier density in channel in
constant voltage model is scaled as: 273. The scaling factor of Gate delay
a) 1/β in Constant field model is:
b) 1 a) 1/α2
c) β b) 1
d) All of the mentioned c) 1/α
d) β/α
Answer: d
Explanation: Carrier density is scaled Answer: c
as 1, since in constant voltage model Explanation: In Constant field model
β = 1, therefore all are correct. the scaling factor of gate delay is 1/α.

271. Carrier density is measured as: 274. The gate delay is proportional
a) Average charge per unit area in the to:
channel in ‘OFF’ state a) Ron .Cg
b) Average charge per unit area in the b) [Link]
channel in ‘ON’state c) [Link]
c) Average charge per unit area in the d) [Link]

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: a Answer: c
Explanation: The gate delay is Explanation: Current density is scaled
proportional to channel resistance by a factor of α2/β and since it is in
and gate capacitance Constant voltage model, β = 1,
therefore α2 is correct answer
275. The maximum operating
frequency is scaled by: 278. Switching energy per gate is
a) 1/α2 scaled by the factor of:
b) β/α2 a) 1
c) α2/β b) α2/β
d) 1 c) 1/ β.α2
d) α2
Answer: c
Explanation: Maximum operating Answer: c
frequency s inversely proportional to Explanation: Switching energy per
the gate delay. It is scaled by α2/β gate is scaled by a factor of 1/ β.α2

276. The saturation current is scaled 279. In Constant field model, the
by the factor of: scaling factor of switching energy per
a) 1 gate would be:
b) 1/α2 a) 1/ β.α2
c) 1/β b) 1/ α3
d) 1/α c) 1/ α2
d) All of the mentioned
Answer: c
Explanation: The saturation current is Answer: b
scaled by the factor of 1/β Explanation: Since in constant field
model α = β
277. The scaling factor of current
density in constant voltage model is: 280. The power dissipation per gate is
a) 1/α2 scaled as:
b) 1 a) 1
c) α2 b) 1/ β.α2
d) α2/β c) α2/β
d) 1/ β2

58
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: d Answer: d
Explanation: Power dissipation per Explanation: The scaling factor of
gate is scaled by the factor of 1/β2 power dissipation per unit area is
α2/β2
281. The dynamic component of
power dissipation is given by: 284. The power speed product has
a) P = [Link] the scaling factor of:
b) P = Vdd2/Rd a) 1
c) P = [Link] b) 1/α2
d) All of the mentioned c) 1/ β.α2
d) None of the mentioned
Answer: c
Explanation: The dynamic component Answer: c
is the product of energy per gate and Explanation: The power speed
maximum operating frequency. product has the scaling factor of 1/
β.α2
282. The static component of power
dsssipation is given by: 285. The scaling factor of power
a) P = [Link] dissipation per unit area in constant
b) P = Vdd2/Ron field model is:
c) P = [Link] a) 1
d) All of the mentioned b) 1/α2
c) 1/ β.α2
Answer: b
d) α2/β2
Explanation: The static component is
the power dissipated across Answer: a
transistor when it is in ON state Explanation: In constant field model α
=β
283. The scaling factor of power
dissipation per unit area is: 286. The scaling factor of Logic Level
a) 1 1 in constant field model is:
b) 1/α2 a) 1
c) 1/ β.α2 b) 1/β
d) α2/β2 c) 1/α
d) α/β

59
 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: c c) Decreasing Temperature

Explanation: The logic level 1 is scaled d) Deformation of Lattice
as 1/β. Since we are using constant
Answer: a
field model, the scaling factor will be
Explanation: By introducing Dopants
1/α
free charge carriers increase further
287. The scaling factor similar to increasing the conductivity of silicon.
scaling factor of power speed product
290. The n-type semiconductor have
is:
_______ as majority carriers.
a) Power dissipation per unit area
a) Holes
b) Switching Energy
b) Negative ions
c) Power dissipation per gate
c) Electrons
d) All of the mentioned
d) Positive ions
Answer: b
Answer: c
Explanation: Switching energy has the
Explanation: In n-type semiconductor
same scaling factor as that of power
the majority charge carriers present
speed products.
are electrons.
288. The parameter which is not
291. The majority carriers of p-type
scaled to any factor is:
semiconductor are:
a) Power speed product
a) Holes
b) Switching energy
b) Negative ions
c) Channel resistance
c) Electrons
d) All of the mentioned
d) Positive ions
Answer: c
Answer: a
Explanation: Channel resistance is
Explanation: The majority charge
scaled by 1. Therefore there are no
carriers of n-type semiconductors are
factors like α or β.
holes.
289. The conductivity of the pure
292. The n-MOS transistor is made up
silicon is raised by:
of:
a) Introducing Dopants (impurities)
a) N-type source, n-type drain and p-
b) Increasing Pressure

60
 ELECTRONIC SCIENCE UNIT-2 MCQs

type bulk Answer: c

b) N-type source, p-type drain and p- Explanation: This is the correct
type bulk representation of n-MOSFET
c) P-type source, n-type drain and n-
type bulk
d) P- type source, p-type drain and n-
type bulk

Answer: a
Explanation: n-MOS Transistor :
consists of n-type source, n-type
294. The correct representation of p-
drain and p-type bulk.
MOSFET is:
293. The correct representation of n-
MOSFET is:
a)

b)
a)

c)

b)
d)

Answer: b
Explanation: This is the correct

c)
d) None of the mentioned representation of p-MOSFET:

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 ELECTRONIC SCIENCE UNIT-2 MCQs

295. The oxide layer formed in the 298. The n-MOSFET is working as
MOSFET is: accumulation mode when:
a) Metal oxide a) Gate is applied with positive
b) Silicon dioxide voltage
c) Poly Silicon oxide b) Gate is grounded
d) Oxides of Non metals c) Gate is applied with negative
voltage
Answer: b
d) Gate is connected to source
Explanation: Silicon Dioxide
(Commonly called as glass) is the Answer: c
insulating oxide layer formed in Explanation: When the negative
MOSFET. voltage is applied to the gate, there
develops a presence of negative
296. The drain current is varied by:
charge on the gate. The mobile
a) Gate to source voltage
positively charged holes are attracted
b) Gate current
to the region beneath the gate. This
c) Source Voltage
explains the formation of
d) None of the mentioned
accumulation mode.
Answer: a
299. The current through the n-MOS
Explanation: The Gate to Source
transistor will flow when:
voltage acts as input which varies the
a) Vgs > Vtreshold, Vds=0
drain current.
b) Vgd < Vtreshold, Vds=0
297. The low voltage on the gate of p- c) Vgs > Vtreshold, Vds>0
MOSFET forms: d) Vgd > Vtreshold, Vds<0
a) Channel of negative carriers
Answer: c
b) Channel is not formed
Explanation: The current flows
c) Channel is clipped
through the n-MOS transistor when
d) Channel of positive carriers
Vgs > Vtreshold, Vds>0.
Answer: d
300. The p-MOS Transistor is said to
Explanation: For a p-MOS low gate
be in Saturation mode when:
voltage forms a conducting channel
a) Vdsp > Vgsp – Vtp
of positive carriers.

62
 ELECTRONIC SCIENCE UNIT-2 MCQs

b) Vgsp < Vdsp –Vtp intrinsic carrier concentration of

c) Vgsp > Vtp silicon, NA is acceptor concentration,
d) Vdsp < Vgsp – Vtp ND is Donor Concentration.

Answer: d 303. The principle of the MOSFET

Explanation: The pMOS transistor is operation is:
in Saturation mode when Vdsp < a) Control the conduction of current
Vgsp – Vtp and Vgsp < Vtp. between the source and the drain,
using the potential difference applied
301. The Fermi potential of the p-
at the gate voltage as a control
type MOSFET is:
variable
a) φfp = (kT/q)ln(ND/NA)
b) Control the current conduction
b) φfp = (kT/q)ln(NA/ND)
between the source and the gate,
c) φfp = (kT/q)ln(NA/ni)
using the electric field applied at the
d) φfp = (kT/q)ln(ni/NA)
drain voltage as a control variable
Answer: d c) Control the current conduction
Explanation: The Fermi potential of between the PN junction, using the
the p-type semiconductor is φfp = electric field generated by the bias
(kT/q)ln(ni/NA) where ni denotes the voltage as a control variable
intrinsic carrier concentration of d) Control the current conduction
silicon, NA is acceptor concentration, between the PN junctions, using the
ND is Donor Concentration. electric potential generated by the
gate voltage as a control variable
302. The Fermi potential(φfp) for the
n-type MOSFET is: Answer:a
a) φfp = (kT/q)ln(ND/NA) Explanation: By varying the gate
b) φfp = (kT/q)ln(NA/ND) voltage the current between the
c) φfp = (kT/q)ln(ND/ni) source and drain are varied.
d) φfp = (kT/q)ln(ni/ND)
304. The conduction of current IDS
Answer: c depends on:
Explanation: The Fermi potential of
i) Gate to source voltage
the p-type semiconductor is φfp =
(kT/q)ln(ND/ni) where ni denotes the ii) Drain to source voltage

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 ELECTRONIC SCIENCE UNIT-2 MCQs

iii) Bulk to source voltage Answer: a

Explanation: If n-MOS operates with
iv) Threshold voltage
negative threshold voltage then it is
v) Dimensions of MOSFET in depletion mode. If n-MOS operates
with positive threshold voltage then
a) Only i
it is in enhancement mode.
b) Only i, ii and iii
c) Only v 307. The electrical equivalent
d) All of the mentioned component for MOS structure is:
a) Resistor
Answer: d
b) Capacitor
Explanation: The current depends on
c) Inductor
Vgs, Vds, Vbs, Vt and dimensions of
d) Switch
MOSFET.
Answer: b
305. The impedance at the input of n-
Explanation: The MOS structure acts
MOS transistor circuit is:
as a capacitor with a metal gate and
a) Lesser than p-MOS transistor
semiconductor acting as parallel plate
b) Greater than BJT transistor
conductors and oxide as dielectric
c) Lesser than JFET transistor
between them.
d) Zero
308. The Fermi potential is the
Answer: b
function of:
Explanation: The impedance at the
a) Temperature
input of n-MOS transistor is more
b) Doping concentration
than BJT transistor.
c) Difference between Fermi level
306. The depletion mode n-MOS and intrinsic Fermi level
differs from enhancement mode n- d) All of the mentioned
MOS in:
Answer: d
a) Threshold voltage
Explanation: The Fermi potential,
b) Channel Length
which is a function of temperature
c) Switching time
and doping, denotes the difference
d) None of the mentioned

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 ELECTRONIC SCIENCE UNIT-2 MCQs

between the intrinsic Fermi level and a) Metal to semiconductor

the Fermi level. b) Semiconductor to metal
c) No field exists
309. The direction of electric field
d) None of the mentioned
when the gate voltage is zero:
a) Metal to semiconductor Answer: b
b) Semiconductor to metal Explanation: When gate voltage is
c) No electric field exists negative, holes in substrate are
d) None of the mentioned attracted towards surface creating
electric field from semiconductor to
Answer: a
metal.
Explanation: Metal being more
positive compared to semiconductor. 312. At threshold Voltage, the surface
The electric field exists from metal to potential is:
semiconductor. a) – Fermi potential
b) Fermi potential
310. Consider a MOS structure with
c) 2 Fermi potential
equilibrium Fermi potential of the
d) -2 Fermi potential
doped silicon substrate is given as
0.3eV. Electron affinity of Si is 4.15eV Answer: a
and metal is 4.1eV. Find the built in Explanation: When surface potential
potential of the MOS system. reaches –fermi potential, the surface
a) -0.8eV inversion occurs. The gate voltage
b) 0.8eV which brings these changes is known
c) 0.9eV as threshold voltage.
d) -0.9eV
313. Surface inversion occurs when
Answer: d gate voltage is:
Explanation: Surface potential: qΦs = a) Less than zero
4.15eV + 0.55eV + 0.3eV = 5.0eV b) Less than threshold voltage
qΦm-qΦs = 4.1eV – 5.0eV = -0.9eV. c) Equal to threshold voltage
d) Greater than threshold voltage
311. When gate voltage is negative
for enhancement mode n-MOS, the Answer: c
direction of electric field will be: Explanation: Surface inversion occurs

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 ELECTRONIC SCIENCE UNIT-2 MCQs

when gate voltage is equal to nMOSFET when gate voltage is zero is

threshold voltage.

314. The energy band diagram of the

MOS system when gate voltage is
zero is: :

315. For enhancement mode n-

MOSFET, the threshold voltage is:
a) Equal to 0
a) b) Greater than zero or Positive
quantity
c) Negative voltage or lesser than
zero
d) All of the mentioned
b)
Answer: b
Explanation: For enhancement mode
n-MOSFET, the threshold voltage is
positive quantity.

c) 316. The threshold voltage depends

on:
a) The workfunction difference
between gate and channel
b) The gate voltage component to
change surface potential
d) c) The gate voltage component to
offset the depletion charge and fixed
Answer: a charges in gate oxide
Explanation: The energy band d) All of the mentioned
diagram of enhancement mode
Answer: d
Explanation: The threshold voltage
depends on: The workfunction

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 ELECTRONIC SCIENCE UNIT-2 MCQs

difference between gate and channel, diagram of MOS system when gate
The gate voltage component to voltage is equal to threshold voltage
change surface potential, The gate
voltage component to offset the
depletion charge and fixed charges in
gate oxide
is
317. The Energy band diagram of
MOS system when gate voltage is 318. The expression for threshold
equal to threshold voltage is: voltage for the enhancement mode
nMOSFET is:
a) Φgc-2ϕf-Qbo/Cox-Qox/Cox
b) Φgc+ϕf-Qbo/Cox
c) Φgc-ϕf-Qbo/Cox+Qox/Cox
a)
d) Φgc+2ϕf-Qbo/Cox-Qox/Cox

Answer: a
Explanation: The expression for
threshold voltage for the
b) enhancement mode nMOSFET is Φgc-
2ϕf-Qbo/Cox-Qox/Cox.

319. Addition of impurities is

essential for creating switching
devices.
c)
a) true
b) false

Answer: a
Explanation: It is necessary to
introduce impurities into the semi-
d) insulating GaAs to facilitate the
creating of switching devices.
Answer: c
Explanation: The Energy band

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 ELECTRONIC SCIENCE UNIT-2 MCQs

320. The behaviour of the switching radius of Ga is 1.26 armstrong unit

element is decided by whereas for As is 1.18 armstrong
a) selection of impurity unit.
b) concentration density
323. ______ is used as the dopant for
c) selection of impurity &
the formation of n-type material.
concentration density
a) aluminum
d) none of the mentioned
b) arsenic
Answer: c c) silicon
Explanation: Selection of the impurity d) gallium
and its concentration density
Answer: c
determines the behaviour of the
Explanation: Group IV impurities tend
switching element.
to occupy gallium sites. Silicon is used
321. ______ elements can act as as the dopant for the formation of n-
either donors or acceptors. type material.
a) group II
324. Increase in positive charge
b) group III
___________ the effective nuclear
c) group IV
charge.
d) group V
a) increases
Answer: c b) decreases
Explanation: Group IV elements such c) exponentially increases
as silicon can act as either donor (on d) does not affect
Ga sites) or as acceptors (on As sites).
Answer: a
322. Which element is smaller? Explanation: Increase in positive
a) arsenic charge of the nucleus results in an
b) gallium increase in the effective nuclear
c) silicon charge thereby increasing the
d) aluminium effective atomic radius.

Answer: a 325. ___________ is used for the

Explanation: Arsenic is smaller than formation of p-type material.
gallium and silicon. The covalent a) beryllium

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 ELECTRONIC SCIENCE UNIT-2 MCQs

b) magnesium field effect transistors. Factors like

c) beryllium and magnesium etching of the crystal, ion
d) aluminium implantation and passivation
introduces the concept of orientation
Answer: c
dependency.
Explanation: Group II elements such
as beryllium and magnesium can be 328. The ion is steered ________ of
used for the formation of p-type the lattice.
materials. a) up the open directions
b) down the open directions
326. Which is the lightest p-type
c) up the closed directions
dopant?
d) down the closed directions
a) beryllium
b) magnesium Answer: b
c) silicon Explanation: When a high energy ion
d) arsenic enters a single crystal lattice, the ion
is steered down the open directions
Answer: a
of the lattice. This steering is called
Explanation: Beryllium is the lightest
axial channeling.
p-type dopant for GaAs, deep
implantation of the dopant atoms can 329. If equivalent direction is not
be accomplished with less lattic used ______ will be increased.
damage. a) ion concentration
b) steering angle
327. _______ influences the
c) area coverage
properties of GaAs field affect
d) depth distribution
transistor.
a) length dependency Answer: d
b) structural dependency Explanation: If a random equivalent
c) material dependency direction is not used during ion
d) orientation dependency implantation, the depth distribution
will be greater than those predicted
Answer: d
by range statistics which are used to
Explanation: Orientation dependency
establish penetration depth.
influences the properties of GaAs

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 ELECTRONIC SCIENCE UNIT-2 MCQs

330. Electrons become hot in gallium Answer: c

arsenide when the energy of Explanation: Gallium arsenide is a
a) lower valley electrons decreases direct gap material with valence bond
b) lower valley electrons rises maximum and conduction band
c) higher valley electrons decreases minimum.
d) higher valley electrons rises
333. Narrow valleys correspond to
Answer: b a) electrons with lower mass state
Explanation: In gallium arsenide, b) protons with lower mass state
when the energy of lower valley c) electrons with higher mass state
electrons rises sufficiently at a higher d) protons with higher mass state
electric field, the electrons become
Answer: a
hot.
Explanation: Valleys with band
331. When electrons become hot, structure that are narrow and sharply
drift velocity curved corresponds to electrons with
a) increases low effective mass state while valleys
b) decreases that are wide are characterized by
c) remains the same larger effective masses.
d) does not depend on drift velocity
334. The curvature of ___________
Answer: b determines the effective mass of
Explanation: When electrons electrons.
becomes hot, there will be a a) energy versus concentration
reduction in the number of high b) energy versus mass
mobility electrons and hence c) energy versus momentum
decrease in drift velocity. d) energy versus structural design

332. ______ is a direct gap material Answer: c

with valence bond maximum. Explanation: The curvature of energy
a) silicon versus electron momentum profile
b) gallium oxide determines the effective mass of
c) gallium arsenide electrons travelling through the
d) silicon arsenide crystal.

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 ELECTRONIC SCIENCE UNIT-2 MCQs

335. Conduction band minimum Answer:c

occurs at Explanation: For GaAs, the effective
a) low momentum mass of these electrons is 0.067 times
b) high momentum the mass of a free electron.
c) all of the mentioned
338. Electrons travels faster in
d) none of the mentioned
a) silicon
Answer: b b) gallium arsenide
Explanation: The minimum point of c) aluminium
gallium arsenide’s conduction band is d) silicon oxide
near the zero point of the crystal-
Answer: b
lattice momentum. Conduction band
Explanation: Electrons travel faster in
minimum occurs at high momentum.
gallium arsenide than in silicon as the
336. Mobility depends on result of their superior electron
a) concentration of impurity mobility brought out by the shapes of
b) temperature their conduction bands.
c) electron efficient mass
339. Electrons is low valley have high
d) all of the mentioned
mass.
Answer: d a) true
Explanation: Mobility depends on b) false
several factors such as concentration
Answer: b
of impurity, temperature and is
Explanation: Electrons in the higher
relatively related to electron efficient
valleys have high mass and strong
mass.
intervalleys scattering and therefore
337. The effective mass of GaAs is exhibit very low mobility.
_________ than the mass of a free
340. The probability of photon
electron.
emission has energy which is
a) 0.67 times greater
_______ the band gap.
b) 0.67 times lesser
a) greater than
c) 0.067 times greater
b) lesser than
d) 0.067 times lesser

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 ELECTRONIC SCIENCE UNIT-2 MCQs

c) equal to 343. Saturation velocity is attained

d) does not depend on when
a) energy gained is greater than
Answer: c
energy lost
Explanation: The probability of
b) energy lost is greater than energy
photon emission with energy nearly
gained
equal to the band gap is high, GaAs
c) energy gained equals energy lost
makes an excellent light-emitting
d) energy is fully drained
diode.
Answer: c
341. Silicon can also be used as light-
Explanation: The energy gained from
emitting device.
the field equals the energy lost as a
a) true
result of collisions. At this point, drift
b) false
velocity attains a limiting value called
Answer: b saturation velocity.
Explanation: Silicon cannot be used
344. The GaAs fabrication has
as light-emitting device. It is indirect-
_________ gate geometry.
gap semiconductor with the
a) less than one micron
conduction gap minimum separated
b) less than two micron
in momentum from valence band
c) more than one micron
minimum.
d) more than two micron
342. As the applied field increases
Answer: a
a) drift velocity increases
Explanation: The GaAs fabrication has
b) energy decreases
characteristics such as having less
c) drift velocity remains constant
than on-micron gate geometry and
d) energy remains constant
less than two-micron metal pitch.
Answer: a
345. The GaAs structure has upto
Explanation: As long as the resultant
_______ metal.
balance is positive, the energy and
a) two-layer
drift velocity of the charge carriers
b) three-layer
increases with an increase in the
applied field.

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 ELECTRONIC SCIENCE UNIT-2 MCQs

c) four-layer 348. Larger energy bandgap _____

d) one-layer parasitic capacitances.
a) increases
Answer: c
b) decreases
Explanation: The GaAs fabrication has
c) maintains constant
the feature of having four-layer metal
d) does not affect
and four-inch diameter wafer.
Answer: b
346. Electron mobility of gallium
Explanation: Large energy bandgap
arsenide is _______ that of silicon.
offers bulk semi-insulating substrate
a) greater than
and minimizes parasitic capacitances
b) lesser than
and allows easy electrical isolation.
c) same as
d) does not depend on 349. In gallium arsenide, radiation
resistance is
Answer: a
a) stronger
Explanation: Electron mobility of
b) weaker
gallium arsenide is six to seven times
c) absent
that of silicon resulting in very fast
d) very weak
electron transit times.
Answer: a
347. Saturated drift velocity of
Explanation: In gallium arsenide
gallium is _______ to that of silicon.
radiation resistance is stronger due to
a) greater
the absence of gate oxide to trap
b) lesser
charges.
c) approximately same
d) does not depend on 350. _______ can be used as light
emitters.
Answer: c
a) forward biased pn junction
Explanation: Saturated drift velocity
b) reverse biased pn junction
of gallium and silicon are
c) forward biased pnp junction
approximately equal. For GaAs
d) reverse biased pnp junction
saturation velocity occurs at a lower
threshold field than for silicon. Answer: a
Explanation: Direct bandgap of GaAs

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 ELECTRONIC SCIENCE UNIT-2 MCQs

allows efficient radiative b) silicon oxide

recombination of electrons and holes c) silicon nitride
and thus forward biased pn junction d) boron nitride
can be used as light emitters.
Answer: d
351. In GaAs __________ has more Explanation: Growth of gallium
intrinsic mobility. arsenide crystals from high purity
a) electron boron nitride cubicles is becoming
b) holes the primary growth technique.
c) proton
354. Wafers in GaAs fabrication are
d) neutron
thermally unstable.
Answer: a a) true
Explanation: In GaAs, electrons have b) false
intrinsic mobility of 8000 cm^2/[Link]
Answer: b
whereas in silicon holes has more
Explanation: The fabrication of GaAs
intrinsic mobility as 500 cm2/[Link].
includes production of round wafers
352. Which has greater intrinsic and they are thermally stable and
resistivity? have superior semi-insulating
a) silicon properties.
b) gallium arsenide
355. The sequence of the steps
c) gallium
followed in fabrication of GaAs is
d) silicon and gallium
i. lapping
Answer: b
Explanation: Gallium arsenide has ii. polishing
greater intrinsic resistivity of
iii. grinding
1×108 [Link] whereas silicon has
intrinsic resistivity of iv. wafer scrubbing
2.2×105 [Link].
a) ii, iii, i, iv
353. Gallium arsenide crystals are b) i, ii, iii, iv
grown from c) iii, i, ii, iv
a) boron oxide d) iv, i, ii, iii

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: c 358. Stable native oxide was

Explanation: The steps followed in produced by
fabrication of GaAs are grinding the a) oxidation of silicon
As-grown boules, wafering, edge b) oxidation of gallium
rounding, lapping, polishing and then c) oxidation of boron
wafer scrubbing. d) oxidation of aluminium

356. Which devices are fabricated Answer: a

using planar process? Explanation: The driving force with
a) enhancement mode MESFET siicon technology were brought
b) depletion mode MESFET about as the result of presence of
c) enhancement mode MOSFET stable native oxide which was readily
d) depletion mode MOSFET produceded through oxidation of
silicon.
Answer: b
Explanation: The depletion mode 359. In GaAs technology, deposited
devices are fabricated using planar dielectric films brings about
process where n-type dopants are a) passivation
directly implanted into semi- b) combination
insulating GaAs. c) decomposition
d) diffusion
357. Threshold voltage can be varied
by Answer: a
a) varying impurity concentration Explanation: In GaAs technology, due
b) varying doping level to the absence of a stable native
c) varying channel length oxide deposited dielectric films brings
d) varying source voltage about passivation or encapsulation.

Answer: b 360. Formation of n-active layer is

Explanation: Threshold voltage in achieved by
GaAs can be varied by varying the a) indirent ion implantation
channel thickness and the doping b) direct ion implantation
level of the active region. c) liquifying
d) wafering

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: b 363. Stress at the interface cannot

Explanation: Formation of n-active arise from
layer is achieved by direct ion a) lattice mismatch
implantation into the GaAs semi- b) intrinsic stress
insulating substrate through the c) thermal mismatch
insulating layer. d) pressure mismatch

361. Implantation of ________ is Answer: d

done for the formation of source and Explanation: Mechanical stability of
drain. thin film encapsulation layer depends
a) n- layer upon stress at the interface and this
b) n+ layer can originate from lattice mismatch,
c) p- layer intrinsic stress and thermal
d) p+ layer mismatch.

Answer: b 364. Which has the greatest

Explanation: Implantation of a deep mismatch?
low resistivity n+ layer is done for the a) Si
formation of source and drain and n- b) Ga
layer for the formation of channel c) GaAs
layer. d) SiO2

362. The channel resistance is high Answer: d

for Explanation: SiO2 has the greatest
a) source contact mismatch and its cofficient of
b) drain contact thermal expansion is 0.5×10-6/degree
c) gate contact celsius.
d) source and drain contacts
365. Which was employed as the first
Answer: d level capping material?
Explanation: The channel resistance is a) SiO2
in the order of 1000 to 2500 b) SiO
ohm/square which is too high for c) Si3N4
source and drain contacts. d) Si2N4

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: a a) two phase clock

Explanation: Si3N4 has a dielectric b) three phase clock
constant of 7 compared to 3.9 for c) one phase clock
silicondioxide and silicondioxide was d) four phase clock
initially employed as the first-level
Answer: d
capping material.
Explanation: In dynamic CMOS logic,
366. In Pseudo-nMOS logic, n four phase clock is used in which
transistor operates in actual signals are used to derive the
a) cut off region clocks.
b) saturation region
369. In clocked CMOS logic, output in
c) resistive region
evaluated in
d) non saturation region
a) on period
Answer: b b) off period
Explanation: In Pseudo-nMOS logic, n c) both periods
transistor operates in a saturation d) half of on period
region and p transistor operates in
Answer: a
resistive region.
Explanation: In clocked CMOS logic,
367. The power dissipation in the logic is evaluated only in the on
Pseudo-nMOS is reduced to about period of the clock. And owing to the
________ compared to nMOS device. extra transistor in series, slower rise
a) 50% time and fall times are expected.
b) 30%
370. In clocked CMOS logic, rise time
c) 60%
and fall time are
d) 70%
a) faster
Answer: c b) slower
Explanation: The power dissipation in c) faster first and then slows down
Pseudo-nMOS is reduced to about d) slower first and then speeds up
60% compared to nMOS device.
Answer: b
368. In dynamic CMOS logic _____ is Explanation: In clocked CMOS logic,
used. rise time and fall time are slower

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 ELECTRONIC SCIENCE UNIT-2 MCQs

because of more number of Answer: a

transistors in series. Explanation: CMOS domino logic
structure occupies smaller area than
371. In CMOS domino logic _____ is
conventional CMOS logic as only n-
used.
block is used.
a) two phase clock
b) three phase clock 374. Why do CCD or CID cameras are
c) one phase clock used?
d) four phase clock a) To generate the electronic signal
representing the image
Answer: c
b) To generate image’s hard copy
Explanation: In CMOS domino logic,
c) To determine lighting of the image
single phase clock is used. Clock
d) To capture heat signature
signals distributed on one wire is
called as single or one phase clock. Answer: a
Explanation: CCD or CID cameras are
372. CMOS domino logic is same as
used to generate the electronic signal
______ with inverter at the output
that represents the image. The
line.
camera collects light from the image
a) clocked CMOS logic
scene via lens and uses a
b) dynamic CMOS logic
photosensitive target to converts it
c) gate logic
into electronic signal.
d) switch logic
375. Where is the Vidicon Camera
Answer: b
used?
Explanation: CMOS domino logic is
a) Open-circuit television systems
same as that of the dynamic CMOS
b) In Image processing
logic with inverter at the output line.
c) In image analysis
373. CMOS domino logic occupies d) Closed-circuit television systems
a) smaller area
Answer: d
b) larger area
Explanation: Vidicon Camera used in
c) smaller & larger area
closed-circuit television systems can
d) none of the mentioned
be used for machine vision systems.

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 ELECTRONIC SCIENCE UNIT-2 MCQs

An image is formed in camera by Answer: d

focussing the incoming light through Explanation: A typical matrix array
a series of lenses onto the solid state cameras have 256 x 256
photoconductive faceplate of the detector elements per array. Solid
vidicon tube. state cameras are small and rugged.
Sensors of solid state cameras are do
376. What is used in solid state
not wear out with use. There is very
cameras?
less image distortion in solid state
a) Image sensor IC
cameras because of placement of
b) CMOS image sensors
photo detectors accurately.
c) Charge coupled device (CCD) image
sensors 378. What is the common rate of an
d) Digital camera image sensor image forming in a camera?
a) 20 images per second
Answer: c
b) 30 images per second
Explanation: Solid state cameras are
c) 25 images per second
generally used in machine vision
d) 50 images per second
systems. These uses charge injected
device (CID) or charge coupled device Answer: b
(CCD) image sensors. They contain Explanation: A camera may typically
linear or matrix array of small, form an image 30 times per sec i.e. at
accurately spaced photo-sensitive 33 m sec intervals. At each time
elements fabricated on silicon chips interval the entire image has to be
using integrated circuit technology. captured and frozen for processing by
an image processor. An analog to
377. How many detector elements
digital converter is used to convert
are present in a matrix array solid
analog voltage of each detector into
state camera?
digital value.
a) 156 x 156 per array
b) 216 x 216 per array 379. The example of dynamic
c) 116 x 116 per array memory is __________
d) 256 x 256 per array a) CCD
b) Semiconductor dynamic RAM
c) Both CCD and semiconductor

79
 ELECTRONIC SCIENCE UNIT-2 MCQs

dynamic RAM plates for optical telescopes because

d) Floppy-Disk CCDs:
(A) can measure brightnesses more
Answer: c
precisely.
Explanation: The examples of
(B) are cheap and disposable.
dynamic memories are CCD and
(C) do not produce diffraction fringes.
semiconductor dynamic RAM
(D) are not susceptible to chromatic
because of the contents of both the
aberration.
memories changes with time.

380. In dynamic memory, CCD stands Answer: (A)

for __________
a) Charged Count Devices Response (C) is a limitation on the
b) Change Coupled Devices resolving power of a telescope, which
c) Charge Coupled Devices ultimately depends on the diameter
d) Charged Compact Disk of its primary mirror (or lens), and
not on the media used to record
Answer: b
images. Response (D) is a property of
Explanation: In dynamic memory,
optical telescope lenses (but not of
CCD stands for Charge Coupled
optical telescope mirrors).
Devices.
383. Mylar coated with a sheet of red
381The famous that invented the
photographic Mylar is used for
charge-coupled device are
artwork (layout) because,
a) Fritz Haber and Willard Boyle a) It is used to get a colourful layout
b) Ernest Rutherford and Willard b) It can be easily peeled off from
Boyle layout
c) George E. Smith and Willard c) It is recommended colour for
Boyle layouts
d) Francis Crick and Willard Boyle d) It is used for highlighting layout

Answer: c Answer: b
Explanation: For photographic
382. Charge-coupled devices (CCDs)
purpose, artwork should not contain
are more useful than photographic

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 ELECTRONIC SCIENCE UNIT-2 MCQs

any line drawing but must be of advantage of dry etching process is

alternate clear and opaque region. that, it is possible to achieve smaller
The red layer can be easily peeled off line openings (<1µm) compared to
thus exposing clear areas with a knife other process.
edge from regions where impurities
386. Which of the following
have to be diffused.
statement is not true?
384. Find the coating material used a) X-ray and Electron beam
for photo etching process along with lithography technique, produce
its thickness range. device dimensions down to
a) Kodak photoresist (5000-10000Å) submicron range.
b) Kodak photoresist (1000-5000Å) b) Ultraviolet lithography has
c) Kodak photo etchant (1000-5000 limitation due to diffraction effects of
Å) wavelength.
d) Kodak photo etchant (500-1000 Å) c) The cost of X-ray or Electron beam
is less compared to Ultraviolet
Answer: a
photolithography.
Explanation: The coating material is
d) The exposure time is less in
Kodak photoresist. It is a
Ultraviolet compared to X-ray or
photosensitive emulsion film coated
Electron beam lithography.
on wafer to remove SiO2 from desired
region. Answer: c
Explanation: The cost of X-ray or
385. Which type of etching process is
Electron beam is very high and thus,
preferred to make the photoresist
it is an expensive process. Therefore,
immune to etchants?
it is used only when very small device
a) None of the mentioned
dimension (<1 µm) are needed.
b) Wet etching
c) Plasma etching 387. For photographic purpose
d) Chemical etching usually coordinatograph is preferred
for artwork because,
Answer: c
a) It is a precision drafting machine
Explanation: Plasma etching is also
b) Cutting head can be positioned
called as dry etching. The major
accurately

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 ELECTRONIC SCIENCE UNIT-2 MCQs

c) It can be moved along two Answer: b

perpendicular axes Explanation: In diffusion process, the
d) All of the mentioned depth of diffusion of impurities
depends upon the time taken for
Answer: d
diffusion, which normally extends for
Explanation: The coordinatograph is a
more than 2 hours.
drafting machine that outlines the
pattern cutting through the red Mylar 390. Which component is not used as
without damaging the clear layer an impurity in diffusion process?
underneath. a) Phosphorous
b) Boron chloride
388. Which of the following is added
c) Phosphorous pentaoxide
as an impurity to p-type material in
d) Boron oxide
diffusion process?
a) Phosphorous pentaoxide (P2O5) Answer: a
b) Phosphorous oxychloride (POcl3) Explanation: Elemental form of
c) Boron oxide (B2O3) Phosphorous is not added directly as
d) None of the mentioned an impurity in diffusion process.

Answer: c 391. In ion implantation method,

Explanation: Boron is a p-type penetrating the ions into the silicon
material, whereas Phosphorous is an wafer depends upon
n-type material. a) Accelerating voltage
b) Accelerating speed
389. In the fabrication of monolithic
c) Accelerating current
ICs, Boron chloride is added as an
d) All of the mentioned
impurity in the diffusion process. Find
the diffusion time, if the furnace is Answer: a
heated up to 1200oc. Explanation:The depth of penetration
a) 1 hour of any particular type of ion increases
b) 2 hours with increasing accelerating voltage.
c) 45 minutes
392. What is the advantage of using
d) 30 minutes
Ion implantation process?
a) Lateral spreading is more

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 ELECTRONIC SCIENCE UNIT-2 MCQs

b) Performed at high temperature b) PN-junction isolation

c) Beam current controlled from c) Barrier isolation
outside d) Dielectric isolation
d) Performed at low temperature
Answer: d
Answer: c Explanation: In dielectric isolation a
Explanation: In diffusion process, layer of solid dielectric is used for
temperature has to be controlled isolation purpose. This layer is thick
over a large area inside the oven, enough such that its associated
whereas in ion implantation capacitance is negligible. Moreover, it
technique, accelerating potential and is more expensive, which is justified
the beam current are electrically by its superior performance.
controlled from outside.
395. Pick out the incorrect statement
393. The major disadvantage of PN- Aluminium is usually used for
junction isolation technique is: metallization of most IC as it offers
a) Formation of Parasitic Resistance a) Relatively a good conductor
b) Formation of Parasitic Capacitance b) High resistance
c) Formation of Isolation island c) Good mechanical bond with silicon
d) None of the mentioned d) Deposition of aluminium film using
vacuum deposition
Answer: b
Explanation: The presence of Answer: c
Parasitic Capacitance at the isolating Explanation: Aluminium forms low
PN-junction, results in an inevitable resistance (it is a good conductor of
capacitor coupling between the electricity). Therefore, it forms ohmic
component and substrate. This also contact (Semiconductor-metal
limits the performance of circuit at contact) with p-type silicon and
high frequencies. heavily doped n-type silicon.

394. Which isolation technique is 396. How the aluminium film coating
used in applications like military and is carried out in metallization
aeroscope? process?
a) Thin film isolation a) Heating and pouring aluminium in

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 ELECTRONIC SCIENCE UNIT-2 MCQs

required place. b) 16 leads

b) Aluminium is vacuum evaporated c) 12 leads
and then condensed d) 24 leads
c) Placing the aluminium in required
Answer: c
place and then heating it using
Explanation: The maximum lead
tungsten
available in a metal can IC package is
d) None of the mentioned
12. The remaining lead numbers are
Answer: b commonly available in dual-in-line
Explanation: Metallization process packages.
takes place in Vacuum evaporation
399. What process is used in
chamber, where the material is
semiconductor industry to fabricate
evaporated by focussing a high power
Integrated Circuits?
density electron beam. Vapours then
a) Silicon wafer preparation
hit the substrate and get condensed
b) Silicon planar process
to form thin film coating.
c) Epitaxial growth of silicon
397. What type of packing is suitable d) Photolithography process
for Integrated Circuits?
Answer: b
a) Metal can package
Explanation: The planar process
b) Dual-in-line package
(Silicon planar technology) in
c) Ceramic flat package
semiconductor industry built
d) All of the mentioned
individual components. It is the
Answer: d primary process by which Integrated
Explanation: These packages are the Circuits are built. The other processes
three different possible packages are the different steps involved
available in Integrated Circuits. Its within the planar process.
usage depends upon the number of
400. Which semiconductor is most
leads required for application.
widely used for fabrication of
398. Metal can IC packages are Integrated Circuit?
available in a) Germanium, Ge
a) 42 leads b) Gallium Arsenide, GaAs

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 ELECTRONIC SCIENCE UNIT-2 MCQs

c) Silicon, Si c) Strong Electric and Magnetic Field

d) All of the mentioned d) None of the mentioned

Answer: c Answer: b
Explanation: Silicon is abundantly Explanation: During arc discharge in
available in the form of sand. It is ion implantation, the unwanted
possible to form superior stable impurities gets generated. The
SiO2(Which has superb insulating magnetic field acts to separate
property). Whereas GaAs is more unwanted impurities from dopant
difficult to grow in crystal form and ions.
Ge crystal will be destroyed at high
403. In which method shallow
temperature.
penetration of dopants is possible?
401. What will be the next step after a) Ion implantation
slicing (process) silicon wafers? b) Vertical diffusion
a) All of the mentioned c) Horizontal diffusion
b) Lapping d) Dopants diffusion
c) Polishing
Answer: a
d) Chemical
Explanation: The depth of diffusion in
Answer: a this method, can be easily regulated
Explanation: When the silicon ingots by control of the incident ion velocity
are sliced for the given industrial and is capable of shallow
dimension. It gives a rough surface penetration.
and thus undergo lapping, polishing
404. Which method is most suitable
and chemical processing steps to get
for silicon crystal growth in silicon
a smooth surface.
wafer preparation?
402. During ion implantation process a) Float zone process
(before the ion strike the wafer) the b) Bridgeman-Stockbarger method
accelerated ions are passed through c) Czochralski crystal growth process
a) Strong Electric field d) Laser heated pedestal growth
b) Strong Magnetic field
Answer: c
Explanation: Czochralski crystal

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 ELECTRONIC SCIENCE UNIT-2 MCQs

growth processes obtain single Answer: d

crystal of semiconductor. The most Explanation: As the collector contact
important application of this method is present on the top of IC transistor,
may be growth of large cylindrical it makes structural difference. Hence,
ingot of single crystal silicon. it increases collector series resistance
and VCE(sat) of device. From this,
405. Which is the most striking
circuit performance is highly
feature in monolithic integrated
improved as matched transistor can
circuit transistor?
be obtained.
a) Collector contact is present at the
bottom of IC 407. Name the process that is used to
b) Collector contact is present at the overcome the increase in collector
top of IC series resistance, which occurs due to
c) Collector contact is absent the presence of collector contact at
d) Collector contact is present on one the top of integrated transistor.
of the sides of IC a) Buried n+ layer
b) Buried p+ layer
Answer: b
c) Triple diffused layer
Explanation: In IC transistor, the
d) Buried epitaxial layer
collector contact has to be taken
from the top because collector is Answer: a
isolated from the substrate and next Explanation: The value of collector
isolation island by reverse biased series resistance of an integrated
diodes. transistor can be easily reduced by a
process known as “buried layer” or
406. Why monolithic IC transistor is
“Buried n+ layer”.
preferred over discrete planar
epitaxial transistor? 408. What is the reason for using
a) Due to structural difference Lateral pnp transistor in Integrated
b) Increase in VCE (sat) and collector Circuits?
series resistor a) Requires simple process control
c) Improvement in circuit b) Simultaneous fabrication of pnp
performance and npn transistors
d) All of the mentioned

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 ELECTRONIC SCIENCE UNIT-2 MCQs

c) Provide good isolation 410. The ‘buried layer’ reduces

d) Miniaturization and cost reduction collector series resistance by
providing,
Answer: b
a) A low resistivity current path from
Explanation: During the p-type base
n-type layer to n+ contact layer
diffusion for npn transistor, two
b) A low resistivity current path from
adjacent p-regions are diffused to
p-type layer to n+ contact layer
form the emitter and collector region
c) A high resistivity current path from
of the lateral pnp transistor (n-type
n-type layer to n+ contact layer
epitaxial layer is used as base of the
d) A high resistivity current path from
pnp transistor).Thus, pnp and npn
p-type layer to n+ contact layer
transistors are fabricated
simultaneously. Answer: a
Explanation: A heavily doped
409. Which of the following transistor
n+ region is sandwiched between the
has the limitation, due to the
n-type epitaxial collector and p-type
requirement of additional fabrication
substrate. This buried n+ region
steps and design consideration?
provide a low resistivity current path
a) Vertical pnp transistor
from active collector region (n-type
b) Lateral pnp transistor
layer) to the collector contact
c) Triple diffused pnp transistor
(n+ contact layer). In effect, the
d) Substrate pnp transistor
n+ layer shunt n-layer of collector
Answer: c region with respect to flow of
Explanation: In triple diffused pnp current, thus effectively reduces the
transistor fabrication process, an collector resistance.
extra p-type diffusion is added to a
411. At what potential, the substrate
standard npn-transistor after the n-
of a vertical pnp transistor should be
diffusion to obtain a pnp transistor.
kept to attain good isolation?
However, the usefulness of such a
a) Same potential
structure is not used due to its
b) Positive potential
limitation.
c) Different potential
d) Negative potential

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: d lateral diffusion of p-type impurities

Explanation: The limitation of vertical and photographic limitations during
pnp transistor is that, collector has to mask marking and alignment.
be held at a fixed negative potential, Therefore, pnp transistor normally
as substrate is to be held at the most gives current gain as low as 1.5 to 30
negative potential in the circuit for compared to 50-300 for the npn
providing good isolation. transistor.

412. Which method is used in the 414. The diffusion of collector

fabrication of pnp transistor? impurities in npn transistor should be
a) Vertical substrate pnp small because,
b) Triple diffused pnp a) No additional diffusion or masking
c) Lateral pnp steps required
d) All of the mentioned b) Bandwidth is controlled by lateral
diffusion of p-type impurity
Answer: d
c) Collector need not be kept at
Explanation: pnp transistors in
negative potential
Integrated Circuits are fabricated in
d) None of the mentioned
one of the following three ways.
Answer: d
413. State the correct reason for
Explanation: Generally, n-type
neglecting pnp transistor.
impurities have smaller diffusion
a) Increase in the series collector
constant than p-type impurities, the
resistance of pnp transistor
n-type collector moves very little
b) Parasitic capacitance appears
while p-type moves appreciably.
between collector and substrate
Therefore, the diffusion coefficient of
c) Current gain of pnp transistor is as
the collector impurities should be as
low as 1.5 to 30
small as possible to avoid the
d) None of the mentioned
movement of the collector junction.
Answer: c
415. The advantage of Multi-emitter
Explanation: Lateral pnp transistor
transistor is
has inferior characteristic as the base
a) To reduce fabrication steps
width is usually larger controlled by
b) To save chip area

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 ELECTRONIC SCIENCE UNIT-2 MCQs

c) To lower design consideration given values of storage time (n) in sec

d) To provide linear output and forward voltage (V γ).
a) n = 56 , V γ = 0.96
Answer: b
b) n = 100 , V γ = 0.92
Explanation: In Mutli-emitter
c) n = 9 , V γ = 0.85
transistor n+ emitter is diffused at
d) n = 53 , V γ = 0.95
three places in the p-type base. Thus,
it is possible to save chip area and Answer: c
enhance component density of an IC. Explanation: The diode with lowest
storage time and lowest forward
416. Which transistor is best suitable
voltage drop is useful for getting high
to achieve very fast switching in
speed diode to be used in digital
digital circuits?
integrated circuit.
a) Lateral pnp transistor
b) Schottky transistor 418. What is the best choice of IC
c) Multi-emitter transistor package used for experimental
d) NPN transistor purpose?
a) DIP package
Answer: b
b) Metal can package
Explanation: Fast switching can be
c) Flat pack
achieved, if the transistor is
d) Transistor pack
prevented from entering into
saturation. In schottky transistor, Answer: a
schottky diode is used to clamp Explanation: DIP package are used as
between base and collector. it is easy to mount. The mounting
Whenever the base current increases does not require bending or soldering
to saturation, the diode conducts. of the leads.
Thus, the base to collector voltage
419. What is the general information
drops to 0.4v (less than VBE(cut-
specified in ordering an IC?
in)=0.5) and the transistor does not
a) Temperature range
enter into saturation .
b) Device type
417. Choose the appropriate value of c) Package type
diode to get a speedy diode from the d) All of the mentioned

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: d typical Motorola IC is,

Explanation: Generally, in ordering an MCxxxx –> Device type
IC, all the three informations must be P –> Package type(Plastic DIP)
specified. 0o to 70oc –> Temperature range
(Commercial).
420. Find the ordering information
for µA741TC. 422. What does the 1-2-3 numbering
a) Sprague 741 DIP with Industrial system used in National
temperature range Semiconductor IC denotes
b) Intersil 741 DIP with commercial a) Validity in years
temperature range b) Temperature range
c) Fairchilds 741 DIP with commercial c) Package type
temperature range d) Ordering information
d) Texas instrument 741 metal can
Answer: c
with Industrial temperature range
Explanation: In National linear ICs, a
Answer: c 1-2-3 numbering system is used to
Explanation: Here “µA” represents represent the temperature range.
the identifying initials used by
423. How does a industrial
Fairchild,
temperature range device in National
T represents Mini DIP package and C
Semiconductor IC is represented?
represents Commercial temperature
a) LM305
range.
b) LM101
421. How a Motorola IC with plastic c) LM201
DIP and commercial temperature d) All of the mentioned
range is ordered?
Answer: c
a) ICLxxxP -> 0o to 75oc
Explanation: In LM201, the number 2
b) CAxxE -> -55o to +125oc
denotes an industrial temperature
c) LMxxxxA -> -40o to+85oc
range device.
d) MCxxxP -> 0o to 70oc
424. Use device identification
Answer: d
method to find the IC of Fairchild chip
Explantion: The ordering format for a

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 ELECTRONIC SCIENCE UNIT-2 MCQs

manufactured in the year 1980. hardware and is inexpensive when

moulded on plastic.

426. What is the use of notch and dot

in DIP ICs?
a) Determine the pin configuration
b) Designed to represent device type
c) Represent property of IC
d) Find the pin number

Answer: d
Explanation: A notch and dot as
Answer: b viewed form top view is used to find
Explanation: In the chip, 80 represent the pin terminal. The terminals are
the manufactured numbered counter clockwise.
year
427. How an eight pin Dual-In-Line
Package is shortly named
a) 8p DIP
b) Maxi DIP
c) Mini DIP
d) ES DIP

Answer: c
425. Dual-In-Line pack is considered Explanation: An eight pin Dual-In-Line
to be suitable for mounting because, Package is called as Mini DIP as it is
a) Easy to handle used for devices with minimum
b) Fits mounting hardware number of inputs and outputs.
c) Inexpensive
428. Which package type is chosen
d) All of the mentioned
for military purposes?
Answer: c a) Ceramic DIP
Explanation: DIP pack is easy to b) Plat pack
handle, fit standard mounting c) Metal can pack
d) Plastic DIP

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: a c) Flat pack

Explanation: Ceramic DIP can be used d) Transistor pack
for high temperature and high
Answer: c
performance equipment.
Explanation: The flat pack is more
429. A Dual-In-Line Package is usually reliable and lighter than a
referred to as comparable DIP package and
a) DIPn therefore is suited for airborne
b) nDIP application.
c) DIPn
432. How a choice is made, if all three
d) All of the mentioned
package types are available?
Answer: a a) Based on cost
Explanation: A Dual-In-Line Package is b) Based on fabrication
usually referred to as DIPn. Where, n c) Based on Experimentation usage
represent the number of pin d) All of the mentioned
terminals in the IC.
Answer: d
430. Which type of DIP IC dissipates Explanation: When all three packages
more heat? are available for a specific
a) Ceramic DIP application, the choice can be made
b) Plastic DIP based on the relative cost, ease of
c) Metal DIP fabrication and breadbording the IC.
d) None of the mentioned
433. How many temperature grades
Answer: b are available for IC?
Explanation: Plastic DIP are cheaper a) Two
than metal or ceramic DIP, but are b) Three
not regarded as satisfactory in c) Four
extremes of temperature. d) Five

431. Choose the type of package used Answer: b

for Airborne application? Explanation: All ICs manufactured fall
a) DIP package into one of the three basic
b) Metal can package temperature grades. They are

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 ELECTRONIC SCIENCE UNIT-2 MCQs

military, industrial and commercial c) Commercial grade IC

temperature range. d) None of the mentioned

434. ICs used for industrial Answer: a

application will have temperature Explanation: The military grade
range from devices are always of superior
a) -55o to +85oc quality, with tightly controlled
b) 90o to 155oc parameters and consequently cost
c) 10o to 100oc more.
d) -20o to +85oc
437. In ordering an IC, the device
Answer: d type is represented as
Explanation: The industrial a) Numbers
temperature range is from -20o to b) Symbols
+85oc. c) Alphabets
d) Alphanumeric characters
435. Find the types of temperature
range used for an IC, which can be Answer: d
used only up to 75oc? Explanation: The device type is a
a) Industrial temperature range group of alphanumeric characters.
b) Commercial temperature range For example, 741 IC is represented as
c) Military temperature range µA741, LM741 and MC1741.
d) All of the mentioned
438. How many gates per chip are
Answer: b used in first generation Integrated
Explanation: Commercial grade IC can Circuits?
be used up to 75oc. It has the worst a) 3-30
tolerance among the three types and b) 30-300
is the cheapest available IC. c) 300-3000
d) More than 3000
436. Which grade device is selected
for superior quality performance? Answer: a
a) Military grade IC Explanation: The first generation ICs
b) Industrial grade IC belongs to small scale integration,

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 ELECTRONIC SCIENCE UNIT-2 MCQs

which consists of 3-30 gates per chip a) Small Scale Integration (SSI)
(approximately). b) Medium Scale Integration (MSI)
c) Large Scale Integration (LSI)
439. Find the chip area for a Medium
d) Very Large Scale Integration (VLSI)
Scale Integration IC?
a) 8 mm3 Answer: b
b) 4 mm2 Explanation: Fabrication of ICs like
c) 64 mm3 counter, multiplexers and Adders
d) 16 mm2 requires 30-300 gates per chip.
Therefore, Medium Scale Integration
Answer: d
is best suitable.
Explanation: The approximate length
and breadth of Medium Scale 442. Determine the chip area for
Integration would be 4 mm. Large Scale Integration ICs.
Therefore, its area is given as = length a) 1,00,000 mil2
× breadth = 4mm × 4mm = 16mm2. b) 10,000 mil2
c) 1,60,000 mil2
440. The number of transistors used
d) 16,000 mil2
in Very Large Scale Integration is
a) 107 transistors/chip Answer: c
b) 106 – 107 transistors/chip Explanation: The chip area for a Large
c) 203 – 105 transistors/chip Scale Integration IC is 1 cm2.
d) 102 – 203 transistors/chip => Area of LSI = 10mm × 10mm = 1cm
× 1 cm = 1cm2.
Answer: c
=> 1,60,000mil2 (1cm=400mil).
Explanation: Very Large Scale
Integration (VLSI) ICs are fabricated 443. The concept of Integrated
using more than 3000 gates/chip, circuits was introduced at the
which is equivalent to 20,000 – beginning of 1960 by
1,00,00,00 transistors/chip. a) Texas instrument and Fairchild
Semiconductor
441. What type of integration is
b) Bell telephone laboratories and
chosen to fabricate Integrated
Fair child Semiconductor
Circuits like Counters, multiplexers
c) Fairchild Semiconductor
and Adders?

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 ELECTRONIC SCIENCE UNIT-2 MCQs

d) Texas instrument and Bell used to produce device dimension as

telephone Laboratories small as 2µm or even down to sub
micron range (<1µm).
Answer: a
Explanation: The concept of 446. When does an integrated circuit
Integrated circuits was introduced by exhibit greater degree of freedom
Texas instrument and Fairchild and electrical performance?
Semiconductor, whereas Bell a) In thin and thick film technology
telephone laboratories developed the b) In semiconductor technology
concept of transistors. c) In semiconductor and films
technology
444. Which process is used to
d) In thick film technology only
produce small circuits of micron
range on silicon wafer? Answer: c
a) Photo etching Explanation: Combining films and
b) Coordinatograph semiconductor technology provide a
c) Photolithography better electrical performance than
d) Ion implantation either technology can provide
separately.
Answer: c
Explanation: It is possible to fabricate 447. Give the thickness range of the
as many as 10,000 transistors on a film used in thin film technology
1cmX1cm chip, using a) 0.5-2.5 mils
photolithography process. b) 0.02-8 mils
c) 10-20 mils
445. Mention the technique used in
d) 0.05-0.0 7mils
photolithography process
a) X-ray lithographic technique Answer: b
b) Ultraviolet lithographic technique Explanation: Thin films have thickness
c) Electron beam lithographic varying from 50 Å to 20,000 Å.
technique W.k.t, 1 Å=0.4 µmil,
d) All of the mentioned =>50 Å=50 × 0.4µmil=0.02 mmil,
=>20,000 Å=20, 000*0.4µmil=8 mmil,
Answer: d
Explanation: All these techniques are

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 ELECTRONIC SCIENCE UNIT-2 MCQs

=>therefore, the thickness range slower than evaporation method.

from 0.02-8 mmil. Since depositing a micron-thick film
takes minutes to hours, compared to
448. Which technology is used to get
seconds to minutes for evaporation.
cheap resistors and capacitors?
a) Thick film technology 450. How a uniform film with good
b) Thin film technology crystal structure is attained in
c) Thin and thick film technology cathode sputtering process?
d) None of the mentioned a) By hitting high energy particle
directly on the substrate
Answer: b
b) Allowing Less time for the particles
Explanation: Thick film technology
to deposit on the substrate
produces cheap and rugged
c) High energy particle diffuse
components, whereas thin film
through low pressure gas and
technology provides greater precision
deposits on the substrate
in manufacturing but is quite
d) Heavy inert gas is used for film
expensive. The processing equipment
deposition on the substrate
for thick film circuit is relatively
inexpensive and is easy to use. Answer: c
Explanation: The process of cathode
449. How is the process of film
sputtering is performed at a low
deposition carried out in cathode
pressure (about 10-12 torr). So, when
sputtering?
the high energy particle landing on
a) Slower than evaporation method
the substrate actually results in a very
b) Faster than evaporation method
uniform film and adhesion.
c) Similar to same as evaporation
method 451. Which process is used to deposit
d) All of the mentioned metals on glass, ceramic and plastic?
a) Silk plating technique
Answer: a
b) Gas plating technique
Explanation: Cathode sputtering and
c) Electroless plating technique
vacuum evaporation uses identical
d) Electroplating technique
system. However, the process of film
deposition in cathode sputtering is

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Answer: c c) Silk screening

Explanation: In electroless plating, a d) All of the mentioned
metal ion in solution is reduced to
Answer: c
the free metal and deposited as a
Explanation: Silk screening is one of
metallic coating without the use of a
the processes of thin film technology.
coating without the use of an electric
current. Thus, this process is used in 454. An ancient process used till
plating on glass, ceramic and plastic. today for production of circuit films
is,
452. Electroplating technique is
a) Silk Screening technique
suitable for
b) Surface Mount Technology
a) Making conduction films ceramic
c) Ceramic Printing technique
b) Coating with considerable
d) Screen Printing technique
thickness
c) Coating without use of electric Answer: d
current Explanation: The process of screen
d) Making conduction films of gold or printing pattern is an ancient one.
copper The Egyptian used this technique
thousands of years ago to decrease
Answer: d
potter and wall of building.
Explanation: Electroplating is a
process of coating an object with one 455. What is the advantage of using
or more layers of different metal. Surface Mount Technology?
When dc is passed through the a) All of the mentioned
electrolytic solution, the positive b) Low power consumption
metal ions migrate from anode c) Reduces heat dissipation in
(metal) and deposit on the cathode components
(substrate). d) Use leaded or leadless
components
453. Which of the following process is
involve in thick film technology Answer: d
a) Screen printing Explanation: Surface Mount
b) Ceramic firing Technology utilizes micro-miniature
leaded or leadless components called

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 ELECTRONIC SCIENCE UNIT-2 MCQs

Surface Mount Device (SMD) which d)

are directly soldered to the specified
areas on the surface without hole.
Also, the compact size of SMDs
reduces the area in PCB and increases
the packing density.

456. Find the epitaxial resistor from

the given cross-sectional view Answer: a
diagram? Explanation: The mention figure is
a) the cross sectional view of epitaxial
resistor. The remaining diagrams are
the cross-sectional view of pinched,
thin film and diffused resistor.

457. Which integrated resistor can

achieve high value of sheet
resistance?
b) a) Pinched resistor
b) Epitaxial resistor
c) Thin film resistor
d) All of the mentioned

Answer: a
Explanation: In a pinched resistor, the
sheet resistivity can be increased by
c) reducing its effective area. This
technique is used to achieve high
value of sheet resistance from
ordinary diffused resistor.

458. How pinched resistor can give

resistance in order of mega-ohm in a
reasonably small area?

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 ELECTRONIC SCIENCE UNIT-2 MCQs

a) By increasing fabrication steps adjusted after fabrication

b) By offering bulk resistance in n- c) Resistance in the range 100kΩ
region possible using nichrome resistors
c) By reducing conduction path d) Thin film resistors are more stable
d) By limiting the thickness of are
Answer: c
Answer: c Explanation: Typically, sheet
Explanation: In pinched resistor resistance value of nichrome is 40 –
structure, one of the diode conducts 400Ω/square (depending upon film
in reverse direction and only a small thickness). So, the resistance in the
reverse saturation current can flow range 20 to 50kΩ can only be
through n-type material. By doing so, obtained.
the effective cross-sectional area of
461. Find the equivalent circuit of
the conduction path will be reduced
junction capacitor?
and resistance between two contact
lead increases.

459. Which of the following is not

used as metallic film in the thin film
resistor?
a) Nichrome (NiCr) a)
b) Tantalum (Ta)
c) Stannic oxide (SnO2)
d) Silicon dioxide (SiO2)

Answer: d
Explanation: Silicon dioxide is the
non-metallic layer on which the
metallic thin films are deposited. b)

460. Pick out the incorrect statement

a) Sheet resistance have smaller and
lesser parasitic components
b) Value of resistor can be easily

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 ELECTRONIC SCIENCE UNIT-2 MCQs

junctions in the junction type IC

capacitor.

463. Which is used as the dielectric

layer in MOS Capacitor?
a) Silicon Nitride (Si3N4)
b) Aluminium oxide (Al2O3)
c) c) Tantalum oxide (Ta2O5)
d) All of the mentioned

Answer: d
Explanation: Si3N4 offers higher value
of capacitance. Whereas , Al2O3 and
d) Ta2O5 are preferred for large value of
capacitance. Hence all of them are
Answer: b
used as dielectric layer.
Explanation: The mentioned diagram
is the equivalent circuit diagram of 464. Which is considered to be a
junction capacitor. serious disadvantages of thin film
capacitor, when Al2O3is used as
462. The capacitance of junction
dielectric.
capacitor does not depend upon
a) Additional fabrication step
a) Impurity concentration of p-type
required
epitaxial layer
b) It require over voltage protection
b) Impurity concentration of n-type
c) Higher dielectric constant value is
epitaxial layer
required
c) Area of the junction
d) All of the mentioned
d) Voltage across the junction
Answer: b
Answer: a
Explanation: One of the serious
Explanation: There is no p-type
disadvantages of thin film capacitor is
epitaxial layer present in junction
that it fails, when the voltage rating
capacitor. But a p-type substrate is
exceeds due to breakdown of the
present and it forms one of the
dielectric, which is a destructive and

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 ELECTRONIC SCIENCE UNIT-2 MCQs

irreversible failure mechanism and it low quality factor can only be

require over voltage protection. obtained.

465. In MOS capacitor, the 467. Which circuit is used to replace

preference in dielectric layer is given inductor in IC components?
to Silicon Nitride (Si3N4) because a) RC active network
a) It makes capacitor non-polar b) PN-junction diode
b) It contain a small resistance c) LC active network
c) It offers less processing step d) None of the mentioned
d) It reduces failure mechanism
Answer: a
Answer: a Explanation: Circuit designer go to
Explanation: Si3N4 gives more circuit great lengths to avoid the use of
flexibility by being non-polar, that is , inductors or otherwise simulate them
it does not matter which plate is by using RC active networks.
positive or negative and the voltage
468. In application such as RF and IF
applied.
circuits, inductor cannot be avoided.
466. Why inductor is avoided in How to manage such situation?
Integrated Circuit component? a) Using inductors external to IC
a) They provide many losses package
compared to other IC components b) Thin film inductor spiral are used
b) IC devices are essentially two c) Thin film hybrid microwave can be
dimensions used
c) Device density of IC increases d) All of the mentioned
d) Fabrication process of these
Answer: d
components are complicated
Explanation: In most cases, inductors
Answer: b external to IC packages are used.
Explanation: Usually, IC devices are However, thin film hybrid Microwave
very small (~1 to 10µm). Even if IC IC (MIC) and thin film inductor spiral
inductor is made in form of a flat can provide inductance up to 250nH.
metallic thin film spirals. Very small
469. Electronics are characterized by
value of the order nanohenry with
____________

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 ELECTRONIC SCIENCE UNIT-2 MCQs

a) low cost level

b) low weight and volume b) n-type substrate of low doping
c) reliability level
d) all of the mentioned c) p-type substrate of moderate
doping level
Answer: d
d) n-type substrate of high doping
Explanation: Electronics are
level
characterized by reliability, low
power dissipation, extremely low Answer: c
weight and volume, low cost, can Explanation: nMOS devices are
cope up with high degree of formed in a p-type substrate of
sophistication and complexity. moderate doping level. nMOS devices
have higher mobility and is cheaper.
470. Speed power product is
measured as the product of 472. Source and drain in nMOS
____________ device are isolated by ____________
a) gate switching delay and gate a) a single diode
power dissipation b) two diodes
b) gate switching delay and gate c) three diodes
power absorption d) four diodes
c) gate switching delay and net gate
Answer: b
power
Explanation: The source and drain
d) gate power dissipation and
regions are formed by diffusing n-
absorption
type impurity, it gives rise to
Answer: a depletion region which extend in
Explanation: Speed power product is more lightly doped p-region. Thus
measure in picojoules and it is the Source and drain in an nMOS device
product of gate switching delay and are isolated by two diodes.
gate power dissipation.
473. In depletion mode, source and
471. nMOS devices are formed in drain are connected by
____________ ____________
a) p-type substrate of high doping a) insulating channel

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b) conducting channel the device is in non conducting

c) Vdd condition. For n-type FET, the
d) Vss threshold voltage is positive and p-
type threshold voltage is negative.
Answer: b
Explanation: In depletion mode, 476. What is the condition for non
source and drain are connected by conducting mode?
conducting channel but the channel a) Vds lesser than Vgs
can be closed by applying suitable b) Vgs lesser than Vds
negative voltage to the gate. c) Vgs = Vds = 0
d) Vgs = Vds = Vs = 0
474. What is the condition for non
saturated region? Answer: d
a) Vds = Vgs – Vt Explanation: In enhancement mode
b) Vgs lesser than Vt the device is in non conducting mode,
c) Vds lesser than Vgs – Vt and its condition is Vds = Vgs = Vs = 0.
d) Vds greater than Vgs – Vt
477. nMOS is ____________
Answer: c a) donor doped
Explanation: The condition for non b) acceptor doped
saturated region is Vds lesser Vgs – c) all of the mentioned
Vt. In non saturation region, MOSFET d) none of the mentioned
acts as voltage source. Varying Vds
Answer: b
will provide a significant change in
Explanation: nMOS transistors are
drain current.
acceptor doped. Acceptor is a dopant
475. In enhancement mode, device is which when added forms p-type
in _________ condition. region. Some of the accpetors are
a) conducting silicon, boron, aluminium etc.
b) non conducting
478. MOS transistor structure is
c) partially conducting
____________
d) insulating
a) symmetrical
Answer: b b) non symmetrical
Explanation: In enhancement mode,

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c) semi symmetrical 481. What is the condition for linear

d) pseudo symmetrical region?
a) Vgs lesser than Vt
Answer: a
b) Vgs greater than Vt
Explanation: MOS transistor structure
c) Vds lesser than Vgs
is completely symmetrical with
d) Vds greater than Vgs
respect to source and drain.
Answer: b
479. pMOS is ____________
Explanation: The condition for linear
a) donor doped
region is Vgs > Vt. The power of MOS
b) acceptor doped
in the linear region is less. It is a
c) all of the mentioned
power dissipating region.
d) none of the mentioned
482. As source drain voltage
Answer: a
increases, channel depth
Explanation: nMOS is acceptor doped
____________
and pMOS is donor doped devices.
a) increases
Acceptor doped forms p-type region
b) decreases
and donor doped forms n-type
c) logarithmically increases
region.
d) exponentially increases
480. Inversion layer in enhancement
Answer: b
mode consists of excess of
Explanation: As source drain voltage
____________
Vds increases, the channel depth at
a) positive carriers
the drain end decreases.
b) negative carriers
c) both in equal quantity
d) neutral carriers

Answer: b
Explanation: Inversion layer in
enhancement mode consists of
excess of negative carriers that is
electron.

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