968 IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, VOL. 12, NO.

4, OCTOBER-DECEMBER 2024

Approximate MAC Unit Using

Static Segmentation
Gennaro Di Meo , Gerardo Saggese , Antonio G. M. Strollo , Senior Member, IEEE, and
Davide De Caro , Senior Member, IEEE

Abstract—In this paper we investigate a novel approx- achieved by resorting to approximate computing, a recent design
imate multiply-and-accumulate (MAC) unit, that computes paradigm aimed at improving the hardware performance by
Y = A × B + C using static segmentation. The proposed intentionally introducing approximations into the design [6], [7],
architecture uses a unique carry-propagate adder and per-
forms segmentation on the three operands A, B, and C, [8], [9]. In literature, several efforts have been spent for investi-
to reduce hardware cost. The circuit can be configured gating approximate multipliers. Recursive multipliers, obtained
at design-time by two parameters. The first one controls by assembling approximate 2 × 2 or 4 × 4 sub-multipliers, are
the segmentation on A and B, while the second one con- reported in [10], [11]. Approximate compressors to sum the PPM
trols the segmentation on C and the adder length. An error
are studied in [12], [13], [14], [15] while logarithmic multipliers
compensation technique is also employed, to reduce the
approximation error. Error analysis and implementation re- are investigated in [16], [17]. The Static Segmented Multipliers
sults in 28nm CMOS for 8-bits multiplier with 20-bits and (SSMs), described in [18], [19], show remarkably good power
24-bits addition are presented. The proposed approximate reduction. The SSMs extract a segment of m contiguous bits
MACs outperform the state of the art, showing the largest from each of the two n-bits operands (m < n), use a small m ×
power saving when the mean relative error distance (MRED) m multiplier for the two segments and a left-shift to obtain the
is larger than 2 × 10−3 and 4 × 10−5 for 20 and 24-bits
addition, respectively. For MRED of about 6 × 10−3 the result.
proposed approximate MAC with 20-bits addition exhibits The study of approximate MACs has received less interest in
a power reduction larger than 60% compared to the exact the scientific literature. An approximate MAC can be obtained
MAC and larger than 27% compared to the state-of-the-art simply by cascading a multiplier and an adder, and by appropri-
approximate MACs. Application examples to image filtering ately approximating one (or both) blocks. Better performance
and template matching show that proposed approximate
circuits are good candidates in applications where their can be obtained by using customized approximate MACs, as
error performances are acceptable. the one presented in [20] (using approximate counters), [21]
(based on recursive approach), and [22] (using a cascade of an
Index Terms—Approximate methods, arithmetic and
logic structures, hardware architecture, low-power design,
approximate multiplier and a modified approximate adder with
VLSI. opposite mean error).
In this paper, we propose a novel approximate MAC ex-
ploiting the static segmentation approach for the first time at
I INTRODUCTION the best of the author’s knowledge. The architecture is named
HE multiply-and-accumulate unit (MAC) implements the Static Segmented MAC (SSMAC) in the following. A naive
T equation Y = A × B+C and has a central role in several
applications, including image and audio processing [1], [2],
approach of designing a SSMAC is cascading an adder to a
static segmented multiplier. This approach is however ineffective
convolutional neural networks, and adaptive filtering [3], [4], since the original SSM [18], [19] uses a shifter to obtain the
[5]. This calls for optimized MAC implementations with reduced approximate product. Then, including an adder after the shifter
power and area. A MAC is usually realized by adding the row would result in the cascade of two carry-propagate additions (one
corresponding to the input C to the partial product matrix (PPM) to calculate the approximate product A × B, and one to sum C).
of the product A × B, to employ a unique carry-propagate In our approach, we properly shift the input C to realize the
adder for the computation of Y. For error-resilient applications, MAC operation by using a unique carry-propagate adder. Then,
further improvements in terms of power, area, and delay can be starting from this topology, we design a novel approximate MAC
in which the segmentation is applied not only on A and B, but also
on the operand C, to further reduce hardware cost. The proposed
Manuscript received 14 October 2022; revised 19 July 2023; accepted circuit can be configured at design-time by two parameters. The
11 September 2023. Date of publication 20 September 2023; date of first one controls the segmentation on A and B, while the second
current version 6 December 2024. (Corresponding author: Gennaro Di one controls the segmentation on C and the adder length. Like
Meo.)
The authors are with the Department of Electrical Engineering and [19], the SSMAC includes a compensation term to reduce the
Information Technology, University of Napoli Federico II, 80125 Napoli, approximation error. Analysis of error metrics, synthesis results
Italy (e-mail: [Link]@[Link]; [Link]@[Link]; in 28 nm CMOS technology, and application examples to image
astrollo@[Link]; dadecaro@[Link]).
Digital Object Identifier 10.1109/TETC.2023.3315301 filtering and template matching validate our proposal.

© 2023 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see
[Link]
DI MEO et al.: APPROXIMATE MAC UNIT USING STATIC SEGMENTATION 969

The implementation of the above equation is shown in

Fig. 2(a). The left-shift needed to calculate PSSM does not
allow to merge the final adder with the inner m × m multiplier
Assm × Bssm . Therefore, two cascaded carry-propagate adders
are required: a first 2m-bits adder is used to compute Assm ×
Fig. 1. Segmentation for the input A. Bssm , while a second nC -bits adder sums the operand C.

III. PROPOSED STATIC SEGMENTED MAC

The paper is organized as follows. Section II briefly recalls
the architecture of the static segmented multiplier. Section III The presence of the two adders in cascade negatively affects
describes the proposed SSMAC, with segmentation extended to the performance of the circuit in Fig. 2(a).
the addend C. The results in terms of error metrics and hardware To solve this problem, we rewrite (5) as follows:
performance are reported in Section IV, while some applications YSSM AC = (Assm × Bssm + C · 2−KS ) · 2KS (6)
for image filtering are reported in Section V.
According to (6), we right-shift the input C, before left shifting
II. STATIC SEGMENT MULTIPLIER the product Assm × Bssm . This allows to eliminate the multi-
plexer between the multiplier and the adder, and to merge the
The SSM described in [18], [19] employs an m × m multiplier term C · 2−KS in the PPM of the multiplier.
for realizing an n × n product, with n/2 ≤ m < n. Let us consider The Fig. 2(b) shows the architecture that implements (6),
the operand A. The signal is segmented in a lower portion (LA ), highlighting in red the differences with respect to the MAC of
comprising its m least significant bits (LSBs), and an upper Fig. 2(a). The two OR-gates compute the flags αA and αB ,
portion (HA ), comprising its m most significant bits (MSBs), that in turn program two 2-1 multiplexers used to segment
that is: A and B. A third multiplexer, marked in red in the figure,
LA = A[m − 1 : 0] applies the right-shift on C, choosing between the portions
C[nC -1:0], C[nC -1:n-m], and C[nC -1:2·(n-m)]. The multiplexer
HA = A[n − 1 : n − m] (1) on the output rearranges the result including the bits C[n-m-1:0]
The Fig. 1 shows an example for n = 8, m = 5. When the and C[2·(n-m)-1:0] at the least significant positions in case of
(n−m) MSBs of A are low, LA is selected for the multiplication. right-shift. Thus, the architecture in Fig. 2(b) allows to merge the
Otherwise, HA is chosen at the cost of an accuracy loss (since the inner multiplication and the final sum in a fused MAC structure,
least significant part εA is discarded, see Fig. 1). Let us define again highlighted in red, requiring a unique nC -bits adder. There
αA as the OR of the (n-m) MSBs of A and let us name Assm the is a small overhead due to the introduction of the multiplexer on
segmented input (Assm = LA if αA = 0 and Assm = HA if αA = C input, but this overhead is more than compensated by the
1). The following relation holds: elimination of the 2m-bits adder required in Fig. 2(a).

0 if αA = 0 A. Segmentation of the Addend C
A  Assm · 2KA where : KA = (2)
n − m if αA = 1
As observed before, the architecture in Fig. 2(b), while more
where an approximation error occurs when αA = 1, due to effective compared to Fig. 2(a), requires an nC -bit adder to com-
discarding εA . pute the output. We can reduce the adder length by segmenting
A similar segmentation is applied to B and the output of the also the input C.
multiplier is approximated as follows: By following an approach like Fig. 1, we subdivide the input
PSSM = A × B  (Assm 2KA ) × (Bssm 2KB ) C in a lower portion (LC ) and an upper portion (HC ) which
comprises mC bits, with nC /2 ≤ mC < nC :
= Assm × Bssm · 2KS (3)
LC = C[mC − 1 : 0]
where:
⎧ HC = C[nC − 1 : nC − mC ] (7)
⎨ 0 if (αA , αB ) = 00
KS = n−m if (αA , αB ) = 01, 10 (4) Thus, the proposed static-segmented MAC (SSMAC) can be
⎩ configured at design time with two parameters: m that controls
2 · (n − m) if (αA , αB ) = 11
the segmentation of A and B, and mC that controls the segmen-
The (3) clearly shows that the SSM requires only a small m × tation of C. In the following we will assume mC ≥ 2m.
m multiplier to compute the inner product Assm × Bssm . The Let us name αC the OR of the (nC -mC ) MSBs of C and let us
SSM implementation is reported in the dashed box of Fig. 2(a). define Cssm the segmented C input (Cssm = LC if αC = 0 and
To obtain a multiplier-accumulator we can simply add the Cssm = HC if αC = 1). Like (2), we have:
operand C to the output of the SSM, as follows: 
  0 if αC = 0
YSSM AC = Assm × Bssm · 2KS + C C  Cssm · 2KC where : KC =
(5) nC − mC if αC = 1
(8)
Note that the word length of C is nC ≥ 2n since in most
From (6), the output of the SSMAC is written as:
applications the multiply-accumulate unit is used sequentially  
to accumulate the output of several multiplications. YSSM AC = Assm × Bssm + Cssm · 2KC −KS · 2KS (9)
970 IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, VOL. 12, NO. 4, OCTOBER-DECEMBER 2024

Fig. 2. MAC realized (a) by cascading a static segmented multiplier (in the dashed line) and an adder, and (b) by implementing the proposed
static segmented multiplier-accumulator, according to (6). In the MAC of (a), two cascaded carry-propagate adders are required: The first one in
the inner multiplier that computes Assm × Bssm , and the second one that adds the operand C. In the MAC of (b), the inner multiplication and the
addition are merged, requiring a unique carry propagate adder. The multiplexer on C input introduces only a small overhead.

The word length of the product Assm × Bssm is 2m bits, and Thus, the approximation (13) can be implemented by trun-
the word length of Cssm is mC . Unfortunately, due to the term cating the (KC -KS )/2 rightmost bits of Assm and Bssm . In other
2KC −KS (that can imply a left or a right shift of Cssm ), we cannot words, Assm is simply a sub-segment of HA or LA , and a similar

use a simple mC -bits adder to compute the output in (9). We thus observation holds for Bssm .
consider the various cases that can occur in (9), depending on In the case in which KC -KS is odd, we can still use (13), but
the values of αC , αB , αA . Assm and Bssm
will have a number of bits that differ by one,
When (αC , αB , αA ) = 000, we have KS = KC = 0 and: and are given by the following equation:
YSSM AC = Assm × Bssm + Cssm (10) A ssm = Assm · 2−(KC −KS )/2
where Assm = LA , Bssm = LB and Cssm = LC .
The last equation requires a mC -bits adder, as desired. B  ssm = Bssm · 2−(KC −KS )/2 (15)
In the other cases, we perform some additional approxima-
where · is the ceil operator.
tions by truncating some of the terms in (9); these approxima-
The Fig. 3 shows an example for n = 8, m = 5 and nC = 20,
tions are different depending on the sign of KC −KS .
mC = 14. In Fig. 3(a) the entire (exact) PPM of the multiplier-
To fix ideas, let us assume: (nC -mC ) ≥ 2(n−m), so that KC -KS
accumulator is shown. The Fig. 3(b) highlights the portion of
is negative only when KC = 0 and KS ࣔ 0.
PPM considered for (αC , αB , αA ) = 111. In this case Assm and
Let us consider the case in which KC -KS is positive, that is 
Bssm include the five most-significant bits of A and B, therefore
KC ࣔ 0. We are in this case when αC = 1, independently on the
the bits a2 ..a0 , b2 ..b0 are truncated. The segment Cssm , including
values of αA and αB . We rewrite (9) as follows:
 the 14 most-significant bits of C, is employed and hence the bits
YSSM AC = Assm × Bssm 2−(KC −KS ) + Cssm · 2KC c5 ..c0 are also truncated.
(11) The Fig. 3(c) shows the portion of PPM considered for (αC ,
We approximate this equation by truncating the term Assm × αB , αA ) = 101. In this case Assm includes the three most-

Bssm 2−(KC −KS ) : significant bits of A, while Bssm includes the bits b4 b3 b2 b1 (the
 bit b0 is truncated, while b7 b6 b5 are zero since αB = 0).
YSSM AC  Assm × Bssm 2−(KC −KS ) + Cssm · 2KC Let us now consider the case in which KC -KS is negative, that
(12) is KC = 0 and KS ࣔ 0. We are in this case when αC = 0, and
having indicated as · the floor operator. Let us assume, for the one of αA and αB , or both, are equal to 1. In these conditions,
sake of simplicity, that KC -KS is even. The (12) can be rewritten the (9) becomes:
as follows: YSSM AC = (Assm × Bssm + Cssm · 2−KS ) · 2KS (16)
 
YSSM AC  (A ssm × B ssm + Cssm ) · 2 KC
(13) This equation can be approximated by truncating Cssm ·
where: 2−KS as follows:

A ssm = Assm · 2−(KC −KS )/2 YSSM AC  (Assm × Bssm + C  ssm ) · 2KS (17)
where:
B  ssm = Bssm · 2−(KC −KS )/2 (14)
C  ssm = Cssm · 2−KS (18)
DI MEO et al.: APPROXIMATE MAC UNIT USING STATIC SEGMENTATION 971

Fig. 3. Multiplier accumulator example, with n = 8, m = 5, nC = 20, mC = 14. (a) Partial product matrix of the entire (exact) multiplier accumulator.
(b) Portion of the partial product matrix considered for (αC , αB , αA ) = 111. Bits a2 ..a0 , b2 ..b0 , c5 ..c0 are truncated. (c) Portion of the partial product
matrix considered for (αC , αB , αA ) = 101. Bits a4 ..a0 , b0 , c5 ..c0 are truncated. Bits b7 b6 b5 are zero. (d) Portion of the partial product matrix
considered for (αC , αB , αA ) = 011. Bits a2 ..a0 , b2 ..b0 , c5 ..c0 are truncated. Bits c19 …c14 are zero.

TABLE I
SEGMENTATION SCHEME FOR THE INPUTS

The (17) requires an mC bit adder to compute the output. c5 c4 c3 c2 c1 c0 are truncated, while c19 c18 …c14 are zero since

Please note that Cssm is simply a segment of C, obtained by αC = 0).
truncating LC . The Table I summarizes the segmentation used to obtain
Fig. 3(d) shows an example for (αC , αB , αA ) = 011. Assm , Bssm 
and Cssm considering all possible values of αC ,
In this case C’ssm includes the bits c13 c12 …c6 (the bits αB , and αA . The last column reports the final shift to be applied
972 IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, VOL. 12, NO. 4, OCTOBER-DECEMBER 2024

As an example, the Fig. 5(a) shows the PPM for the case m = 5
and mC = 12. In the case (αC , αB , αA ) = 011 the dropped terms
with the largest weight 29 are a7 b2 and a2 b7 . We mitigate the
error by performing the OR of these two terms and by including
this value in the column of weight 210 . A similar approach is
used for the dropped terms with weight 28 a6 b2 and a2 b6 . The
condition in Fig. 5(b) refers to the case (αC , αB , αA ) = 111.
Here, the terms considered for the error correction are: a7 b3 OR
a3 b7 (included in column of weight 211 ) and: a6 b3 OR a3 b6
(included in column of weight 210 ).
In general, for (αC , αB , αA ) = 011 the error compensation
term is given by:
Fig. 4. Implementation of static segmented multiplier-accumulator,
with segmentation applied also to operand C. The architecture requires 
1

a small mC -bits adder. D ≈ 22n−2m dk 2 k (21)

k=0

on the result. As it can be observed, there are six possible with:

segmentations to be considered for the operand A: the segments dk = (ak+n−m bn−m−1 OR bk+n−m an−m−1 ) (22)
are LA , HA (see (1)) and also LA , LA , HA , HA
 
, and HA . Similar
considerations hold for B. The possible segmentations for the Only two terms are considered in (21), as we have found
operand C are four. In addition to HC and LC (7), the other that this is a good trade-off between hardware complexity and
segments are named LC and LC in Table I. approximation error. When (αC , αB , αA ) = 111, the expression
The Fig. 4 shows the hardware implementation of the pro- for the error compensation term is similar to (21)-(22), but in this
posed SSMAC. Different from the MAC of Fig. 2(b), two 6-1 case come into play the terms Assm and Bssm
that are truncated
multiplexers are used to select the relevant segments Assm and versions of HA and HB , as detailed in previous subsection. As

Bssm for the inputs A and B, according to the values of αC , shown in Table I, Assm and Bssm
include the most significant
αB , and αA . Similarly, the 4-1 multiplexer on the right selects bits of A and B, ranging from index n−1 to index n−m  or to
the segment Cssm
for the input C. A small inner multiplier- index n− m , with:
accumulator computes the intermediate results named YMAC . (nC − mC ) − 2(n − m)
As shown in Table I, there are four possible shifts to obtain the m = m − (23)
2
result. The multiplexer on the bottom in Fig. 4 is responsible
for performing this shift to compute YSSMAC . The high bit in Thus, the error compensation term can be expressed with
the quantities y2 , y3 , y4 of Fig. 4 and the dashed box that adds equations very similar to (21), (22) where m is substituted by
the correction term D allow to limit the error of the proposed m  or m :
SSMAC, as detailed in the next subsection. 
1

D ≈ 22n−2m d k 2 k (24)
B. Error Compensation k=0

The error sources in the proposed SSMAC are due to the d k = (ak+n−m bn−m −1 OR bk+n−m  an−m −1 ) (25)
truncation of the operands A, B, C. Let us indicate as εA , εB and
εC the errors due to operands truncation: For further correction, we also compensate for the error due
to the segmentation of C, by performing a rounding (rather than
A = A ssm + εA a truncation) of this operand. To this end, we set a high bit to the
right of the segment C’ssm (see the ‘1’ bit, highlighted in green,
B = B  ssm + εB
in position 25 and 27 in Fig. 5(a) and (b), respectively).
C = C  ssm + εC (19) From a hardware point of view the implementation of the error
correction term is straightforward, since the correction term D
The total approximation error of the SSMAC can be written
comprises just two terms, each one given by the OR of two partial
as:
products. Similarly, also the correction of C has a negligible
ε = A × B + C − (A ssm × B  ssm + C  ssm ) impact on the hardware. As shown in Fig. 4, the correction of C
is implemented by setting to ‘1’ a bit of the terms y2 , y3 and y4
= εA B  ssm + εB A ssm + εC + εA εB (20)
before the final shift.
The largest error component is due to the first two terms in
(20), since the error in each of the operand is multiplied by the IV RESULTS
other operand. Thus, the error is mainly due to the segmentation
A. Error Metrics
of the operands A and B of the multiplier, while the error
due to the segmentation of C is lower. As a consequence, the Let us indicate as YEXACT and YAPP the outputs pro-
approximation error ε can widely be mitigated by using the same duced by exact and approximate MAC, respectively, and as
approach discussed in [19] for the static segmented multiplier. YM AX = (2nC − 1) + (2n − 1)2 the maximum possible value
DI MEO et al.: APPROXIMATE MAC UNIT USING STATIC SEGMENTATION 973

Fig. 5. Error correction for the SSMAC. (a) Correction terms for (αC , αB , αA ) = 011. (b) Correction terms for (αC , αB , αA ) = 111.

of YEXACT . The error E, the error distance ED and the relative the use of the architecture in Fig. 2(b), where segmentation on
error distance RED are defined as follows: operand C is not performed. As it can be observed in Fig. 6,
the segmentation of C reveals effective. For m = 4, using
D = YEXACT − YAP P
mC = 12 (and hence a 12-bits adder) allows to obtain almost
ED = |YEXACT − YAP P | the same precision as the architecture with mC = 20 (using a
20-bits adder). For m = 5, the SSMAC with mC = 14 gives
ED
RED = (for : YEXACT = 0) (26) a precision very close to the one with mC = 20. The plots in
|YEXACT | Fig. 6 also show that the correction technique is efficacious,
The metrics used to assess the error characteristics of the reducing by more than 50% NMED and MRED in all investigated
investigated circuits are: the Normalized Mean error NM, the cases.
Normalized Mean Error Distance NMED, the Mean Relative The Table II reports results obtained for the proposed SSMAC
Error Distance MRED, and the Normalized maximum Error (the SSMACs marked with ‘∗ ’ implement the correction tech-
Distance NmaxED, defined as follows: nique) and for several state-of-the-art MACs from literature in
the case n = 8, nC = 20. Similarly, Table III shows results for
N M = μE /YM AX
n = 8, nC = 24 bits as further test case.
N M ED = μED /YM AX The techniques [10], [12], [14] implement different types of
approximate multipliers. The design in [10] uses a recursive
M RED = μRED
architecture base on an approximate 4 × 4 multiplier. In [12],
N maxED = max(ED)/YM AX (27) L represents the number of rows grouped for the compression
with the OR-gates. The reference [14] uses approximate 4-2
where μE , μED , μRED are the mean values of E, ED, RED,
compressors that populate the n less significant columns in the
respectively. We also considered the parameter PRED, defined
PPM. The CN version uses only the compressors developed in
as the probability of having RED larger than 2%.
[14], while the CNHYB version uses both the compressors of [14]
and the ones proposed in [15]. The architectures in [20], [21],
B. Error Performance [22] are specifically designed for multiplier-accumulators. The
Error performance of investigated MACs have been obtained work [20] employs a mask able to define the accuracy of the PPM
by simulating 10 million uniformly distributed values of A, B compression. We considered the two cases mask = 0 and mask =
and C. 127, corresponding to maximum hardware simplification and
The Fig. 6 shows results for the proposed SSMAC, con- to maximum precision, respectively. The MACISH architecture
sidering n = 8, nC = 20 as test case. The Fig. 6(a) and (b) [21] uses a recursive structure. The MAC ISH_1 involves only
report the NMED and MRED as a function of mC , for m = approximate 2 × 2 multipliers, whereas ISH_2 uses also exact
4. Results for m = 5 are shown in Fig. 6(c) and (d). Please multipliers. The IBAM architecture [22] uses imprecise adders
note that in these Figures the results for mC = 20 correspond to and multipliers, trying to compensate the error of the two blocks.
974 IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, VOL. 12, NO. 4, OCTOBER-DECEMBER 2024

Fig. 6. SSMAC with n = 8, nC = 20. Error performance as a function of mC . (a) NMED for m = 4. (b) MRED for m = 4. (c) NMED for m = 5.
(d) MRED for m = 5.

The considered approximate multiplier truncates the VBL = 3 The minimum delay is instead computed by synthesizing each
less significant columns of the PPM. MAC at the minimum timing constraint that allows to achieve a
The results in Tables II, III show that the investigated MACs positive slack.
cover a wide range of precision. The error performances of As shown in Tables II the proposed SSMACs show a re-
proposed SSMACs with m = 45 are comparable with [10], [12], markable power reduction compared to the exact MAC, ranging
[20], and [21], with NMED and MRED in the range 2.56 × from 45%−66% for m = 4 and 16%−60% for m = 5. The
10−4 −3.3 × 10−3 , and 1.12 × 10−3 −1.44 × 10−2 for nC = segmentation on operand C reveals effective in reducing power
20, respectively. Similarly, NMED and MRED are in the range consumption. For example, the SSMAC architecture with m =
1.69 × 10−5 −4.21 × 10−4 , and 1.17 × 10−4 −2.81 × 10−3 for 5, mC = 20 has a power consumption of 225 μW, while the
nC =24. Only the implementations [14] and [22] show superior SSMAC with m = 5, mC = 14 exhibits a power consumption of
accuracy, with NMED and MRED in the ranges 2.19 × 10−6 188μW with almost the same precision. Likewise, also results
−2.97 × 10−5 and 1.11 × 10−5 −1.42 × 10−4 when nC = 20, in Table III show remarkable power improvements, ranging
respectively, and in the range 1.47 × 10−7 −1.97 × 10−6 and between 42.4%−69.5% for m = 4 and 12.8%−63.6% for m =
1.09 × 10−6 −1.43 × 10−5 when nC = 24. 5. Among the other investigated approximate MACs, [12] L =
4 and [20] mask = 0 show the largest power saving com-
pared to the exact MAC, offering 45% and 37.3% respectively
C. Electrical Performances for nC = 20, and 44.5% and 36.4% with nC = 24. Among
We synthesize the proposed SSMACs and the state-of-the-art the investigated circuits, area saving shows a similar trend as
in TSMC 28nm CMOS technology employing a physical flow power saving in both the cases nC = 20 and nC = 24 (with
in Cadence Genus. An exact Dadda MAC is also implemented improvements up to 50% with m = 4, mC = 10, and up to
for reference. We obtain the power dissipation by means of 34.4% with m = 5 and mC = 10 referring to data in Table II).
post-synthesis simulations with 105 random input vectors and At the same time, an increase of the minimum delay is reg-
toggle rate of 1GHz. The timing constraint is 500ps for all the istered due to the multiplexers that realize the shift and the
implementations, to obtain iso-delay area and power values. segmentation.
DI MEO et al.: APPROXIMATE MAC UNIT USING STATIC SEGMENTATION 975

TABLE II
ERROR METRICS AND ELECTRICAL PERFORMANCES OF THE MAC FOR N = 8 BITS AND NC = 20 BITS

Fig. 7. Tradeoff between (a) power saving and NMED and (b) power saving and MRED for n = 8, nC = 20 bits.

To put results in perspective, the Fig. 7 represents the trade-off proposed SSMACs exhibit a favorable trade-off between ac-
between power saving and the metrics NMED and MRED. curacy and power, defining the pareto front for NMED>5 ×
For the sake of simplicity, we focus our attention on the case 10−4 and MRED>3 × 10−3 . In this region, the proposed MACs
with n = 8, nC = 20, since the MACs with nC = 24 offer a overcome the designs of [10], [20] and [21], which achieve
comparable behavior both in terms of power and error metrics comparable error metrics with a lower power saving. The figure
(as observable from the tables). In the plots of Fig. 7, the highlights also that the MACs [14] and [22] offer the best accu-
optimal point is located in the top-left corner, corresponding racy at the cost of a reduced power improvement (limited around
to better precision and larger power reduction. As shown, the 20%). Therefore, the proposed SSMACs are good candidates
976 IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, VOL. 12, NO. 4, OCTOBER-DECEMBER 2024

TABLE III
ERROR METRICS AND ELECTRICAL PERFORMANCES OF THE MAC FOR N = 8 BITS AND NC = 24 BITS

for applications where the offered NMED and MRED can be PSNR about 27 dB). The IBAM MAC [22] shows a remarkably
tolerated. good behavior, with SSIM about 1 and PSNR larger than 67 dB.
The Fig. 8 shows some examples of Gaussian filtered “Cam-
V APPLICATIONS eraman” image. The images computed with the proposed SS-
MACs without correction and m = 4, mC = 12, 20 show a slight
A. Image Filtering
degradation in the background. The images obtained using the
The MACs performances are investigated in image filtering SSMACs with the correction technique are instead very close
applications, by using two kernels: the first one is a Gaussian to the exact case. The SSMACs without correction and m = 5,
low-pass filter with size 5 and standard deviation 2, while the mC = 14, 20 yield acceptable results.
second kernel approximates the linear motion of a camera by 10 In order to compare the power performances with the accu-
pixels, with an angle of 25 degrees. racy, we plot in Fig. 9 the power saving with respect to the
The Table IV shows the performances in terms of mean average PSNR. In other to simplify the visualization, we have
structural similarity index (SSIM) and peak signal-to-noise ratio included in this Figure only the corrected SSMACs (which give
(PSNR) in dB, having considered MACs with n = 8 and nC = 20 the best behavior, as pointed out above). As it can be observed,
bits. Here, we report the average values of SSIM and PSNR ob- the proposed SSMACs with m = 4, mC = 12, 20 and m = 5,
tained by processing two test images, “Lena” and “Cameramen”. mC = 12 offer the best trade-off between power and quality of
The last column of the Table reports the overall average SSIM results, giving an acceptable PSNR (between 30 and 35dB) with
and PSNR. The proposed SSMACs with correction perform a remarkable power reduction (larger than 40%).
quite well in this application, exhibiting an average SSIM larger
than 0.92 for all the investigated configurations, and SSIM larger
than 0.98 for mC ≥ 12. The average PSNR is up to 34.4 dB with B. Template Matching
m = 4 and overcomes 41 dB with m = 5 and mC ≥ 14. The Template matching is a method for finding the location of
SSMACs without correction, on the other hand, show a lower a template image in a larger image and is a common task in
SSIM that is smaller than 0.9 for mC = 10. several applications. The basic algorithm involves sliding the
The other investigated MACs also show good performance, template over the given image. At each position the template and
with the partial exceptions of [20] mask = 0 (SSIM about 0.88 the patch of the input image under the template are compared.
and PSNR about 20 dB) and [12] L = 4 (SSIM about 0.97 but The algorithm then selects the position with the maximum
DI MEO et al.: APPROXIMATE MAC UNIT USING STATIC SEGMENTATION 977

Fig. 8. “Cameramen” image filtered with Gaussian kernel.

TABLE IV
MAC RESULTS IN THE IMAGE PROCESSING APPLICATION

Fig. 9. Power saving versus average PSNR for image filtering

application.

similarity as the location of the template within the image. Sev-

eral comparison methods can be employed (see, for instance, the
OpenCv library [23]). In our experiment, we used the covariance
(corresponding to TM_CCOEFF mode in OpenCv), computed
as follows:
 d2−1
d1−1 
C(x, y) = I(x − i, y − j)T (i, j) − μI · μT (28)
i=0 j=0

where T is the template including d1 × d2 pixels, I is the image,

μT is the mean value of the template and μI is the mean values
of the patch of the image under the template. The investigated
978 IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, VOL. 12, NO. 4, OCTOBER-DECEMBER 2024

TABLE V The third column in Table V reports whether a correct match

MAC RESULTS FOR TEMPLATE MATCHING
has been obtained or not. It can be observed that all the SSMACs
allow to obtain a correct match, with the exception of the two
versions with: m = 4, mC = 12 and m = 5, mC = 12. The
architectures [12] L = 4, [21] ISH_1 and Kulkarni [10] are also
unable to obtain the right match. The Fig. 10(b) represents the
obtained matching for SSMAC(414), SSMAC∗ (414), and [21]
ISH_1.

VI CONCLUSION
In this paper we have proposed a novel approximate multiply-
and-accumulate unit, that computes Y = A × B+C using
static segmentation. The developed architecture uses a unique
carry-propagate adder and performs segmentation on the three
operands, by using a reduced word length adder. A correction
technique is also proposed for recovering precision. The pro-
posed circuit can be configured at design-time by two parame-
ters. The first one controls the segmentation on A and B, while
the second one controls the segmentation on C and the adder
length.
Analysis of error metrics and VLSI synthesis results in 28 nm
CMOS technology are presented. The obtained results show that
the proposed approximate MACs outperform the state of the art,
exhibiting a favorable trade-off between accuracy and power
consumption.
Application examples to image filtering and template match-
ing confirm that proposed circuits are good candidates in appli-
cations where their error performances are acceptable.

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imgproc__object.html engineering and computer science from the Uni-
versity of Naples, Federico II, Italy, in July 1999
Gennaro Di Meo received the MS degree (cum and February 2003, respectively. For past 14
years, he worked in the area of digital integrated
laude) in electrical engineering, and the PhD de-
VLSI circuit design. He is an associate profes-
gree in information technology and electrical en-
sor with the Department of Electrical Engineer-
gineering from the University of Napoli Federico
ing and Information Technology, University of
II, Italy, in 2018 and 2022, respectively. Cur-
Naples Federico II. He is the author of more
rently, he is a postdoc researcher with the De-
than 80 technical articles in international journals and refereed inter-
partment of Information Technology and Electri-
cal Engineering, University of Napoli Federico national conferences.
II, Italy. His research interests include design
of digital VLSI circuits for telecommunications,
LMS filters, and approximate computing.

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