Worksheet 1

1. Draw the architecture of 8086 MP and discuss the detailed working principle?

The 8086 microprocessor is divided in to 2 logical units: the bus interface unit and the execution
unit. Each unit has dedicated function and both operate simultaneously. The BIU is responsible
for establishing communication with the outside world (memory, I/O devices). It performs all
external bus operation, such as fetching, reading and writing of data operands from and to a
memory, and calculating physical address. When program execution begins, the BIU uses the
code segment (CS) register and instruction pointer (IP) to compute the physical address of the
next instruction. It then fetches the instruction from memory and place it in instruction queue,
allowing the BIU to fetch the next instruction even before the EU finish the execution of the
current one. This is called pipelining, which improves efficiency by simultaneously performing
the fetch and execute stages.
While the BIU proceeds prefetching instructions, the execution unit (EU) takes the next
instruction from queue and decodes it. Depending on the instruction the EU perform arithmetic
or logic operations using the ALU. When an instruction requires data from memory, the EU send
the offset address to BIU, which combines it with segment register to form physical address. BIU
then perform a memory read over system bus and retrieve the operands. Once it has fetched the
operand, it forwards it to EU over the data bus. The EU receives the operand and store it in AX
(or register specified by the instruction). The operand in AX moves through the system bus to the
ALU when it is need for execution. ALU performs the necessary computation, and the flag
register is updated to reflect the result. The result of the operation is sent back to the AX register
or any other specified register through the system bus. If results are going to be stored in
memory, the BIU handles the writing process.
2. Explain the architecture of the 8086 microprocessor and how it differs from other
microprocessors?
The 8086 microprocessor is divided in two logical units: the execution unit and the bus interface
unit. The BIU is responsible for communication with memory and I/O devices. It contains the
segment registers (CS, DS, SS, ES), along with instruction pointer (IP), the address adder and 6-
byte instruction queues that enables pipelining. The EU executes decode and execute
instructions. It contains the arithmetic logic unit (ALU), the general-purpose registers (AX, BX,
CX, DX) for storing operands, pointer and index registers (SP, BP, SI, DI) for addressing and
flag registers which stores the status and control flag.
The things that made the 8086 architectures different from other microprocessors (like the earlier
8085) are its 16-bit data bus, 20-bit address bus, and pipelined architecture, which makes it much
faster. Earlier processors used a single bus and executed instructions sequentially. However, the
8086 can fetch the next instruction while executing the current one, improving performance. It
also introduced segmented memory organization. it laid the foundation for later Intel processors.
3. Explain the concept of pipelining in the 8086 microprocessor and how it improves the
processing speed.
In the 8086 microprocessors, pipelining become practical through the division of the processor in
to 2 logical unit: the BIU and EU. The BIU is responsible for fetching from memory and placing
then in instruction queue, while the EU decodes and execute them from the instruction queue.
This allows the fetching and executed to be done simultaneously. While the EU is busy
executing the BIU fetches the instruction. This way, the processor reduces the idle time and
improves efficiency, because the EU doesn’t have to wait for memory access.
4. Why IP is located in BIU? and what will happen if it is located in EU?
the instruction pointer is located in BIU because fetching instruction falls under the
responsibility of BIU. The IP holds the offset address of the next instruction currently to be
fetched which combines with the codes segment register to form the physical address of the next
instruction to be fetched. Since BIU handles memory related operations including fetching
instruction it needs direct access to IP to facilitate pipelining.
If the IP was located in the EU instead, the BIU would have to wait for the next instruction to be
fetch to be provided by the EU, which prevents the prefetching and therefore pipelining. This
process would lead to slower performance since each instruction has to wait until the previous
instruction is executed before being fetched.
5. Why is divided into BIU and EU?
The 8086 microprocessor is divided in two main logical units: the bus interface unit and
execution unit to efficiency and performance. This division allows to perform 2 major operations
simultaneously, the BIU fetch instruction or data while the EU is busy decoding and executing
the previously fetched instruction. By separating these two functions, the 8086 implements
pipelining, where instruction fetching and execution overlap, reducing the idle time and
increasing performance.
6. Discuss the architectural and signal differences between 8086 and 8088.
The 8088 and 8086 microprocessor share nearly the same internal architecture, but differ in bus
structure and signal characteristics. Architecturally, both processors have same register set,
instruction set, both are divided in to two main unit (BIU and EU). However, the main difference
arises in their data bus. The 8086 has 16-bit data bus while the 8088 has 8-bit data bus. This
difference impacted the control signals used to communicate with memory and I/O devices.
While both processors use standard signals like RD, WR…, the 8088 requires additional timing
coordinator because the 16-bit word must be split in to 8-bit transfers. Therefore the 8088
perform read or write operation twice whereas the 8086 perform the same operation in single bus
cycle. The prefetch(instruction) queue in the BIU also differs. It 6 bytes long in 8086 but only 4
bytes in 8088.
7. What is the difference between status and control flag bits of 8086?
The flag register in the 8086 microprocessor contain 2 types of bits: the status and control flag.
Status lag indicate conditions that are produced as a result of executing an instruction. After the
executing an instruction, such as ADD, specific flag bits are reset (0) or set (1) based on the
result produced. These are primarily used by processor for conditional operation. Control flag, on
the other hand, are used to guide or modify the behavior of processor for upcoming instructions.
Status flag reports what just happened, while control flag determines what the processor will do
next.
8. What is the flag register in an 8086 microprocessor? And what is the purpose of
conditional flags of 8086?
The flag register in the 8086 microprocessor is 16-bit register that stores information about the
outcome of executed instruction and helps to control CPU behavior. Each bit in the register
represents a status or control flag. Status flag indicates condition that are produced as the result
of an arithmetic or logical operation such as a result is zero, negative, cause an overflow. The
conditional flags are part of the status flag, and are used to determine flow of program execution.
These include the zero flag, the carry flag, the sign flag, and the overflow flag. After an
operation, these flags are set or cleared depending on the result. Condition instructions, like jump
if zero or jump if carry, checks these flags to determine whether the CPU should branch or
continue sequentially. This way conditional flags allow the processor to control program flow
based on the result of the previous operation.
9. Why is segment override prefix necessary in assembly language?
Segment overrider prefix is special byte added to an instruction in 8086 assembly language to
use different register than the default one that it normally uses. It is necessary because 8086
assumes that certain type of memory access will always use specific segment register. However,
there are situations where the programmer needs to access the memory in different segment than
default. The segment override prefix allows instruction to use segment register other than the
default. This gives the programmer explicit control over the segment accessed.
10. What is the maximum memory capacity that can be addressed by the 8086
microprocessor?
The maximum memory capacity that can be addressed by the 8086 microprocessor is 1MB. This
is because the 8086 has 20-bit address bus which generate 220 unique addresses.
220 = 1𝑀𝐵

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