ELE 501 - Lecture 2

IC Amplifier Building Blocks

Textbook: Chapter 7 (Sections 7.2-7.3)

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 1

 Common Gate Amplifier
The common gate amplifier  Gate is grounded (in small signal)
Small signal analysis circuit (ignoring body effect):
io  ii
vo
Input resistance ignoring ro
D
i vi
G RL Rin 
ii
S
i
1⁄ 𝑔
1
vi Rin 
gm
Rs ii

vsig

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 2

 Input Resistance with ro
Taking ro into account
io  ii vi
vo Rin 
D
ii
i ii  g m vi  iro
G RL
ro vi  vo
iro  vo  ii RL
S ro
i
1⁄𝑔 iro ro  RL 1 R
Rin  Rin   L
vi 1  g m ro g m g m ro

Rs ii
ro  
Ignore ro
 Rin 
1
gm
vsig
𝑅 ≅𝑟  Rin 
2
gm
Usual case
© D. Tannir – Fall 2025 ELE 501 - Lecture 2 3
 Voltage Gains
Output Voltage
Voltage Gain 
Input Voltage

• Open Circuit Amplifier Gain Avo (no source, no load)

• Amplifier Gain with load Av (no source)

• Open Circuit overall voltage gain Gvo (with source, no load)

• Overall voltage gain Gv

Let us derive each one of these gains for the Common Gate
with ro
© D. Tannir – Fall 2025 ELE 501 - Lecture 2 4
 Open Circuit Voltage Gain
io  ii  0
vo  iro  vi
D
iro  i  vi g m i
G
ro
vo  g m ro vi  vi
S
Non-inverting 1 gm i
iro
vi
vo Rs ii
Avo   1  g m ro
vi Rin
RL   vsig

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 5

 Open Circuit Voltage Gain
The input resistance can also be expressed in terms of the open-
circuit voltage gain

ro  RL
Recall: Rin  Avo  1  g m ro  g m ro
1  g m ro

ro  RL
Rin 
Avo

1 RL
Rin  
g m Avo

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 6

 Open Circuit Overall Voltage Gain
The overall gain while accounting for “source io  ii  0
resistance” but no load.
D
vo i
Gvo  G
vsig ro
RL  

S
1 gm i
io  ii  0 iro
vi
vsig  vi
Rs ii
No voltage drop across Rs Rin
vsig
Gvo  Avo  1  g m ro

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 7

 Voltage Gain with Load
vo  io RL  ii RL io  ii
vo
vi  ii Rin
D
The voltage gain is vo/vi
i
vo RL G RL
Av   ro
vi Rin
S
r  RL
1 gm i
Substitute the iro
value of Rin Rin  o
Avo vi
RL Rs ii
Av  Avo
RL  ro Rin
vsig

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 8

 Overall Voltage Gain with Load
vo  io RL  ii RL io  ii
vo
vsig  ii Rs  Rin  D
i
G RL
vo RL ro
Gv   S
vsig Rs  Rin 1 gm i
iro
vi
ro  RL
Recall: Rin  Rs ii
Avo
Rin
RL vsig
Gv  Avo
RL  ro  Avo Rs
© D. Tannir – Fall 2025 ELE 501 - Lecture 2 9
 Output Resistance
vi vo

Rs io

vsig

Two kinds of output resistance:

vo vo
Rout  Ro   Rout
io v sig  0 io Rs  0
vi  0

Accounts for the Does not account for the

source resistance effect of the source resistance

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 10

 Output Resistance
What is Ro? (Set vi to zero)
ix
i  vsg g m  0 vx
D
vx
ix  iro  G
i
ro
ro
S
1 gm i
iro
vx
Ro   ro
ix

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 11

 Output Resistance with Rs
What is Rout? (Set vsig to zero) Rout  v x ix
ix vx
i  g mv D
v x  ix  i ro  v v  ix Rs i ix  i
G
i  g m Rsix
ro
v x  ix  g m Rs ix ro  Rs ix 1 gm
S
i
Rout   1  g m Rs ro  Rs
vx
ix v
Rout  ro  1  g m ro Rs Rs ix

Rout  ro  Avo Rs
© D. Tannir – Fall 2025 ELE 501 - Lecture 2 12
 Impedance Transformation
Summarizing the derived relations illustrates the concept of
impedance transformation between output and input of a Common
Gate Amplifier

RL
Rout  ro  Avo Rs  g m ro Rs
D

G 1 RL
S Rin  
g m Avo
Rs
Avo  1  g m ro  g m ro
© D. Tannir – Fall 2025 ELE 501 - Lecture 2 13
 Common Gate - Exercise
• Neglecting VA, find the drain current of Q1 and the required VBIAS
• While accounting for VA, find the value of Rin
3.3V 3.3V W  W 
 n Cox     p Cox    4mA/V
2

 L n  L p

Vt  0.8V
Q3 Q2 For all Transistors
VA  20V
vO

100A Q1 ID1
VBIAS

I D1  100μA
50
VBIAS  1.03V
vsig
Rin  2.24k

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 14

 BJT Equivalent

Rin 𝑒

© D. Tannir – Fall 2025 ELE 501 - Lecture 2 15