UNIT IV

The 8051 microcontroller: Architecture, pin diagram, memory organization, external memory
interfacing, stack, addressing modes, instruction set, Assembler directives, Assembly Language
programs and Time delay Calculations, 8051 interrupt structure, 8051 counters and Timers,
programming 8051 timers.

Text Book:

The 8051 microcontroller: Architecture, Programming & Applications, Kenneth J Ayala, penram
publications, 2nd edition.
[Link]
ocontroller%20Architecture,%20Programming%20and%20Applications%[Link]

THE 8051 ARCHITECTURE

Salient features of 8051 microcontroller are given below:
➢ Eight bit CPU
➢ On chip clock oscillator
➢ 4Kbytes of internal program memory (code memory) [ROM]
➢ 128 bytes of internal data memory [RAM]
➢ 64 Kbytes of external program memory address space.
➢ 64 Kbytes of external data memory address space.
➢ 32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable I/O
lines)
➢ Two 16 Bit Timer/Counter :T0, T1
➢ Full Duplex serial data receiver/transmitter
➢ Four Register banks with 8 registers in each bank.
➢ Sixteen bit Program counter (PC) and a data pointer (DPTR)
➢ 8 Bit Program Status Word (PSW)
➢ 8 Bit Stack Pointer
➢ Five vector interrupt structure (RESET not considered as an interrupt.)
➢ 8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’ , B register,
PSW, SP, 16 bit program counter, stack pointer.
➢ ALU can perform arithmetic and logic functions on 8 bit variables.
➢ 8051 has 128 bytes of internal RAM which is divided into
o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]
8051 Microcontroller Architecture:

Figure: Internal architecture of 8051 microcontroller

Figure shows internal architecture of 8051 microcontroller. The 8051 includes an 8-bit CPU, Memory,
four 8 bit I/O ports, two timers/counters and a Universal Asynchronous Receiver Transmitter (UART).

PROCESSOR: The processor includes arithmetic and logic unit, instruction decoder and timing
generation unit, Accumulator (A), B and status register.

ALU: The ALU performs the computing functions.

It is an 8 bit unit. It performs arithmetic operation as addition, subtraction, multiplication, division,

increment and decrement. It performs logical operations like AND, OR and EX-OR. It manipulates 8
bit and 16 bit data. It calculates address of jump locations in relative branch instruction. It performs
compare, rotate and complement operations. It consists of a Boolean processor which performs bit,
set, test, clear and compliment. 8051 microcontroller contains 34 general purpose registers or
working registers. 2 of them are called math registers A & B and 32 are bank of registers.

a. Accumulator(A-register): It is an 8 bit register. Its address is E0H and it is bit and byte
accessible. Results of arithmetic & logic operations performed by ALU are accumulated by this
register. Therefore it is called an accumulator register. It is used to store an 8 bit data and to hold one
of the operands of ALU units during arithmetical and logical operations. Most of the instructions are
carried out on accumulator data. It is the most versatile of 2 CPU registers.

b. B-register: It is a special 8 bit math register. It is bit and byte accessible. It is used in conjunction
with A register as I/P operand for ALU. It is used as a general purpose register to store 8 bit data.

c. PSW: It is an 8 bit register. Its address is D0H and It is bit and byte accessible. It has 4 conditional
flags or math flags which sets or resets according to condition of result. It has 3 control flags, by
setting or resetting bit required operation or function can be achieved. The format of flag register is
as shown below:

CY AC F0 RS1 RS0 OV -- P

FLAGS:

1. Carry Flag(CY): During addition and subtraction any carry or borrow is generated then carry
flag is set otherwise carry flag resets. It is used in arithmetic, logical, jump, rotate and Boolean
operations.

2. Auxiliary carry flag(AC): If during addition and subtraction any carry or borrow is generated
from lower 4 bit to higher 4 bit then AC sets else it resets. It is used in BCD arithmetic operations.

3. Overflow flag(OV): If in signed arithmetic operations the result exceeds more than 7 bit than OV
flag sets, else resets. It is used in signed arithmetic operations only.

4. Parity flag(P): Set when ACC contains an odd number of 1’s. Cleared when ACC contains an
even number of 1’s. (If in the result, even [Link] ones "1" are present then it is called even parity and
parity flag resets. In result odd [Link] ones "1"are present then it is called odd parity and parity flag
sets.)

CONTROL FLAGS:

1. FO: It is a user defined flag. The user defines the function of this flag. The user can set ,test n
clear this flag through software.

2. RS1 and RS0: These flags are used to select bank of register by resetting those flags which are as
shown in table :
 RS1 RS0 Bank selected

0 0 Bank 0

0 1 Bank 1

1 0 Bank 2

1 1 Bank 3

Program counter (PC): The Program Counter (PC) is a 2-byte address which tells the 8051 where
the next instruction to execute is found in memory.. When the 8051 is initialized, the PC always
starts at 0000h and is incremented each time an instruction is executed.

Data pointer register (DTPR): It is a 16 bit register used to hold the address of external or internal
RAM where data is stored or result is to be stored. It is used to store 16 bit data. It is divided into2-
8bit registers, DPH-data pointer higher order (83H) and DPL-data pointer lower order (82H). Each
register can be used as a general purpose register to store 8 bit data and can also be used as memory
location. DPTR does not have a single internal address. It functions as Base register in base relative
addressing mode and in-direct jump.

Stack pointer (SP): It is an 8-bit register. It is byte addressable. Its address is 81H. It is used to hold
the internal RAM memory location addresses which are used as stack memory. When the data is to
be placed on stack by push instruction, the content of stack pointer is incremented by 1, and when
data is retrieved from stack, content of stack of stack pointer is decremented by 1.

Instruction decoder and control: This is the part of timing and control unit. When an instruction is
fetched from program memory, it is loaded in the instruction register. The decoder decodes the
instruction and establishes the sequence of events to follow. The timing generation and control unit
synchronizes all microcontroller operations with the clock and generates control signals necessary for
communication between the processor and peripherals.

8051 has 4 K Bytes of internal ROM. The address space is from 0000 to 0FFFh. If the program size
is more than 4 K Bytes 8051 will fetch the code automatically from external memory.

Oscillator and clock generator: All operations in a microcontroller are synchronized by the help of
an oscillator clock. The oscillator clock generates the clock pulses by which all internal operations
are synchronized. A resonant network connected through pins XTAL1 and XTAL2 forms up an
oscillator. For this purpose a quartz crystal and capacitors are employed. The crystal run at specified
maximum and minimum frequencies typically at 1 MHz to 16 MHz.

Special function Registers(SFR): The 8051 microcontroller has 11 SFR divided in 4 groups:
A. Timer/Counter register: 8051 microcontroller has two16 bit Timer/counter registers called
Timer-register-T0 And Timer/counter Register-T1. Each register is a 16 bit register divided into lower
and higher byte registers as shown below: These registers are used to hold initial no. of count. All of the
4 registers are byte addressable.
1. Timer control register: 8051 microcontroller has two 8-bit timer control register i.e. TMOD and
TCON register. TMOD Register: it is an 8-bit register. Its address is 89H. It is byte addressable. It used
to select mode and control the operation of time by writing control words.
2. TCON register: It is an 8-bit register. Its address is 88H. It is byte addressable. Its MSB 4- bit are
used to control operation of the timer/ counter and LSB 4-bit are used for external interrupt control.
B. Serial data register: 8051 micro controller has 2 serial data register viz. SBUF and SCON.
1. Serial buffer register (SBUF): It is an 8-bit register. It is byte addressable .Its address is 99H. It is
used to hold data which is to be transferred serially.
2. Serial control register (SCON): It is an 8-bit register. It is bit/byte addressable. Its address is 98H.
The 8-bit loaded into this register controls the operation of serial communication.
C. Interrupt register: 8051 µC has two 8-bit interrupt registers.
1. Interrupt enable register (IE): It is an 8-bit register. It is bit/byte addressable. Its address is A8H. It
is used to enable and disable the function of interrupt.
2. Interrupt priority register (IP): It is an 8-bit register. It is bit/byte addressable. Its address is B8H. It
is used to select low or high level priority of each individual interrupts.
D. Power control register (PCON): It is an 8-bit register. It is byte addressable. It’s address is 87H. It’s
bits are used to control mode of power saving circuit, either idle or power down mode and also one bit is
used to modify baud rate of serial communication.
PIN DIAGRAM

Pinout Description

Pins 1-8 PORT 1. Each of these pins can be configured as an input or an output.

Pin 9 RESET. A logic one on this pin for two machine cycles disables the
microcontroller and clears the contents of most registers. In other words,
the positive voltage on this pin resets the microcontroller. By applying
logic one to this pin, the program starts execution from the beginning.

Pins 10-17 PORT 3. Similar to port 1, each of these pins can serve as general input or
output. Besides, all of them have alternative functions.

Pin 10 RXD. Serial asynchronous communication input or Serial synchronous

communication output.

Pin 11 TXD. Serial asynchronous communication output or Serial

synchronous communication clock output.

Pin 12 [Link] Interrupt 0 input

Pin 13 INT1. External Interrupt 1 input

Pin 14 T0. Counter 0 clock input

Pin 15 T1. Counter 1 clock input

Pin 16 WR. Write to external (additional) RAM

Pin 17 RD. Read from external RAM

Pin 18, XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal
19 which specifies operating frequency is usually connected to these pins.

Pin 20 GND. Ground.

Pin 21-28 Port 2. If there is no intention to use external memory then these port pins
are configured as general inputs/outputs. In case external memory is
used, the higher address byte, i.e. addresses A8-A15 will appear on this
port. Even though memory with capacity of 64Kb is not used, which
means that not all eight port bits are used for its addressing, the rest of
them are not available as inputs/outputs.

Pin 29 PSEN. If an external ROM is used for storing a program then a logic zero
(0) appears on it every time the microcontroller reads a byte from memory.

Pin 30 ALE. Prior to reading from external memory, the microcontroller puts the
lower address byte (A0-A7) on P0 and activates the ALE output. After
receiving a signal from the ALE pin, the external latch latches the state of
P0 and uses it as a memory chip address. Immediately after that, the ALE
pin returned its previous logic state and P0 is now used as a Data Bus.

Pin 31 EA. By applying logic zero to this pin, P2 and P3 are used for data and
address transmission with no regard to whether there is internal memory
or not. It means that even there is a program written to the
microcontroller, it will not be executed. Instead, the program written to
external ROM will be executed. By applying logic one to the EA pin, the
microcontroller will use both memories, first internal then external (if
exists).

Pin 32-39 PORT 0. Similar to P2, if external memory is not used, these pins can be
used as general inputs/outputs. Otherwise, P0 is configured as address
output (A0-A7) when the ALE pin is driven high (1) or as data output
(Data Bus) when the ALE pin is driven low (0).

Pin 40 VCC. +5V power supply.

MEMORY ORGANIZATION: Internal RAM organization

Register Banks: 00h to 1Fh. The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1, R2,
R3, R4, R5, R6, and R7). There are four such register banks. Selection of register bank can be done
through RS1,RS0 bits of PSW. On reset, the default Register Bank 0 will be selected.

Bit Addressable RAM: 20h to 2Fh . The 8051 supports a special feature which allows access to bit
variables. This is where individual memory bits in Internal RAM can be set or cleared. In all there are
128 bits numbered 00h to 7Fh. Being bit variables any one variable can have a value 0 or 1. A bit
variable can be set with a command such as SETB and cleared with a command such as CLR. Example
instructions are: SETB 25h ; sets the bit 25h (becomes 1)
CLR 25h ; clears bit 25h (becomes 0) Note, bit 25h is actually bit 5 of Internal RAM location 24h.
The Bit Addressable area of the RAM is just 16 bytes of Internal RAM located between 20h and 2Fh.

General Purpose RAM: 30h to 7Fh. Even if 80 bytes of Internal RAM memory are available for
general-purpose data storage, user should take care while using the memory location from 00 -2Fh
since these locations are also the default register space, stack space, and bit addressable space. It is a
good practice to use general purpose memory from 30 – 7Fh. The general purpose RAM can be
accessed using direct or indirect addressing modes.

EXTERNAL MEMORY INTERFACING

Interfacing of 16 K Byte of RAM and 32 K Byte of EPROM to 8051.
Number of address lines required for 16 Kbyte memory is 14 lines and that of 32Kbytes of memory is 15
lines.

The lower order address and data bus are multiplexed. De-multiplexing is done by the latch. Initially
the address will appear in the bus and this latched at the output of latch using ALE signal. The output of
the latch is directly connected to the lower byte address lines of the memory. Later data will be
available in this bus. Still the latch output is address itself. The higher byte of the address bus is directly
connected to the memory. The number of lines connected depends on the memory size.

The RD and WR (both active low) signals are connected to RAM for reading and writing the data.
PSEN of the microcontroller is connected to the output enable of the ROM to read the data from the
memory.

EA (active low) pin is always grounded if we use only external memory. Otherwise, once the program
size exceeds internal memory the microcontroller will automatically switch to external memory.

STACK
A stack is a last in first out (LIFO) memory. In 8051 128 bytes of internal RAM space can be used as
a stack. The address of the stack is contained in a register called stack pointer. Instructions PUSH and
POP are used for stack operations. When a data is to be placed on the stack, the stack pointer
increments before storing the data on the stack so that the stack grows up as data is stored
(pre-increment). As the data is retrieved from the stack the byte is read from the stack, and then SP
decrements to point to the next available byte of stored data (post decrement). The stack pointer is set
to 07 when the 8051 resets. So that default stack memory starts from address location 08 onwards (to
avoid overwriting the default register bank ie., bank 0).

ADDRESSING MODES
Various methods of accessing the data are called addressing modes. 8051 addressing modes are
classified as follows.
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.
1. Immediate addressing.
In this addressing mode the data is provided as a part of instruction itself. In
other words, data immediately follows the instruction.
Eg. MOV A,#30H
ADD A, #83 # Symbol indicates the data is immediate.
2. Register addressing.
In this addressing mode the register will hold the data. One of the eight general registers
(R0 to R7) can be used and specified as the operand.
Eg. MOV A,R0
ADD A,R6

R0 – R7 will be selected from the current selection of register bank. The default register bank will
be bank 0.

3. Direct addressing
There are two ways to access the internal memory. Using direct address and indirect
address. Using direct addressing mode we can not only address the internal memory but SFRs also.
In direct addressing, an 8 bit internal data memory address is specified as part of the instruction
and hence, it can specify the address only in the range of 00H to FFH. In this addressing mode,
data is obtained directly from the memory.
Eg. MOV A,60h
ADD A,30h
4. Indirect addressing
The indirect addressing mode uses a register to hold the actual address that will be used
in data movement. Registers R0 and R1 and DPTR are the only registers that can be used as data
pointers. Indirect addressing cannot be used to refer to SFR registers. Both R0 and R1 can hold 8
bit address and DPTR can hold 16 bit address.
Eg. MOV A,@R0
ADD A,@R1
MOVX A,@DPTR
5. Indexed addressing.
In indexed addressing, either the program counter (PC), or the data pointer (DTPR)—is
used to hold the base address, and the A is used to hold the offset address. Adding the value of
the base address to the value of the offset address forms the effective address. Indexed
addressing is used with JMP or MOVC instructions. Look up tables are easily implemented with
the help of index addressing.
Eg. MOVC A, @A+DPTR // copies the contents of memory location pointed by the
sum of the accumulator A and the DPTR into accumulator A.
MOVC A, @A+PC // copies the contents of memory location pointed by the sum of the
accumulator A and the program counter into accumulator A.

6. Relative Addressing.
Relative addressing is used only with conditional jump instructions. The relative address,
(offset), is an 8 bit signed number, which is automatically added to the PC to make the address of
the next instruction. The 8 bit signed offset value gives an address range of +127 to —128
locations. The jump destination is usually specified using a label and the assembler calculates the
jump offset accordingly. The advantage of relative addressing is that the program code is easy to
relocate and the address is relative to position in the memory.
Eg. SJMP LOOP1
JC BACK
7. Absolute addressing
Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute
Call) instructions. These are 2 bytes instructions. The absolute addressing mode specifies the
lowest 11 bit of the memory address as part of the instruction. The upper 5 bit of the destination
address are the upper 5 bit of the current program counter. Hence, absolute addressing allows
branching only within the current 2 Kbyte page of the program memory.
Eg. AJMP LOOP1 ACALL LOOP2

8. Long Addressing
The long addressing mode is used with the instructions LJMP and LCALL. These are 3 byte
instructions. The address specifies a full 16 bit destination address so that a jump or a call can be
made to a location within a 64 Kbyte code memory space.
Eg. LJMP FINISH
LCALL DELAY
9. Bit Inherent Addressing

In this addressing, the address of the flag which contains the operand, is implied in the opcode of
the instruction.

Eg. CLR C ; Clears the carry flag to 0

10. Bit Direct Addressing

In this addressing mode the direct address of the bit is specified in the instruction. The RAM
space 20H to 2FH and most of the special function registers are bit addressable. Bit address
values are between 00H to 7FH.

Eg. CLR 07h ; Clears the bit 7 of 20h RAM space

SETB 07H ; Sets the bit 7 of 20H RAM space.

8051 INSTRUCTIONS:
The instructions use 8 bit registers A, B, R0, R1, R2, R3, R4, R5, R6, R7 and also 16 bit registers,
DPTR (data pointer) and PC (program counter).

The instructions of 8051 can be broadly classified under the following headings:
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation instructions

The following notations are used in the description of the instruction.

Rn means any of the eight registers (R0 to R7) in the selected banks.
Ri means either of the pointing registers (R0 or R1) in the selected banks.
M means internal data memory.
E.D.M. means external data memory.
P.M. means internal or external program memory.

Data Transfer Instructions:

In this group of instructions, none of the flags of the status register are affected.

MOV A, Rn: Copy the contents of a register Rn to A:

This instruction copies the contents of register Rn to A.
It is a 1 byte instruction.
Example: MOV A, R2; Contents of R2 is copied into register A.

MOV Rn, A: Copy the contents of a register A to Rn:

This instruction copies the contents of A to Rn.
It is a 1 byte instruction.
Example: MOV R7, A; Contents of A is copied into register R7.

MOV A, #data: Copy an 8 bit immediate data into register A or to Rn or to a memory location. This
type of instruction loads the immediate data to A or to Rn or to the memory by using direct and indirect
addressing.
Example: MOV A, #77; 77 is copied into register A.

MOV Rn, #data: Copy an 8 bit immediate data into register Rn.
This type of instruction loads the immediate data into register Rn.
Example: MOV R3, #77; 77 is copied into register R3.

MOV direct memory, #data: Copy an 8 bit immediate data into a memory location.
This type of instruction loads the immediate data into the memory.
Example: MOV 70,#77; 77 is copied into memory location 70 H.

MOV @Ri, #data: Copy an 8 bit immediate data into a memory location pointed by Ri register (R0 or
R1).
This type of instruction loads the immediate data into the memory location pointed by the Ri register.
Example: MOV @R0,#77; 77 is copied into the memory location pointed by R0 H.

MOV DPTR, #16bitdata: Copy 16 bit immediate data into the DPTR register.
This type of instruction loads the 16-bit immediate data into the DPTR register.
Example: MOV DPTR, #1234 H

MOV A, direct: Copy the contents of a memory location to A.

Example: MOV A, 70; The contents of the memory location 70H is copied into register A.

MOV direct, A: Copy the contents of A into memory location.

Example: MOV 70, A; The contents of register A is copied into memory location 70H.

MOV A, @Ri: Copy the contents of the memory location pointed by Ri into register A.
Example: MOV A, @R1; The contents of the memory location pointed by register R1 is copied
into register A.

MOV @Ri, A: Copy the contents of the register A into the memory location pointed by Ri .
Example: MOV @R1, A ; The contents of the register A is copied into the memory location
pointed by register R1.

MOV Rn, direct: Copy the contents of the memory location into the register Rn.
Example: MOV R3, 60; The contents of the 60 H memory location is copied into the register R3.

MOV direct, Rn: Copy the contents of the Rn register into the memory location.
Example: MOV 70, R4; The contents of the register R4 is copied into the 70 H Memory location.
MOV direct1, direct2: Copy the contents of direct2 memory location to direct1 memory location.
Example: MOV 77, 70; The contents of the 70H memory location is copied into 77H memory
location.

MOV direct, @Ri: Copy the contents of the memory location pointed by Ri register into the memory
location.
Example: MOV 77, @R1; The contents of the memory location pointed by register R1 is copied
into 77H memory location.

MOVX A, @Ri: Copy the contents of an external data memory location pointed by Ri into A.

MOVX @Ri,A: Copy the contents of the register A to an external data memory pointed by
register Ri.

MOVX A, @DPTR: Copy the contents of an external data memory location pointed by DPTR
into register A.

MOVX @DPTR, A: Copy the contents of register A into an external data memory pointed by
DPTR.

MOVC A, @A+PC: Copy the code byte to accumulator:

Copy the contents of program memory location pointed by register A and PC to register A.

MOVC A,@ A+DPTR: Copy code byte to accumulator:

Copy the contents of the program memory location pointed by A and DPTR to register A.

Push instruction:
Push instruction increments SP by 1 and then copies the data at direct address to the location pointed by
SP.
Syntax: PUSH direct
Operation: [SP] ←[SP]+1
[[SP]]← direct

Pop instruction:
Pop instruction copies the data at the location pointed by SP to the direct address and then decrements
SP by 1.
Syntax: POP direct
Operation: direct ← [[SP]]
[SP] ← [SP]-1

Exchange instructions:

XCH A, Rn: The contents of the register Rn is copied into A and the contents of the register A is
copied into register Rn.

XCH A, direct: The contents of the memory location is exchanged with the contents of register A.
XCH A,@Ri: The contents of the memory location pointed by the register Ri is exchanged with the
contents of register A.

XCHD A, @Ri: Exchange digit

XCHD instruction exchanges the low–order nibble of the A bits (bits 3–0), with that of the internal
RAM location indirectly addressed by the specified register.

Arithmetic Instructions:

ADD A, #data: Add an 8-bit immediate data to accumulator A and store the result in A.

ADDC A, #data: Add an 8-bit immediate data and the contents of carry flag to accumulator A and
store the result in A.

ADD A,Rn: Add the contents of register Rn to accumulator A and store the result in A.

ADDC A, Rn Add the contents of register Rn and the contents of carry flag to accumulator A and store
the result in A.

ADD A, direct Add the contents of direct memory to accumulator A and store the result in A.

ADDC A, direct Add the contents of direct memory and the contents of carry flag to accumulator A and
store the result in A.

ADD A,@Ri Add the contents of memory location pointed to by Ri to accumulator A and store the
result in A.

ADDC A,@Ri Add the contents of memory location pointed to by Ri and the contents of carry flag to
accumulator A and store the result in A.

SUBB A, #data Subtract immediate data and the contents of carry flag from A and store the result in A

SUBB A,Rn Subtract the contents register Rn and the contents of carry flag from A and store the result
in A

SUBB A, direct Subtract the contents of direct memory and the contents of carry flag from A and store
the result in A.

SUBB A, @Ri Subtract the contents of memory location pointed by Ri and the contents of carry flag
from A and store the result in A.

MUL AB Multiplies the unsigned 8 bit integer in the A and register B. Low order byte of the result is
stored in the A and high order byte of the result is stored in B. After the execution, the carry flag is
cleared.

DIV AB Divides the unsigned 8 bit integer in the A by the unsigned 8 bit integer in register B. The
quotient is stored in the A and the remainder is stored in the B register. The carry and overflow flags are
cleared. If the content of B is zero, then OV is set.

DA A Decimal Adjustment After Addition

When two Binary Coded Decimal (BCD) numbers are added, the answer is a non–BCD number. To get
the result in BCD, DA A instruction is executed after adding two BCD numbers and storing the result in
an A. The working of DA A is as follows.

If the lower nibble of A ≤ 9 and the auxiliary flag is 0, then the lower nibble will not be altered.
If a lower nibble is greater than 9 or an auxiliary flag is set, then 6 is added to the lower nibble and after
addition, if there is a carry, then the upper nibble is incremented by one.
If the upper nibble of A ≤ 9 and the carry flag is 0, then the upper nibble will not be altered.
If the upper nibble is greater than 9 or the carry flag is set, then 6 is added to the upper nibble and after
addition, if there is a carry, carry flag is set.

INC A Increments the contents of A by 1:

[A] ← [A]+1

INC Rn
INC R5 Increments the contents of register 5 by 1:
[R5]← [R5]+1

INC direct
INC 50 Increments the contents of memory location 50 by 1.

INC @Ri
INC @R0 Increments the contents of memory location using indirect addressing mode by 1.
M [[R0]]← M[[R0]]+1

INC DPTR Increments the 16 bits data pointer by 1:

[DPTR] ← [DPTR] +1

DEC A Decrements the contents of A by 1:

[A] ← [A] – 1

DEC Rn
DEC R5 Decrements the contents of register 5 by 1:
[R5] ← [R5] – 1

DEC direct
DEC 60 Decrements the contents of memory location 60 by 1.
M [60] ←M [60]–1

DEC @Ri
DEC @R0 Decrements the contents of memory location using indirect addressing mode by 1.
M [[R0]]←M [[R0]]–1
Logical Instructions:
ANL A, #data; AND the contents of A with immediate data.
This instruction AND the contents of an A with immediate data and stores the result in the A.

ANL A, Rn; AND the contents of A with contents of register Rn.

This instruction AND the contents of an A with contents of register Rn and stores the result in the A.

ANL A, direct; AND the contents of A with contents of memory using direct addressing.
This instruction AND the contents of an A with contents of memory using direct addressing mode and
stores the result in the A.

ANL A, @Ri; AND the contents of A with contents of memory using indirect addressing.
This instruction AND the contents of an A with contents of memory using indirect addressing mode and
stores the result in the A.

ANL direct,A; AND the contents of memory using direct addressing with the contents of A. This
instruction AND the contents of memory using direct addressing mode with the contents of an A and
stores the result in memory.

ANL direct, #data; AND the contents of memory using direct addressing with immediate data. This
instruction AND the contents of memory using direct addressing mode with immediate data.

ORL A, #data; OR the contents of A with immediate data.

This instruction OR the contents of A with immediate data and stores the result in the A.

ORL A, Rn; OR the contents of A with contents of register Rn.

This instruction OR the contents of an A with contents of register Rn and stores the result in the A.

ORL A, direct; OR the contents of A with contents of memory using direct addressing.
This instruction OR the contents of A with contents of memory using direct addressing mode and stores
the result in the A.

ORL A, @ Ri; OR the contents of A with contents of memory using indirect addressing.
This instruction OR the contents of an A with contents of memory using indirect addressing mode and
stores the result in the A.

ORL direct, A: OR the contents of memory using direct addressing with the contents of A.
This instruction OR the contents of memory using direct addressing mode with the contents of an A and
stores the result in memory.

ORL direct, #data: OR the contents of memory using direct addressing with immediate data. This
instruction OR the contents of memory using direct addressing mode with immediate data.

XRL A, #data: EX-OR the contents of A with immediate data.

This instruction Exclusive-OR the contents of an A with immediate data and stores the result in the A.

XRL A, Rn: EX-OR the contents of A with contents of register Rn.

This instruction Exclusive–OR the contents of an A with contents of register Rn and stores the result in
the A.
XRL A, direct: EX-OR the contents of A with contents of memory using direct addressing.
This instruction Exclusive–OR the contents of an A with contents of memory using direct addressing
mode and stores the result in the A.

XRL A, @Ri: EX-OR the contents of A with contents of memory using indirect addressing. This
instruction Exclusive-OR the contents of an A with contents of memory using indirect addressing mode
and stores the result in the A.

XRL direct, A: EX-OR the contents of memory using direct addressing with the contents of A. This
instruction EX-OR the contents of memory using direct addressing mode with the contents of A and
stores the result in memory.

XRL direct, #data: EX-OR the contents of memory using direct addressing with immediate data. This
instruction EX-OR the contents of memory using direct addressing mode with immediate data.

CPL A: Complement Contents of A This instruction performs logical inversion of the contents of A. It
changes 0’s to 1’s and 1’s to 0’s. It performs the NOT operation.

SWAP A: Swap the Upper and Lower Nibble of A This instruction interchanges the low and high order
nibbles of the A. The operation can also be thought of as a 4 bit rotate instruction. No flags are affected.

Rotate Instructions:
RL A Rotate left contents of A Rotate A left one place.
RR A Rotate right contents of A Rotate A right one place.
RLC A Rotate left including carry contents of A Rotate A left one place through carry.
RRC A Rotate right including carry contents of A Rotate A right one place through carry.

Branch (JUMP) Instructions:

Unconditional Jump Instructions:
LJMP addr16: LJMP causes an unconditional branch to the indicated address, by loading the program
counter with 16 bits address i.e. the second and third byte of the instruction respectively.

AJMP addr11: AJMP causes an unconditional branch to the indicated address, by loading the 11 bit
address to 0 to 10 bits of the program counter. The destination must therefore be within the same 2K
blocks.

SJMP rel: The branch destination is computed by adding the signed displacement to the contents of the
program counter. Therefore, it branches from 128 bytes preceding this instruction to 127 bytes following
it.

JMP Indirect: The contents of an A is added (8 bit unsigned) with 16 bit contents of data pointer and
this 16 bit is loaded to the program counter. Neither the A nor the data pointer is altered and no flags are
affected.

Compare and jump if not equal (CJNE , ,rel)

CJNE compares the magnitude of the first two operands, and branches if their values are not equal.
Branch address is computed by adding the signed displacement to the contents of Program Counter
(PC). The carry flag is set, if the unsigned integer value of is less than the unsigned integer value of ,
else the carry flag is cleared.

CJNE A, direct, rel:

CJNE A, #data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel

Decrement and jump if not zero (DJNZ)

DJNZ decrements the contents of the memory or register by 1, and if the resulting value is not zero, it
branches to the relative address indicated by the second operand. No flags are affected and the branch
destination is computed by adding the signed displacement value to the contents of the program counter.
DJNZ Rn,rel
DJNZ direct,rel

Jump if A is zero (JZ rel) If A is zero, branch to the address indicated; otherwise execute the next
instruction. The branch address is computed by adding the signed displacement to the contents of the
PC, after incrementing the PC twice. Flags are not affected.

Jump if A is not zero (JNZ rel) If A is not zero, branch to the address indicated; otherwise execute the
next instruction. The branch address is computed by adding the signed displacement to the contents of
the PC, after incrementing the PC twice. Flags are not affected.

Conditional Jump Instructions

Jump if carry is set (JC rel) If the carry flag is set, branch to the address indicated; otherwise execute
the next instruction. Flags are not affected. The branch destination is computed by adding the signed
displacement to the contents of PC, after incrementing the contents of PC by 2.

Jump if carry is not set (JNC rel) If the carry flag is not set, branch to the address indicated; otherwise
execute the next instruction. Flags are not affected. The branch destination is computed by adding the
signed displacement to the contents of PC, after incrementing the contents of PC by 2.

Subroutine CALL and RET instructions

CALL Instructions
The 8051 provides two types of CALL instructions.
LCALL addr16 This instruction is called long call instruction and it unconditionally calls a subroutine
located at the indicated address. This is a 3 byte instruction. The instruction increments program counter
by 3 and generates the address of the next instruction and saves this address in a stack. The program
counter is then loaded with the 16 bit address of the LCALL instruction. Flags are not affected.

ACALL addr11 This instruction is called absolute call instruction and it unconditionally calls a
subroutine located at the indicated address. This is a 2 byte instruction. The instruction increments the
program counter by 2, and generates the address of the next instruction and saves this address in a stack.
The program counter (PC10–0) is then loaded with an 11 bit address of the LCALL instruction. Flags
are not affected.

RET Instructions
The 8051 provides two types of RET instruction.
RET: Return from subroutine RET instruction pops the top two contents of the stack and is loaded to
PC. It decrements the stack pointer by 2 and flags are not affected.

RETI: Return from interrupt RETI instruction pops the top two contents of the stack and is loaded to
PC. It decrements the stack pointer by 2 and flags are not affected. It restores the interrupt logic at the
same priority level to accept the request from I/O devices.

Bit Manipulation Instruction

The 8051 supports a single bit operation. The internal RAM contains 128 addressable bits (20H to 2FH)
00 to 7FH. SFR supports 128 addressable bits and all the I/O ports are bit addressable. Each I/O line can
be treated as a separate single bit port. The 8051 provides bit manipulation instructions to perform
operations such as and, or, set, clear, complement and also conditional bit manipulation jump
instructions.
And
AND contents of carry flag with Boolean value of the source bit or with complemented Boolean value
of the source bit.
OR
OR contents of carry flag with Boolean value of the source bit or with complemented Boolean value of
the source bit.
CLR bit
The indicated bit is cleared. No flags are affected. CLR can operate on the carry flag or any directly
addressable bit.

CPL bit
Bit variable specified is complemented. Mentioned bit, which had been a one, is changed to zero and
vice-versa.

Bit Manipulation Branch Instructions

It checks the condition of the bit; if the condition is satisfied then it jumps to the address indicated;
otherwise executes the next instruction. Instruction increments the program counter by 3 and then
branch address is computed by adding the signed displacement to the contents of PC.
JB bit, rel: Jump if direct bit is set
JNB bit, rel: Jump if direct bit is not set
JBC bit, rel: Jump if direct bit is set and clear bit.
ASSEMBLER DIRECTIVES

In assembly language programming, the assembler directives instruct the assembler to

• process subsequent assembly language instructions
• define program constants
• reserve space for variables
Each assembler uses various directives. The following are the widely used 8051 assembler directives.

ORG (origin)
The ORG directive is used to indicate the starting address. It can be used only when the program counter
needs to be changed. The number that comes after ORG can be either in hex or in decimal.
Example: ORG 2000H ; Set program counter 2000

EQU and SET

The EQU and SET directives assign numerical value or register name to the specified symbol name.
EQU is used to define a constant without storing information in the memory. The symbol defined with
EQU should not be redefined, whereas the SET directive allows redefinition of symbols at a later stage.

Pointer SET R1 ; use R1 as pointer

Counter EQU R3 ; use R3 as counter
N EQU 35H
MOV R3, #N ; 35h is stored in R3
DB (define byte)
The DB directive is used to define an 8 bit data. DB directive initialises memory with 8 bit values. The
numbers can be in decimal, binary, hex or in ASCII formats. For decimal, the ‘D’ after the decimal
number is optional, but for binary and hexadecimal, ‘B’ and ‘H’ are required. For ASCII, the number is
written in quotation marks (‘ ’).

DATA1: DB 40H ; hex

DATA2: DB 01011100B ; binary
DATA3: DB 48 ; decimal
DATA4: DB 'HELLO’ ; ASCII
END
The END directive signals the end of the assembly module. It indicates the end of the program to the
assembler. Any text in the assembly file that appears after the END directive is ignored. If the END
statement is missing, the assembler will generate an error message.

Write a program to add the values of locations 50H and 51H and store the result in locations 52H
and 53H.
ALGORITHM
Step 1: Load the memory contents 50H into A
Step 2: ADD the memory contents 51H with contents of A
Step 3: Store the contents of A in 52H
Step 4: Store the contents of the carry flag in 53H.
The program is as follows
ORG 0000H ; Set program counter 0000H
MOV A,50H ; Load the contents of memory location 50H into A
ADD A,51H ; Add the contents of memory location 51H with contents of A
MOV 52H,A ; Save the least significant byte of the result in location 52H
MOV A, #00 ; Load 00H into A
ADDC A, #00 ; Add the immediate data and the contents of carry flag to A
MOV 53H,A ; Save the most significant byte of the result in location 53
END
Write a program to subtract the values of locations 51H from 50H and store the result in location
52H.
If the result is positive, store 00H, else store 01H in 53H.
ALGORITHM
Step 1: Load the memory contents 50H into A A
Step 2: Clear the carry flag
Step 3: Subtract the memory contents 51H from the contents of A A
Step 4: Store the contents of A A in 52H
Step 5: Check the contents of the carry flag, if the contents of the carry flag is 0 (result is positive) store
00H, else if the contents of the carry flag is 1 (result is negative) store 01H in 53H.
ORG 0000H ; Set program counter 0000H
MOV A,50H ; Load the contents of memory location 50H into A
CLR C ; Clear the borrow fl ag
SUBB A,51H ; Subtract the contents of memory location 51H from content of A
MOV 52H,A ; Store the result in location 52H
MOV A,#00 ; Load 00H into A
ADDC A,#00 ; Add the immediate data and the contents of carry flag to A
MOV 53H,A ; Save the most significant byte of the result in location 53
END

Write a program to clear 10 RAM locations starting at RAM address 1000H.

ORG 0000H ; Set program counter 0000H
MOV DPTR, #1000H ; Copy address 1000H to DPTR
CLR A ; Clear A
MOV R6, #0AH ; Load 0AH to R6
again: MOVX @DPTR,A ; Clear RAM location pointed by DPTR
INC DPTR ; Increment DPTR
DJNZ R6, again ; Loop until counter R6 = 0
END
Write a program to clear 10 RAM locations starting at RAM address 10H.
ORG 0000H ; Set program counter 0000H
MOV R0, #10H ; Copy address 10H to R0
CLR A ; Clear A
MOV R6,#0AH ; Load 0AH to R6
again: MOV @R0,A ; Clear RAM location pointed by R0
INC R0 ; Increment R0
DJNZ R6, again ; Loop until counter R6 = 0
END
Write a program to compute 1 + 2 + …. + N (say 15) and save the sum at 70H
ORG 0000H ; Set program counter 0000H
N EQU 15
MOV R0, #00 ; Clear R0
CLR A ; Clear A
again: INC R0 ; Increment R0
ADD A, R0 ; Add the contents of R0 with contents of A
CJNE R0, #N, again ; Loop until counter, R0 = N
MOV 70H,A ; Save the result in location 70H
END
Write a program to multiply two 8 bit numbers stored at locations 70H and 71H and store the
result at memory locations 52H and 53H. Assume that the least significant byte of the result is
stored in a low address.
ORG 0000H ; Set program counter 0000H
MOV A,70H ; Load the contents of memory location 70H into A
MOV B,71H ; Load the contents of memory location 71H into B
MUL AB ; Perform multiplication
MOV 52H,A ; Save the least significant byte of the result in location 52H
MOV 53H,B ; Save the most significant byte of the result in location 53
END

Write a program to divide contents of 70H from contents of 71H (Assume contents of 70H is
greater or equal to contents of 71H). Store the remainder at memory location 53H and the
quotient at memory location 52H.
ORG 0000H ; Set program counter 0000H
MOV A,70H ; Load the contents of memory location 70H into A
MOV B,71H ; Load the contents of memory location 71H into B
DIV AB ; Perform division
MOV 52H, A ; Save the quotient in location 52H
MOV 53H, B ; Save the remainder in location 53H
END
Time delay Calculations:
Write a program to generate a delay of 1 msec. Assume that the oscillator frequency is 12 MHz.

Oscillator period = 1/12MHz

1 Machine cycle = (1/12MHz) X 12 = 1µsec

MOV R1, #125 (Decimal) (COUNT) 2 Machine cycles

START: PUSH E0 (H) 2 Machine cycles
POP E0 (H) 2 Machine cycles
NOP 1 Machine cycles
NOP 1 Machine cycles
DJNZ R1, START 2 Machine cycles

Microcontroller will take 8 Machine cycles to execute the internal loop for ONE time.
So, it takes 8µsec time.
For 1msec delay the internal loop must be executed COUNT no. of times.
1msec = 8 µsec X COUNT.
COUNT = 1msec / 8 µsec.
COUNT = 125 (Decimal)

TIME DELAY = 2 + (2 + 2 + 1 + 1 + 2) * 1 * 10 -6 *125.

This is an approximate calculation.
8051 Interrupts and Timers/Counters:

BASICS OF INTERRUPTS:
During program execution if peripheral devices need service from the microcontroller, the device will
generate an interrupt and get the service from the microcontroller. When peripheral devices activate
the interrupt signal, the processor branches to a program called interrupt service routine. After
executing the interrupt service routine the processor returns to the main program.

Steps taken by processor while processing an interrupt:

1. It completes the execution of the current instruction.

2. PSW is pushed to the stack.
3. PC content is pushed to stack.
4. Interrupt flag is reset.
5. The PC is loaded with an ISR address.

ISR will always end with RETI instruction. The execution of RETI instruction results in the following.
1. POP the current stack top to the PC.
2. POP the current stack top to PSW.

Classification of interrupts:

1. External and internal interrupts

External interrupts are those initiated by peripheral devices through the external pins of the
microcontroller.
Internal interrupts are those activated by the internal peripherals of the microcontroller like timers,
serial controller etc.)
2. Maskable and non-maskable interrupts
The category of interrupts which can be disabled by the processor using the program is called
maskable interrupts.
Non-maskable interrupts are those categories by which the programmer cannot disable it using the
program.
3. Vectored and non-vectored interrupt
Starting address of the ISR is called an interrupt vector. In vectored interrupts the starting address is
predefined. In non-vectored interrupts, the starting address is provided by the peripheral as follows.
·Microcontroller receives an interrupt request from an external device.
· Controller sends an acknowledgement (INTA) after completing the execution of the current
instruction.
· The peripheral device sends the interrupt vector to the microcontroller.
8051 INTERRUPT STRUCTURE:
8051 has five interrupts. They are maskable and vectored interrupts. Out of these
five, two are external interrupts and three are internal interrupts.

Interrupt source Type Vector address Priority

External interrupt 0 External 0003 Highest

Timer 0 interrupt Internal 000B

External interrupt 1 External 0013

Timer 1 interrupt Internal 001B

Serial interrupt Internal 0023 Lowest

8051 makes use of two registers to deal with interrupts.

IE Register

This is an 8 bit register used for enabling or disabling the interrupts. The structure of IE register is
shown below.
IP Register

This is an 8 bit register used for setting the priority of the interrupts.
TIMERS AND COUNTERS:
Timers/Counters are used generally for
· Time reference
· Creating delay
· Waveform properties measurement
· Periodic interrupt generation
· Waveform generation
8051 has two timers, Timer 0 and Timer 1.

Timer in 8051 is used as a timer, counter and baud rate generator. Timer always counts up irrespective
of whether it is used as timer, counter, or baud rate generator: Timer is always incremented by the
microcontroller. The time taken to count one digit up is based on master clock frequency.
If Master CLK=12 MHz,
Timer Clock frequency = Master CLK/12 = 1 MHz Timer Clock Period = 1micro second

This indicates that one increment in count will take 1 micro second.

The two timers in 8051 share two SFRs (TMOD and TCON) which control the timers, and each timer also has
two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1).

The following are timer related SFRs in 8051.

SFR Name Description SFR Address

TH0 Timer 0 High Byte 8Ch

TL0 Timer 0 Low Byte 8Ah

TH1 Timer 1 High Byte 8Dh

TL1 Timer 1 Low Byte 8Bh

TCON Timer Control 88h

TMOD Timer Mode 89h

Timer/ Counter Control Logic:

TIMER MODES:
Timers can operate in four different modes. They are as follows
Timer Mode-0: In this mode, the timer is used as a 13-bit UP counter as follows.

Fig. Operation of Timer on Mode-0

The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count. Upper 3 bits of TLX are
ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is
generated. The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0, the
counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the counter is
controlled by input. This mode is useful to measure the width of a given pulse fed to input.

Timer Mode-1: This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit
mode.

Fig: Operation of Timer in Mode 1

Timer Mode-2: (Auto-Reload Mode): This is a 8 bit counter/timer operation. Counting is
performed in TLX while THX stores a constant value. In this mode when the timer
overflows i.e. TLX becomes FFH, it is fed with the value stored in THX. For example if
we load THX with 50H then the timer in mode 2 will count from 50H to FFH. After that
50H is again reloaded. This mode is useful in applications like fixed time sampling.
 Fig: Operation of Timer in Mode 2

Timer Mode-3: Timer 1 in mode-3 simply holds its count. The effect is the same as setting TR1=0. Timer0 in
mode-3 establishes TL0 and TH0 as two separate counters.

Fig: Operation of Timer in Mode 3

Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and
TF0 are available to Timer-0 lower 8 bits(TL0).

PROGRAMMING 8051 TIMERS IN ASSEMBLY

In order to program 8051 timers, it is important to know the calculation of the initial count value to be stored in
the timer register. The calculations are as follows.
In any mode, Timer Clock period = 1/Timer Clock Frequency.
= 1/(Master Clock Frequency/12)
a. Mode 1 (16 bit timer/counter)
Value to be loaded in decimal = 65536 – (Delay Required/Timer clock period) Convert the answer into
hexadecimal and load onto THx and TLx register. (65536D = FFFFH+1)
b. Mode 0 (13 bit timer/counter)
Value to be loaded in decimal = 8192 – (Delay Required/Timer clock period) Convert the answer into
hexadecimal and load onto THx and TLx register. (8192D = 1FFFH+1)
c. Mode 2 (8 bit auto reload)
Value to be loaded in decimal = 256 – (Delay Required/Timer clock period) Convert the answer into
hexadecimal and load onto THx register. Upon starting the timer this value from THx will be reloaded to TLx
register.
(256D = FFH+1)

Steps for programming timers in 8051

Mode 1:
· Load the TMOD value register indicating which timer (0 or 1) is to be used and which timer mode is
selected.
· Load registers TL and TH with initial count values.
· Start the timer by the instruction “SETB TR0” for timer 0 and “SETB TR1” for timer 1.
· Keep monitoring the timer flag (TF) with the “JNB TFx, target” instruction to see if it is raised. Get out of
the loop when TF becomes high.
· Stop the timer with the instructions “CLR TR0” or “CLR TR1”, for timer 0 and timer 1, respectively.
· Clear the TF flag for the next round with the instruction “CLR TF0” or “CLR TF1”, for timer 0 and timer 1,
respectively.
· Go back to step 2 to load TH and TL again.
Mode 0:
The programming techniques mentioned here are also applicable to counter/timer mode 0. The only difference
is in the number of bits of the initialization value.
Mode 2:
· Load the TMOD value register indicating which timer (0 or 1) is to be used; select timer mode 2.
· Load TH register with the initial count value. As it is an 8-bit timer, the valid range is from 00 to FFH.
· Start the timer.
· Keep monitoring the timer flag (TFx) with the “JNB TFx, target” instruction to see if it is raised. Get out
of the loop when TFx goes high.
· Clear the TFx flag.
· Go back to step 4, since mode 2 is auto-reload.

1. Write a program to continuously generate a square wave of 2 kHz frequency on pin P1.5 using timer 1.
Assume the crystal oscillator frequency to be 12 MHz.
The period of the square wave is T = 1/(2 kHz) = 500 µs.
Each half pulse = 250 µs.
The value n for 250 µs is: 250 µs /1 µs = 250
65536 - 250 = FF06H.
TL = 06H and TH = 0FFH.
MOV TMOD,#10 ;Timer 1, mode 1
AGAIN: MOV TL1,#06H ;TL0 = 06H
MOV TH1,#0FFH ;TH0 = FFH
SETB TR1 ;Start timer 1
BACK: JNB TF1,BACK ;Stay until timer rolls over
CLR TR1 ;Stop timer 1
CPL P1.5 ;Complement P1.5 to get Hi, Lo
CLR TF1 ;Clear timer flag 1
SJMP AGAIN ;Reload timer
2. Write a program segment that uses timer 1 in mode 2 to toggle P1.0 once whenever the counter reaches
a count of 100. Assume the timer clock is taken from external source P3.5 (T1).
The TMOD value is 60H
The initialization value to be loaded into TH1 is 256 - 100 = 156 = 9CH
MOV TMOD, #60H ; Counter1, mode 2, C/T’= 1
MOV TH1, #9CH ; Counting 100 pulses
SETB P3.5 ; Make T1 input
SETB TR1 ; Start timer 1
BACK: JNB TF1,BACK ; Keep doing it if TF1 = 0
CPL P1.0 ;Toggle port bit
CLR TF1 ;Clear timer overflow flag
SJMP BACK ;Keep doing it