Control Systems Design Overview
Control Systems Design Overview
© H. T. Hoang - HCMUT 1
Chapter 5
DESIGN OF CONTINUOUS
CONTROL SYSTEMS
© H. T. Hoang - HCMUT 2
Content
Introduction
Effect of controllers on system performance
Control systems design using the root locus method
Control systems design in the frequency domain
Design of PID controllers
Control systems design in state-space
Design of state estimators
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Introduction
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Introduction to design process
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Series compensator
The controller is connected in series with the plant.
R(s) Y(s)
+ GC(s) G(s)
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State feedback control
All the states of the system are fed back to calculate the control
rule.
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Effects of controller on system
performance
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Effects of the addition of poles
The addition of a pole (in the left-half s-plane) to the open-
loop transfer function has the effect of pushing the root locus
to the right, tending to lower the system’s relative stability and
to slow down the settling of the response.
Im s Im s Im s
Re s Re s Re s
K K K
G (s) G(s) G (s)
s p1 ( s p1 )( s p2 ) ( s p1 )( s p2 )( s p3)
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Effects of the addition of zeros
Re s Re s Re s
K K ( s z1 )( s z2 )
G (s) G(s)
( s p1 )( s p2 )( s p3) ( s p1 )( s p2 )( s p3)
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Effects of lead compensators
Transfer function:
1 Ts
GC ( s ) K C ( 1)
1 Ts
Frequency response:
1 Tj
GC ( j ) K C
1 Tj
Characteristics of the Bode plots:
1 1
max sin
1
1
max
T
L ( max ) 20 lg K C 10 lg
The lead compensators improve
the transient response (POT, ts,..)
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Lead compensator implementation
Lead compensator transfer function:
U ( s ) R2 R4 1 R1C1s 1 Ts
KC ( 1 R1C1 R2C2 )
E ( s ) R1 R3 1 R2C2 s 1 Ts
E(s)
U(s)
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Effects of lag compensators
Transfer function:
1 Ts
GC ( s ) K C ( 1)
1 Ts
Frequency response:
1 Tj
GC ( j ) K C
1 Tj
Characteristics of the Bode plots:
1 1
min sin
1
1
min
T
L (min ) 20 lg K C 10 lg
The lag compensators
reduce the steady-state error.
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Lag compensator implementation
Lag compensator transfer function:
U ( s ) R2 R4 1 R1C1s 1 Ts
KC ( 1 R1C1 R2C2 )
E ( s ) R1 R3 1 R2C2 s 1 Ts
E(s)
U(s)
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Effects of lead-lag compensators
1 1T1s 1 2T2 s
Transfer function: GC ( s) KC (1 1, 2 1)
1 T1s 1 T2 s
Bode diagram
E(s)
U(s)
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Effects of proportional controller (P)
Transfer function: GC ( s) K P
Increasing proportional gain leads to decreasing steady-state
error, however, the system become less stable, and the POT
increases.
y(t)
Ex: response of a
proportional control
system whose
plant has the
transfer function
below:
10
G ( s)
( s 2)( s 3)
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Effects of proportional derivative controller (PD)
The PD controller is a
special case of phase lead
compensator, the
maximum phase lead is
max=900 at the frequency
max=+.
The PD controller speed up
the response of the system,
however it also makes the
system more sensitive to
high frequency noise.
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Effects of proportional derivative controller (PD)
Note: The larger the derivative constant, the faster the
response of the system.
y(t)
unompensated
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PD controller implementation
PD controller transfer function:
U ( s ) R2 R4
(1 R1C1s ) K P K D s
E ( s ) R1 R3
E(s)
U(s)
© H. T. Hoang - HCMUT 20
Effects of proportional integral controller (PI)
Transfer function: Bode diagram
KI 1
GC ( s ) K P K P (1 )
s TI s
The PI controller is a
special case of phase lag
compensator, the minimum
phase lag is min= 900 at
the frequency min=0.
PI controllers eliminate
steady state error to step
input, however it can
increase POT and settling
time.
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Effects of proportional integral controller (PI)
Note: The larger the integral constant, the larger the POT
of response of the system.
y(t)
uncompensated
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PI controller implementation
PI controller transfer function:
U ( s ) R2 R4 R2C2 s 1 KI
KP
E ( s ) R1 R3 R2C2 s s
E(s)
U(s)
© H. T. Hoang - HCMUT 23
Effects of proportional integral controller (PID)
Transfer function:
Bode diagram
KI
GC ( s ) K P KDs
s
1
GC ( s ) K P (1 TD s )
TI s
1
GC ( s ) K P 1 1 TD 2 s
TI 1s
E(s)
U(s)
y(t)
Uncompensated
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Control systems design
using the root locus method
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Procedure for designing lead compensator using the root locus
s (1 / T )
Lead compensator: GC ( s ) K C ( 1)
s (1 / T )
*
Step 1: Determine the dominant poles 1, 2 from desired
s
transient response specification:
Overshoot (POT)
s1*, 2 n jn 1 2
Settling time ts n
Step 2: Determine the deficiency angle so that the dominant
poles s1*, 2 lie on the root locus of the compensated system:
n m
* 180 0 arg( s1* pi ) arg( s1* z i )
i 1 i 1
GC ( s )G ( s ) s s* 1
1
© H. T. Hoang - HCMUT 29
Example of designing a lead compensator using RL
R(s) 50 Y(s)
+ GC(s)
s ( s 5)
Solution:
Because the design objective is to improve the transient
response, we need to design a lead compensator:
s (1 / T )
GC ( s ) K C ( 1)
s (1 / T )
© H. T. Hoang - HCMUT 30
Example of designing a lead compensator using RL (cont’)
4 4
t qñ 0,5 n n 11,4
n 0,5
Chose n 15
The dominant poles are:
s1*, 2 n j n 1 2 0,707 15 j15 1 0,707 2
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Example of designing a lead compensator using RL (cont’)
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Example of designing a lead compensator using RL (cont’)
B A C 1 Re s
O
10,5 5
OPˆ x * OPˆ x *
sin sin
2 2 2 2
OB OP 28,12 OC OP 8,0
OPˆ x
*
OPˆ x
*
sin sin
2 2 2 2
s8
GC ( s ) K C
s 28
© H. T. Hoang - HCMUT 33
Example of designing a lead compensator using RL (cont’)
GC ( s )G ( s ) s s* 1
10,5 j10,5 8 50
KC . 1
10,5 j10,5 28 (10,5 j10,5)(10,5 j10,5 5)
10,79 50
KC 1
20,41 15 11,85
K C 6,7
Conclusion: The transfer function of the lead compensator is:
s8
GC ( s ) 6,7
s 28
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Root locus of the system
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Transient response of the system
y(t)
uncompensated
compensated
R(s) Y(s)
+ GC(s) G(s)
20
G(s) =
s( s + 3)
Objective: Design the phase lead compensator GC(s) so that
the compensated system has a pair of complex poles with
0.8 and n 4
Calculate the POT and ts before and after compensation.
Simulate the system to verify the design.
© H. T. Hoang - HCMUT 37
Exercise
R(s) Y(s)
+ GC(s) G(s)
5
G(s) =
s( s + 2)( s + 8)
Objective: Design the phase lead compensator GC(s) so that
the compensated system has a pair of complex poles with
0.8 and n 3
Solution:
© H. T. Hoang - HCMUT 38
Procedure for designing lag compensator using the root locus
s (1 / T )
Lag compensator: GC ( s) KC ( 1)
s (1 / T )
Step 1: Determine to meet the steady-state error requirement:
KP KV Ka
* or * or *
KP KV Ka
1 *
Step 2: Chose the zero of the lag compensator: Re( s1, 2 )
T
1 1
Step 3: Calculate the pole of the compensator: .
T T
© H. T. Hoang - HCMUT 39
Example of designing a lag compensator using RL
R(s) 10 Y(s)
+ GC(s)
s( s 3)( s 4)
Solution:
The compensator to be design is a lag compensator:
s (1 / T )
GC ( s) KC ( 1)
s (1 / T )
© H. T. Hoang - HCMUT 40
Example of designing a lag compensator using RL (cont’)
Step 1: Determine
The velocity constant of uncompensated system :
10
KV lim sG ( s) lim s 0.83
s 0 s 0 s ( s 3)( s 4)
0,017
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Example of designing a lag compensator using RL (cont’)
GC ( s )G ( s ) s s* 1
s 0,1 10
KC . 1
s 0,0017 s( s 3)( s 4) s 1 j
( 1 j 0,1) 10
KC . 1
( 1 j 0,0017) ( 1 j )( 1 j 3)( 1 j 4)
KC 1,0042 1
s 0,1
GC ( s )
s 0,0017
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Root locus of the system
y(t)
uncompensated
compensated
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Exercise
R(s) Y(s)
+ GC(s) G(s)
12
G(s) =
s( s + 2)( s + 8)
Objective: Design the phase lag compensator GC(s) so that
the system after compensation has steady error to ramp input
satisfying ess 0.05
.
Solution:
© H. T. Hoang - HCMUT 46
Exercise
© H. T. Hoang - HCMUT 47
Procedure for designing lead lag compensator using the RL
phase phase
lead lag
Step 1: Design the lead compensator GC1(s) to satisfy the
transient response performances.
© H. T. Hoang - HCMUT 48
Example of designing a lead lag compensator using RL
R(s) 4 Y(s)
+ GC(s)
s( s 0.5)
Solution
The compensator to be designed is a lead lag compensator
because the design objective is to improve the transient
response and to reduce the steady-state error.
GC ( s) GC1 ( s)GC 2 ( s)
© H. T. Hoang - HCMUT 49
Example of designing a lead lag compensator using RL (cont’)
s 0,5 4
K C1 . 1
s 5 s ( s 0,5) s 2,5 j 4,33
K C1 6,25
s 0,5
GC1 ( s ) 6,25
s5
KV* 80
KV 5 1
*
KV 80 16
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Example of designing a lead lag compensator using RL (cont’)
© H. T. Hoang - HCMUT 54
Example of designing a lead lag compensator using RL (cont’)
( s 0,5)( s 0,16)
Final result: GC ( s ) GC1 ( s )GC 2 ( s ) 6,31
( s 5)( s 0,01)
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Exercise
R(s) 10 Y(s)
+ GC(s)
s ( s 2)
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Control system design in
frequency domain
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Procedure for designing lead compensators in frequency domain
Ts 1
The lead compensator: GC ( s ) KC ( 1)
Ts 1
Step 1: Determine KC to meet the steady-state error requirement:
K C K P* / K P or K C KV* / KV or K C K a* / K a
Step 2: Let G1(s)=KCG(s). Plot the Bode diagram of G1(s)
Step 3: Determine the gain crossover frequency of G1(s):
L1 (C ) 0 or G1 ( j C ) 1
Step 4: Determine the phase margin of G1(s) (phase margin
of uncompensated system): M 180 1 ( C )
Step 5: Determine the necessary phase lead angle to be
added to the system: M * M
max
M * is the desired phase margin, 50 200
© H. T. Hoang - HCMUT 58
Procedure for designing lead compensators in frequency domain
1 sin max
Step 6: Calculate :
1 sin max
Step 7: Determine the new gain crossover frequency (of
the compensated open-loop system) using the conditions:
L1(C* ) 10lg or G1 ( jC* ) 1 /
1
Step 8: Calculate the time constant T: T
C*
Step 9: Check if the compensated system satisfies the gain
margin? If not, repeat the design procedure from step 5.
Note: It is possible to determine C (step 3), M (step 4) and
*C (step 7) by using Bode diagram instead of using analytic
calculation.
© H. T. Hoang - HCMUT 59
Design lead compensator in frequency domain - Example
R(s)
GC(s) 4 Y(s)
+
s( s 2)
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Design lead compensator in frequency domain – Example (cont’)
Step 1: Determine KC
The velocity constant of the uncompensated system:
4
KV lim sG ( s ) lim s 2
s 0 s 0 s ( s 2)
The desired velocity constant: KV* 20
KV* 20
KC K C 10
KV 2
4
Step 2: Denote G1 ( s ) K C G ( s ) 10.
s ( s 2)
20
G1 ( s )
s (0,5s 1)
Draw the Bode diagram of G1(s)
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Design lead compensator in frequency domain – Example (cont’)
-20dB/dec
26
-40dB/dec
2 c=6
M
-160
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Design lead compensator in frequency domain – Example (cont’)
max 37 0
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Design lead compensator in frequency domain – Example (cont’)
Step 6: Calculate
1 sin max 1 sin 37 0
4
1 sin max 1 sin 37 0
Step 7: Determine the new gain crossover frequency using
Bode plot L ( ) 10 lg 10 lg 4 6dB
1 C
-20dB/dec
-40dB/dec
+20dB/dec
-20dB/dec
-6
-40dB/dec
-40dB/dec
M *
M
-160
© H. T. Hoang - HCMUT 65
Design lead compensator in frequency domain – Example (cont’)
© H. T. Hoang - HCMUT 66
Design lead compensator in frequency domain – Example 2
R(s) Y(s)
+ GC(s) G(s)
20e-0.01s
G(s) =
s( s + 4)
Solution:
© H. T. Hoang - HCMUT 67
Design lead compensator in frequency domain – Example 3
R(s) Y(s)
+ GC(s) G(s)
16e 0.005 s
G(s)
( s 2)( s 5)
Objective: Design the compensator GC(s) so that the
compensated system has: M * 600 , GM * 10dB and
steady-state error to unit step input ess* 0.05;
Solution:
© H. T. Hoang - HCMUT 68
Procedure for designing lag compensators in frequency domain
Ts 1
The lag compensator: GC ( s ) K C ( 1)
Ts 1
Step 1: Determine KC to meet the steady-state error requirement:
K C K P* / K P or K C KV* / KV or K C K a* / K a
Step 2: Let G1(s)=KCG(s). Plot the Bode diagram of G1(s)
Step 3: Determine the new gain crossover frequency C*
satisfying the following condition:
1 (C* ) 180 M *
*
M is the desired phase margin, 50 20 0
Step 4: Calculate using the condition:
1
L1 ( ) 20lg
* or G1 ( j )
*
C C
© H. T. Hoang - HCMUT 69
Procedure for designing lag compensators in frequency domain
(
Note: It is possible to determine 1 C , C (step 3), L1 (C* )
*
) *
© H. T. Hoang - HCMUT 70
Design lag compensator in frequency domain – Example
R(s)
GC(s) 1 Y(s)
+
s( s 1)(0.5s 1)
© H. T. Hoang - HCMUT 71
Design lag compensator in frequency domain – Example (cont’)
Step 1: Determine KC
The velocity constant of the uncompensated system:
1
KV lim sG ( s ) lim s 1
s 0 s 0 s( s 1)(0.5s 1)
The desired velocity constant: KV* 5
KV*
KC 5
KV
Step 2: Denote G1 ( s ) K C G ( s )
5
G1 ( s )
s ( s 1)(0.5s 1)
Draw the Bode diagram of G1(s)
© H. T. Hoang - HCMUT 72
Design lag compensator in frequency domain – Example (cont’)
-20dB/dec
14 -40dB/dec
-60dB/dec
1 2
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Design lag compensator in frequency domain – Example (cont’)
-20dB/dec
L1(’c)
14 -40dB/dec GM*
L’(’)
-60dB/dec
-135
© H. T. Hoang - HCMUT 76
Design lag compensator in frequency domain – Example 2
R(s) Y(s)
+ GC(s) G(s)
20e-0.2 s
G(s) =
s( s + 4)
Solution:
© H. T. Hoang - HCMUT 77
Design lag compensator in frequency domain – Example 3
R(s) Y(s)
+ GC(s) G(s)
16e 0.01s
G(s)
( s 2)( s 5) 2
Objective: Design the compensator GC(s) so that the
compensated system has: M * 600 , GM * 10dB and
steady-state error to unit step input ess* 0.05;
Solution:
© H. T. Hoang - HCMUT 78
Comparison of phase lead and phase lag compensator
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Zeigler Nichols method 1
Determine the PID parameters based on the step response of
the open-loop system.
u(t) y(t)
Plant
y(t)
T1 T2
© H. T. Hoang - HCMUT 81
Zeigler Nichols method 1 (cont’)
R(s) Y(s)
+ PID Plant
1
PID controller: GC ( s ) K P 1 TD s
TI s
Controller KP TI TD
P T2/(T1K) 0
PI 0.9T2/(T1K) 3.3T1 0
PID 1.2T2/(T1K) 2T1 0.5T1
© H. T. Hoang - HCMUT 82
Zeigler Nichols method 1 – Example
Problem: Design a PID y(t)
controller to control a furnace
providing the open-loop
characteristic of the furnace 150
obtained from a experiment
beside. t (min)
K 150
8 24
T1 8 min 480 sec
T2 24 min 1440 sec
T2 1440 1
K P 1.2 1.2 0.024 GPID ( s ) 0.0241 240s
T1K 480 150 960s
TI 2T1 2 480 960 sec
© H. T. Hoang - HCMUT 83
Zeigler Nichols method 2
Determine the PID parameters based on the response of the
closed-loop system at the stability boundary.
+ KKcr Plant
y(t)
Tcr
t
© H. T. Hoang - HCMUT 84
Zeigler Nichols method 2 (cont’)
R(s) Y(s)
+ PID Plant
1
PID controller: GC ( s ) K P 1 TD s
TI s
Controller KP TI TD
P 0.5Kcr 0
PI 0.45Kcr 0.83Tcr 0
PID 0.6Kcr 0.5Tcr 0.125Tcr
© H. T. Hoang - HCMUT 85
Zeigler Nichols method 2 – Example
Problem: Design a PID controller to control the angle position
of a DC motor, providing that by experiment the critical gain of
the system is 20 and the critical cycle is T= 1 sec.
Solution:
According to the given data:
K cr 20
Tcr 1 sec
Applying Zeigler – Nichols method 2:
K P 0.6 K cr 0.6 20 12
1
GPID ( s ) 121 0.5s
TI 0.5Tcr 0.5 1 0.5 sec 0.125s
TD 0.125Tcr 0.125 1 0.125 sec
© H. T. Hoang - HCMUT 86
Analytical method for designing PID controller
© H. T. Hoang - HCMUT 87
Analytical method for designing PID controller
© H. T. Hoang - HCMUT 89
Analytical method for designing PID controller (cont’)
100
Conclusion: GC ( s ) 12,64 1,54 s
s
© H. T. Hoang - HCMUT 90
Exercise
Steady-
Para- Settling
Rise time POT state Stability
meter time
error
Small
KP Decrease Increase Decrease Degrade
change
KI Decrease Increase Increase Eliminate Degrade
Minor Improve if
KD Decrease Decrease No effect
change KD small
© H. T. Hoang - HCMUT 92
Manual tuning of PID controllers (cont.)
A procedure for manual tuning of PID controllers:
1. Set KI and KD to 0, gradually increase KP to the critical gain
Kcr (i.e. the gain makes the closed-loop system oscilate)
2. Set KP Kcr /2
3. Gradually increase KI until the steady-state error is
eliminated in a sufficient time for the process (Note that too
much KI will cause instability).
4. Increase KD if needed to reduce POT and settling time (Note
that too much KD will cause excessive response and
overshoot)
5. Fine tuning of Kp, Ki and Kd to meet the desired
perfomances
© H. T. Hoang - HCMUT 93
Control systems design in state-space
using pole placement method
© H. T. Hoang - HCMUT 94
Controllability
x (t ) Ax(t ) Bu (t )
Consider a system:
y (t ) Cx(t )
The system is complete state controllable if there exists an
unconstrained control law u(t) that can drive the system from
an initial state x(t0) to a arbitrarily final state x(tf) in a finite
time interval t0 t tf . Qualitatively, the system is state
controllable if each state variable can be influenced by the
input.
y(t)
System:
x (t ) Ax(t ) Bu (t )
y (t ) Cx (t )
Controllability matrix
C [ B AB A2 B An1 B]
© H. T. Hoang - HCMUT 96
Controllability – Example
x (t ) Ax(t ) Bu (t )
Consider a system
y (t ) Cx(t )
where: 0 1 5
A B C 1 3
2 3 2
Evaluate the controllability of the system.
© H. T. Hoang - HCMUT 97
State feedback control
r(t) u(t) x(t) y(t)
+
x (t ) Ax (t ) Bu (t ) C
0 1 0 0
A 0 0 1 B 3 C 0 0 1
4 7 3 1
Determine the state feedback controller u (t ) r (t ) Kx(t )
so that the closed-loop system has complex poles with
0,6;n 10 and the third pole at 20.
x (t ) Ax(t ) Bu (t )
Consider a system:
y (t ) Cx(t )
The system is complete state observable if given the control
law u(t) and the output signal y(t) in a finite time interval
t0 t tf , it is possible to determine the initial states x(t0).
Qualitatively, the system is state observable if all state variable
x(t) influences the output y(t).
y(t)
System x (t ) Ax(t ) Bu (t )
y (t ) Cx(t )
It is necessary to estimate the state xˆ (t ) from mathematical
model of the system and the input-output data.
Observability matrix: C
CA
O CA
2
CAn 1
+
L
xˆ (t )
B ++
+ C
yˆ (t )
xˆ (t ) Axˆ (t ) Bu (t ) L( y (t ) yˆ (t ))
State estimator:
yˆ (t ) Cxˆ (t )
L [l1 l2 ln ]
T
where:
28 November 2022 © H. T. Hoàng - [Link]/~hthoang/ 113
Design of state estimators
Requirements:
The state estimator must be stable, estimation error
should approach to zero.
Dynamic response of the state estimator should be fast
enough in comparison with the dynamic response of the
control loop.
It is required to chose L satisfying:
All the roots of the equation det( sI A LC ) 0 locates
in the half-left s-plane.
The roots of the equation det( sI A LC ) 0 are further
from the imaginary axis than the roots of the equation
det( sI A BK ) 0
Depending on the design of L, we have different state estimator:
Luenberger state observer
Kalman filter
© H. T. Hoang - HCMUT 114
Procedure for designing the Luenberger state observer
0 1 0 0
A 0 0 1 B 3 C 1 0 0
4 7 3 1
Assuming that the states of the system cannot be directly
measured. Design the Luenberger state estimator so that the
poles of the state estimator lying at 20, 20 and 50.
Balancing the coefficients of the equ. (1) and (2) leads to:
l1 3 90
3l1 l2 7 2400
7l 3l l 4 20000
1 2 3