MOSFET

Digital Circuit

1
Introduction
• The design of digital circuits has progressed from resistor-transistor
logic (RTL) and diode-transistor logic (DTL) to transistor-transistor
logic (TTL) and emitter-coupled logic (ECL) to complementary
MOS (CMOS)

The founders of Intel posing with a

rubylith of the 8080 CPU in 1978.
From left to right: Andy Grove
(CEO of Intel), Robert Noyce and
Gordon Moore (Image courtesy of
Intel Corporation)

2
 Introduction (cont.)
•Moore’s Law: The number of transistors in an integrated circuit (IC) doubles about every two years.
•The density and number of transistors in microprocessors has increased from 2300 in the 1971 4-bit 4004
µprocessor to 25 million at the beginning of the 21st century (The mature version of Pentium III and early
AMD processors)
•The most recent reports show that there are almost 500 Billion transistor in the AMD Epyc Rome chips
•The highest number of transistors per single chip is 16TB Micron Flash 5.3 Trillion MOSFET.

3
Introduction (cont.)
• The most widely used technology for the fabrication of digital
integrated systems is MOSFET transistor. The small size and low
power dissipation of CMOS circuits allows for a high level of
integration for logic and memory circuits.
• Initially NMOS logic circuits will be examined, which contain only
n-channel transistors. Complementary MOS, or CMOS, logic
circuits, which contain both n-channel and p-channel transistors are
to be discussed in the next chapter.
• JFET logic circuits are very specialized so they will not take into
account.

4
Review on the previous types
• Resistor-Transistor Logic (RTL) Gates

VO

NOR gate RTL logic circuit diagram

5
Review on the previous types (cont.)
• Resistor-Transistor Logic (RTL) Gates

6
 Review on the previous types (cont.)
• Resistor-Transistor Logic (RTL) Gates

NAND gate RTL logic AND gate RTL logic

circuit diagram circuit diagram

OR gate RTL logic

circuit diagram
7
Review on the previous types (cont.)
• Diode-Transistor Logic (DTL) Gates

NOR gate DTL logic circuit diagram

8
Review on the previous types (cont.)
• Diode-Transistor Logic (DTL) Gates

NAND gate DTL logic circuit diagram

9
Review on the previous types (cont.)
• Diode-Transistor Logic (DTL) Gates

AND gate DTL logic circuit diagram

10
Review on the previous types (cont.)
• Diode-Transistor Logic (DTL) Gates

OR gate DTL logic circuit diagram

DTL was ousted by faster TTL gates by 1974.

11
NMOS Inverter
For any IC technology used in digital circuit design, the basic circuit
element is the logic inverter.
Once the operation and characterization of the inverter circuits are
thoroughly understood, the results can be extended to the design
of the logic gates and other more complex circuits.
The ideal inverter has the following symbol and Voltage Transfer
Characteristic curve(VTC).

12
NMOS Inverter: practical transfer characteristic
In inverter circuit, the transition between VH and VL does not occur in
the abrupt manner as indicated in pervious figure, but is more gradual,
as indicated by the more realistic transfer characteristic shown below.
A single, well-defined value of VREF does not exist. Instead, several
additional input voltage levels are important.
Ideal VTC

13
NMOS Inverter: practical transfer
characteristic (cont.)
• When the input vi is below the input low-logic-level VIL, the
output is defined to be in the high-output or 1 state.
• As the input voltage increases, and exceeds the voltage of the
input high-logic-level VIH. the output voltage vo falls until it
reaches the low output or 0 state.
• The input voltages VIL and VIH are defined by the points at which
the slope of the voltage transfer characteristic equals – 1.
• Voltages corresponding to the region between VIL and VIH do not
represent valid logic input and generate indeterminate output
voltages.
• The voltages, VOL and VOH represent the inverter output voltages at
the -1 slope points and correspond to input levels of VIH and VIL,
respectively.
14
NMOS Inverter (cont.)
An inverter operating with power supplies at V+ can be implemented
using a switch with a resistive load.

Load
Element

Three inverter load elements are compared in terms of voltage transfer

characteristics, noise margin, power consumption, packing density, and
propagation delay time.

15
NMOS Inverter with resistor load
Figure below shows a single NMOS transistor connected to a resistor to
form an inverter, with its characteristics and load line.
The voltage transfer characteristics of the inverter will be determined
by examining the various regions in which the transistor can be biased.

16
 IV Characteristic curve VS Voltage Transfer Curve
• Diagnose the voltage development (Vin and Vout at the
Transfer Curve and compare the output location of Vout in
the IV curve

High VIN Low VIN

ID
Input related Development

VD

17
NMOS Inverter with resistor load (cont.)
• When the input voltage is less than or equal to the threshold voltage,
(vI < VTN ). The transistor is cut off, iD = 0, there is no voltage drop across
RD and the output voltage is vo = VDD = vDS. The maximum output voltage
is defined as the logic 1 level.
• As the input voltage becomes just greater than VTN, the transistor turns on
and is biased in the saturation region.
The output voltage is then 1𝑊
vo = VDD – iD RD 𝐾𝑛 = 𝜇𝑛 𝐶𝑜𝑥 VRD
2 𝐿
where the drain current is given by
iD = Kn(vGS – VTN)2 = Kn(vI – VTN )2 VO
So: vo = VDD – RDKn(vI – VTN )2
which relates the output and input voltages as long as the transistor is biased
in the saturation region.

18
 NMOS Inverter with resistor load (cont.)

• As the input voltage increases,

the Q-point of the transistor
moves up the load line. At the
transition point, we have
vDS (sat ) = vGS – VTN Vot = VIt – VTN

• where Vot , and VIt , are the

drain-to-source and gate-to-
source voltages, respectively,
at the transition point.

19
NMOS Inverter with resistor load (cont.)
Substituting the final equation into vo,
RDKn(VI – VTN )2 + (VI – VTN ) – VDD = 0
the input voltage at the transition point can be determined

• As the input voltage becomes greater than VIt, the Q-point continues
to move up the load line, and the transistor becomes biased in the
nonsaturation region. The drain current is then
iD = Kn[2(vGS – VTN)vDS – vDS 2] = Kn[2(vI – VTN)vo – vo2]
Substitute the value of iD , in the equation of output voltage
vo = VDD – RDKn[2(vI – VTN)vo – vo2]
Which relates the input and output voltages as long as the transistor is
biased in nonsaturation region.

20
NMOS Inverter with resistor load (cont.)
Figure below shows the voltage transfer characteristics of this inverter
for three resistor values. Also shown is the line, which separates the
saturation and nonsaturation bias regions of the transistor.
The figure shows that low output voltage, (logic 0 level), for high input
decreases with increasing load resistance, and the sharpness of the
transition region between low and high input increases with increasing
load resistance.

21
NMOS Inverter with resistor load (cont.)
large resistor value in the inverter will limit current and power
consumption as well as provide a small VOL value. But it would also
require a large chip area fabricated in a standard MOS process.
For completely integrated circuits, R must be implemented on chip
using the shown structure
Using the given equation, it can be seen that resistors take up a large
area of silicon as an example to fabricate 95 KΩ resistor

L
R
tW

 
 

L Rt 95 k  1 10  4 cm 9500
W  0.001  cm 1

22
 Example 1
The load resistor in an NMOS inverter is 40 KΩ. The circuit is biased
at VDD = 5 V, with VTN = 0.8 and K'n = 8 × 10–5 A/V2. 𝑘𝑛′ = 𝜇𝑛 𝐶𝑂𝑋
(a) Redesign the width-to-length ratio of the driver transistor such that
vo =0.1 V when vi = 5V.
(b) Using the results of part (a), find the driver transition point.
(c) The maximum power dissipated in the inverter circuit.
VDD  vO 5  0 .1
a) I D    0.125 mA b) RD K n (VI  VTN ) 2  (VI  VTN )  VDD  0
RD 40 10 3

40  0.1476  (VIt  0.8) 2  (V It  0.8)  5  0

I D  K n [2(vI  vTN )vo  vo ]
2

3
0.125 10  K n [2(5  0.8)(0.1)  (0.1) ]2  1  (1) 2  4(0.1476)(40)(5)
(V It  0.8) 
2(0.1476)(40)
K n  1.476 10  4 A/V 2
So, (V It  0.8)  0.839  V It  1.64 V
K n  W  4 8  10 5  W 
Kn     1.476 10   
2 L 2 L
c) P  I D (max)  VDD
W 
    3.69 3
L P  0 . 125  10  5  0.6125 mW
23
NMOS Inverter with enhancement load
• Enhancement load logic played an important role in the history of
electronic circuits. This form of logic was used in the design of the early
microprocessors, first in PMOS and later in NMOS technology, and this
logic family provides a basic foundation for understanding many of the
issues related to MOS VLSI design.
• An n-channel enhancement-mode MOSFET with the gate
connected to the drain as shown in figure below can be used
as a load device in an NMOS inverter.
MOSFET with this connection always operates in saturation
region when not in cutoff, since vDS = vGS.

For vGS = vDS ≤ VTN , the transistor is cutoff, and the

drain current is zero
For vGS = vDS > VTN , a nonzero drain current is induced in the transistor and
the transistor operates in saturation only and following condition is satisfied.
vDS(sat) = (vGS – VTN) = (vDS – VTN)
The drain current is
iD = Kn(vGS – VTN)2 = Kn(vDS – VTN )2
24
NMOS Inverter with enhancement load (cont.)
The iD versus vDS characteristic is shown below which indicate
that this device acts as a nonlinear resistor.

25
 NMOS Inverter with enhancement load (cont.)
Figure below shows an NMOS inverter with the enhancement load.
The driver transistor parameters are denoted by VTND and KnD , while the load
transistor parameters arc denoted by VTNL and KnL.
The driver transistor characteristics and the load curve are also shown in the
figure below.

26
NMOS Inverter with enhancement load
(driver at the cutoff region)
When the inverter input voltage is less than the driver threshold
voltage, (vGSD < VTND ), the driver transistor is in cutoff mode, and
does not conduct drain current.
iDL = KnL(vDSL – VTNL)2 = 0 vDSL – VTNL = 0
We have
vDSL = VDD – vo = 0
Combining these two equations
VDD – vo – VTNL = 0
The maximum output voltage is then
vo(max) =VDD – VTNL ≡ VOH
As a result the output high voltage VOH is degraded by the threshold voltage,
as shown in the driver characteristics and the load curve.

27
NMOS Inverter with enhancement load
(driver at the saturation region)
As the inverter input voltage become just greater than the driver
threshold voltage, (vGSD > VTND ), the driver transistor turns on, and is
biased in the saturation mode.
The two drain currents are equal since the output will be connected to
the gate of the other NMOS.
iDL = iDD
KnL(vGSL – VTNL)2 = KnD(vGSD – VTND)2
Substituting VGSD = vI and VGSL = VDD – vo
yields
KnL(VDD – vo – VTNL)2 = KnD(vI – VTND)2
Solving for the output voltage

KD
vo  VDD  VTNL  (vI  VTND )
KL
28
NMOS Inverter with enhancement load
(driver at the transition point)
As the input voltage increases, the driver Q - point moves up the load
curve and the output voltage decreases linearly with vI .
At the driver transition point, we have
vDSD (sat) = vGSD – VTND
In terms of input and output transition voltages
VOt = VIt – VTND
Substituting above Equation into the equation of vo in the case of
saturation, we find the input voltage at the transition
 K D 

VDD  VTNL  VTND 1 
 K L 
VIt 
KD
1
KL

29
NMOS Inverter with enhancement load
(driver at the nonsaturation region)
As the input voltage becomes greater than VIt the driver transistor
Q - point continues to move up the load curve and the driver becomes
biased in the nonsaturation region.
Since the driver and load drain currents are still equal, (iDD = iDL),
we now have
KnL(vDSL – VTNL)2 = KnD[2(vGSD – VTND)× vDSD – v2DSD ]
Substituting vGSD = vI , vDSD = vo , and vDSL = VDD – vo
we get
KnL(VDD – vo – VTNL)2 = KnD[2(vI – VTND)× vo – v2o ]
As shown in the above equation, the relationship between vI and vo in
this region is not linear.

30
NMOS Inverter with enhancement load (cont.)
Figure below shows the voltage transfer characteristics of this inverter
for three KnD – to – KnL ratios.
The ratio KnD / KnL is the aspect ratio and is related to the width-to-
length parameters of the driver and load transistors.
We see that the minimum output voltage, or the logic 0 level, for a high
input decreases with an increasing KnD / KnL ratio.

31
Example 2
For an NMOS inverter with saturated load, the bias is VDD = 3 V and
the transistor threshold voltages are 0.5 V.
(a) Find the ratio KnD / KnL such that vO = 0.25 V when vI = 3 V.
(b) Repeat part (a) for vI = 2.5 V.
(c) If W /L = 1 for the load transistor, determine the power dissipated
in the inverter for parts (a) and (b).
a) K nL(VDD  vo  VTNL ) 2  K nD [2(vI  VTND )  vo  vo ]
2

K nD K
[2(3  0.5)(0.25)  (0.25) 2 ]  (3  0.25  0.5) 2  nD  4.26
K nL K nL
K nD K
b) [2(2.5  0.5)(0.25)  (0.25) 2 ]  (3  0.25  0.5) 2  nD  5.4
K nL K nL
c) iD  K nL(VDD  vo  VTNL ) 2
80  10 5
iD  (1)(3  0.25  0.5) 2  0.203 mA
2
P  iD  VDD  0.203  10 3  3  0.608 mW
for both (a) and (b)
32
 Depletion Mode MOSFET
• The regular enhancement mode MOSFETs
usually operate by applying +ve voltage to
its gate (talking about n-channel
MOSFETs)
• The positive polarity attracts the electrons
to create the inversion layer (the channel)
to conduct the current. So it is normally
OFF (no channel unless the voltage is
applied to the gate).
• Depletion Mode MOSFETs has their layer
already created using ion implantation, for
that reason they will conduct even when no
voltage is applied to the gate. So this made
it Normally ON.
• To control the behavior of the transistor, -
ve voltage is applied to the gate. In this
way, the applied voltage will repel the
electrons in the channel and (Deplete the
electrons there) 33
NMOS Inverter with depletion load
• Depletion-mode MOSFETs can also be used as load elements in NMOS inverters.
• The saturated load circuits were developed for use in integrated
circuits because all the devices had the same threshold voltages
in early NMOS technologies. Once ion-implantation
technology was perfected, it became possible to selectively
adjust the threshold of the load transistors to alter their
characteristics to become those of NMOS depletion mode
devices with VTN < 0, and the use of this circuit became
feasible.
• Figure on the right hand side shows the NMOS inverter
with depletion load. The gate and source of the
depletion-mode transistor are connected together.
• The driver transistor is still an enhancement-mode.
• For driver transistor parameters (VTND > 0) and for load
transistor (VTNL < 0).
• The fabrication process for this inverter is slightly more
complicated than for the enhancement-load, since the
threshold voltages of the two devices are not equal.
• However, the advantages of this inverter make the extra processing steps
worthwhile. This inverter has been the basis of many microprocessor and static
memory designs. 34
NMOS Inverter with depletion load (cont.)
The current-voltage characteristic curve for
the depletion load, is shown in the figure.
Since the gate is connected to the source,
vGSL = 0, and the Q-point of the load is on
this particular curve.

The driver transistor characteristics and the common load curve are
shown in Figure below.

35
NMOS Inverter with depletion load
(driver at the cutoff region)
When the inverter input is less than the driver threshold voltage, the
driver is cutoff and the drain currents are zero.
As shown in the current-voltage characteristic for the depletion load,
for iD = 0, the drain-to-source voltage of the load transistor must be
zero; therefore,
vO = VDD for vI < VTND .
An advantage of the depletion-load inverter over the enhancement-load
inverter is that the high output voltage, or the logic 1 level, is at the full
VDD value.

36
NMOS Inverter with depletion load
(driver at the saturation region)
As the input voltage becomes just greater than the driver threshold
voltage (vI > VTND), the driver turns on and is biased in the saturation
region; however, the load is biased in the nonsaturation region.
The Q-point lies between points A and B on the load curve shown
previously. The two drain currents still equal, or
iDD = iDL, so:
KnL(2(vGSL – VTNL)vDSL – v2DSL) = KnD(vGSD – VTND)2
Substituting vGSD = vI , vGSL = 0, and vDSL = VDD – vO ,
KnL(2(–VTNL)(VDD – vO) – (VDD – vO)2) = KnD(vI – VTND)2
• This equation relates the input and output voltage as long as the
driver is biased in saturation region and load is biased in
nonsaturation region.

37
NMOS Inverter with depletion load
(inverter transition points)
There are two transition points for the NMOS inverter with a depletion
load: one for the load and one for the driver. These are points B and C,
respectively, as shown in the Figure.
The transition point for the load is given by
vDSL = VDD – VOt
And
vDSL = vGSL – VTNL
By equating the relations we get
VDD – VOt = vGSL – VTNL
Since vGSL = 0
VOt = VDD + VTNL
since VTNL is negative, this implies that
VOt < VDD

38
NMOS Inverter with depletion load
(inverter transition points)
The transition point for the driver is given by
vDSD = vGSD – VTND
Or in terms of input and output voltage we can write
VOt = VIt - VTND
When both devices are biased in saturation region the Q point lies
between point B and C on the load curve, and
KnD(vGSD – VTND)2 = KnL(vGSL – VTNL)2
Or
KD
(vI  VTND )  VTNL
KL
Implies that input voltage is
constant as the Q-point
passes this region
39
NMOS Inverter with depletion load
(driver is in nonsaturation region)
If the input voltage further increased, the driver is biased in the
nonsaturation region while load is in saturation region. The Q-point
moves between C and D on the load curve.
equating the two drain currents equation, we obtain
KnD(2(vGSD – VTND)vDSD – v2DSD) = KnL(vGSL – VTNL)2
Which becomes
K nD
[2(vI  VTND )vO  vO ]  (VTNL ) 2
2

K nL
Which Implies that input and output
voltages are not linear in this
region.

40
NMOS Inverter with depletion load
The voltage transfer characteristic of this inverter for three value of KD
/KL , are shown below. The figure shows that in this configuration, more
abrupt VTC transition region can be achieved even though the W/L ratio for
the output MOSFET is small.

41
Example 3
Consider a depletion load inverter biased at VDD = 5V. The threshold
voltages are VTND = 0.8 V and VTNL = – 2 V. Design the inverter such
that the maximum power dissipation is 350 μW and the output voltage
is 0.05 V when vI = 5V. (K'n = 35 μA/V2)
350 10 6
P  iD  VDD  iD   70 μA
5
6
35  10 W 
iD  K nL (VTNL ) 2  70 10 6     (2) 2
2  L L
W 
   1
 L L
iD  K nD [2(vI  VTND )  vo  vo ]
2

6 35 10 6  W 
70 10      [2(5  0.8)  (0.05)  (0.05) 2 ]
2  L L
W 
    9.58
 L D 42
Noise Margin
• The noise margin represent safety margins that prevent the
gate from producing false logic decisions in the presence of
noise sources
• The type of noise usually considered in digital circuit is called
series voltage noise. Figure below shows two inverters in
series in which the output of the second is connected back to
the input of the first, and a series voltage noise sources δVL
and δVH.
• The noise amplitudes may be such as to increase the low
output and reduce the high output. The noise margins are
defined as the maximum values of δVL and δVH at which the
inverters will remain in the correct state.

43
Noise Margin (cont.)
Return back to the general voltage transfer function for the
inverter shown previously.
When the input voltage is in the range VIL < vI < VIH , the output
signal changes rapidly and the gain magnitude is greater than
one. This region is called the undefined range.
If the input voltage is pushed into this range by a noise signal, a
logic error could be introduced into the system.

44
Noise Margin (cont.)
The noise margins are defined as
NML = VIL – VOLU & NMH = VOHU – VIH
where
NML and NMH : are noise margins for low and high input levels
VOLU and VOHU are the output voltages at unity-gain values (-1)
Since inverter with a resistor load is rarely used in practice, noise
margins for NMOS inverters with enhancement and depletion
loads will be examined.

45
Enhancement-Load Inverter Noise Margin
The general voltage transfer characteristic for the NMOS inverter
with enhancement load is shown below

At input voltage high we have:

KnL(VDD – vo – VTNL)2 = KnD[2(vI – VTND)× vo – v2o ]
By taking the derivative of the relationship between the input and
output voltages with respect to vI ,
dvO dvO dvO dvO
2 K nD vO  2 K nD vI  2 K nDVTND  2 K nD vO  2 K nL (VDD  vO  VTNL )
dvI dvI dvI dvI 46
Enhancement-Load Inverter Noise Margin (cont.)
Setting the derivative equal to –1
K nD vO  K nD vI  K nDVTND  K nD vO  K nL (VDD  vO  VTNL ) 
K nD
(VDD  VTNL )  (vI  VTND )
K nL
vO  VOLU 
K
1  2 nD
K nL
Combining this equation with the input and output relationship
for this case, and solving for vI , we get
 
 1  2 K nD  VOt = VIt + VTND
V V  K nL 
vI  VIH  VTND  DD TNL   1
K nD
 1  3 K nD 
K nL  K nL 
 

47
Example 4
Determine the noise margins of an inverter with enhancement
load with the following parameters: VDD = 5 V, VTND = VTNL = 0.8 V,
VOH = 4.2 V, VOL = 0.1 V, and KnD /KnL = 25.1.

48
Enhancement-Load Inverter Noise Margin (cont.)
The results of this example can be compared to the two series inverter shown
previously with including series-voltage noise sources as shown below.
If the input is high at VOHU = 4.2 V and if a noise source of
δVH = NMH = 2.59V is included, the input to inverter G1 is 1.61 V
corresponding to VIH, which is the minimum value corresponding to a logic 1
level. With an input of VIH = 1.61 V to G1 the output is 0.479V.
If a noise source of δVL = NML = 0.321 V is present, then input to G2 is 0.8V
corresponding to VIL, which is the minimum value corresponding to a logic 0
level. With an input of VIL = 0.8V to G2, the output is 4.2V.
If the output is connected back to the input, the resulting configuration is in a
stable stale. If the noise sources δVH and δVL increase slightly above the noise
margins, the configuration will switch states.

49
depletion-Load Inverter Noise Margin
The general voltage transfer characteristic for the NMOS inverter
with depletion load is shown below

The point at which VIL occurs, is calculated by taking the derivative of the
relationship between the input and output voltage and equal it to -1, we get:
K nD
vO  VOHU  (VDD  VTNL )  (vI  VTND )
K nL
50
Depletion-Load Inverter Noise Margin (cont.)
and
(VTNL )
vI  VIL  VTND 
K nD  K nD 
1  
K nL  K nL 

The point at which VIH occurs, is calculated by taking the derivative of the
relationship between the input and output voltage and equal it to -1, we get:
(VI  VTND )
vO  VOLU 
2
and
2(VTNL )
vI  VIH  VTND 
K 
3 nD 
 K nL 

51
NMOS NOR and NAND Gates
NMOS logic circuits are formed by combining driver transistors
in parallel, series, or series-parallel combinations to produce a
desired output logic function.
NMOS NOR gate can be constructed by connecting an additional
driver transistor in parallel with a depletion load inverter as
shown below.

52
NMOS NOR and NAND Gates (cont.)
• If both A and B are low (logic 0),
then both MDA and MDB are cut off and
vO = VDD.
• If one of the input is high and the other is low, for example:
A is high (logic 1) and B is low (logic 0),
then MDB is cut off and the remaining circuit behave as
depletion load inverter as considered previously.
• If both A and B are high (logic 1),
then both MDA and MDB turn on and the two driver transistors
are switched into nonsaturation region and load transistor is
biased in saturation region. We have
iDL = iDA + iDB ,

53
NMOS NOR and NAND Gates (cont.)
which in general terms can be written
KnL[vGSL – VTNL]2 = KnDA[2(vGSA – VTNA)vDSA – v2DSA] +
KnDB[2(vGSB – VTNB)vDSB – v2DSB]
Suppose that the two driver transistors are
identical, which implies that,
KnDA = KnDB = KnD
VTNA = VTNB = VTND
from figure we have:
vGSL = 0,
vGSA = vGSB = VDD
vDSA = vDSB = vO
By substituting all these parameters we can write above equation as,
(– VTNL)2 = 2(KnD/KnL)[2(VDD – VTND)vO – v2O]

This equation shows that when both driver are conducting, the effective
width – length ratio of the NOR gate is double. This mean that output
voltage becomes slightly smaller when both inputs are high. 54
NMOS NOR and NAND Gates (cont.)
The NMOS NAND logic gate contains additional driver transistors
connected in series. Figure below shows a two-input NMOS NAND
gate with a depletion load.
• If both A and B is low (logic 0),
or if either A or B is low (logic 0),
at least one driver is cut off, and the output is high
• If both A and B is high (logic 1)
then the composite driver of NMOS inverter conducts
and the output goes low.
Since vGSD of MDA and MDB are not equal, determining
the actual voltage VOL of a NAND gate is difficult.
vDS of MDA and MDB must adjust themselves to produce the same current.
In addition, if the body effect is also included, the analysis becomes even more
difficult. Since the two driver transistors are in series, a good approximation
assumes that the width-to-length ratio of the drivers must be twice that of a
single driver in an NMOS inverter to achieve a given VOL value. 55
Example 5
Design a three-input NMOS NOR logic gate with depletion load such
that VOL(max) = 0.12 V. Let VDD = 5 V, VTND = 0.8 V, VTNL = – 1.4 V.
The maximum power dissipation in the circuit must be 0.8 mW.
Determine (W/L) for the load and (W/L) for each driver.
maximum value of vo in low state obtain when only one input is high
assume only input A is high
K nD [2(vGSA  VTNL )  vDSA  vDSA ]  K nL (VTNL ) 2
2

K nD
K nD [2(5  0.8)  0.12  0.12 2 ]  K nL ((1.4)) 2   1.97
K nL
800  10 6
P  iD  VDD  iD   160 μA
µW
5
iD  K nL (VTNL ) 2  K nL  81.63 μA µA.V-2
 k   W   35  10 6  W 
K nL   n    81.63  10 6
   
 2  L  L  2  L  L
 
W  W 
    4.66     9.19
 L L  L D 56
NMOS Logic Circuits
A series – parallel combination of drivers can be expanded to
synthesize more complex logic functions.
Consider the circuit in Figure below.
the Boolean output function is
f  ( A  B  C)
The individual transistor width-to-length
ratios produce an effective (KnD/KnL) ratio
of 4 for an effective single inverter when
only MDA and MDB are conducting, or only
MDC is conducting. The actual complexity
of the Boolean function is limited since the
required width-lo-length ratios of individual transistors may become
unreasonably large.

57