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ADEC Lab Manual 3 Sem

Analog and digital electronics (Bangalore Institute of Technology)

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BANGALORE INSTITUTE OF TECHNOLOGY

K.R. ROAD, V.V. PURA, BENGALURU -560 004

Department of Robotics and Artificial Intelligence

Engineering

Analog and Digital Electronic Circuits Laboratory Manual

(BRI303)

Prepared by: PALLAVI M L

Assistant Professor
DEPT of RAI

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LIST OF EXPERIMENTS

Design and implement

1.
(a) Half Adder &Full Adder using i) Basic gates ii) NAND gates.
(b) Half Subtractor & Full Subtractor using i) Basic gates ii) NAND gates.
2. Design and implement 4-bit Parallel Adder/ Subtractor using IC 7483.

3. Design and Implementation of 1-bit Comparator.

4. Realize the 4-variable function using IC 74151(8:1MUX).

5. Realize the following flip-flops using NAND Gates. JK & D

Flip-flops.
6. Realize 4bit SISO, SIPO, PIPO using D flip flop
7.
Realize 3bit Asynchronous counter using JK flip flop
8. Realize 3bit synchronous counter using D flip flop

9 To construct and observe clipping for different configurations.

10. To construct and find band width of RC coupled amplifier.

11. To construct and check oscillation frequency for RC phase shift oscillator.

12 To construct and obtain OPAMP Astable multi-vibrator.

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OBJECTIVES & OUTCOMES OF THE COURSE

Course Objectives
This laboratory course enables students to get practical experience in design,
realization and verification of
 Demorgan’s Theorem, SOP, POS forms
 Full/Parallel Adders, Subtractors and Magnitude Comparator
 Multiplexer using logic gates
 Demultiplexers and Decoders
 Flip-Flops, Shift registers and Counters.

Course Outcomes
On the completion of this laboratory course, the students will be able to:
 Demonstrate the truth table of various expressions and combinational
circuits using logic gates.
 Design various combinational circuits’ such as adders, subtractors,
comparators, multiplexers and demultiplexers.
 Construct flips-flops, counters and shift registers.
 Simulate Serial adder and Binary Multiplier.

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1. Half Adder

Truth Table:

A B S C
0 0 0 0 S =A 
0 1 1 0 BC =
1 0 1 0 A.B
1 1 0 1

Realization of Half Adder:

i). Using Basic gates

ii). Using NAND gates

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Experiment No: 1

ADDERS AND SUBTRACTORS

Aim:(i) To realize half/full adder using Logic gates & NAND gates
(ii) To realize half/full Subtractor using Logic gates & NAND gates

Components Required: IC 7408, IC 7432, IC 7486, IC 7404, IC 7400,

Patch cords

Theory:

Half-Adder: A combinational logic circuit that performs the addition of two

data bits, A and B, is called a half-adder. Addition will result in two output
bits; one of which is the sum bit S, and the other is the carry bit, C. The
Boolean functions describing the half-adder are: S =A  B
C = A.B
Full-Adder: The half-adder does not take the carry bit from its previous
stage into account. This carry bit from its previous stage is called carry-in
bit. A combinational logic circuit that adds two data bits, A and B, and a
carry-in bit, Cin , is called a full-adder. The Boolean functions describing
the full-adder are:
S = A  B  Cin
C = A.B+ Cin (A  B)

Half Subtractor: Subtracting a single-bit binary value B from another A

(i.e. A-B) produces a difference bit D and a borrow out bit Br. This operation
is called half subtraction and the circuit to realize it is called a half
subtractor. The Boolean functions describing the half-Subtractor are:

D =A  B
Br= A’.B
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a
single-bit value A produces a difference bit D and a borrow out Br bit. This
is called full subtraction. The Boolean functions describing the full-
subtractor
are:
D = A  B  Cin
Br= A’.B + A’ .Cin + B . Cin

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2. Full Adder
Truth Table:

A B Cin S C
0 0 0 0 0
0 0 1 1 0 S = A  B  Cin
0 1 0 1 0 C = A.B+ Cin (A  B)
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Realization of Full Adder:

(i) using logic gates

(ii) using Nand gates

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Procedure:

1. Verify that the gates are working.

2. Make the connections as per the circuit diagram for the half adder
circuit, on the trainer kit.

3. Switch on the VCC power supply and apply the various combinations
of the inputs according to the respective truth tables.
4. Verify that the outputs are according to the expected results.

5. Repeat the procedure for the full adder circuit, the half subtractor
and full subtractor circuits.

6. Verify that the sum/difference and carry/borrow bits are according

to the expected values.

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3. Half Subtractor

Truth Table:

A B D Br
0 0 0 0 D =A  B
0 1 1 1
1 0 1 0 Br = A.B
1 1 0 0

Realization of Half Subtractor:

(i)
(ii) using logic gates

ii) Using NAND gates

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4. Full Subtractor

Truth Table:

A B Cin D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1 D = A  B  Cin
1 0 0 1 0
Br= A’.B + A’.Cin + [Link]
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Realization of Full Subtractor:

(i) Using logic gates:

(ii) Using NAND gates

Result:

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1. 4-BIT BINARY ADDER

Example: 7+2=09 which is equal to (1001)2

• 7 is realized at A3 A2 A1 A0 = 0111
• 2 is realized at B3 B2 B1 B0 = 0010
Sum = (1001)2

Circuit:

MSB LSB
INPUTS Cin
A3 A2 A1 A0
B3 B2 B1 B0
OUTPUT Cout S3 S2 S1 S0

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Experiment No: 2

PARALLEL ADDER AND SUBTRACTOR USING 7483

Aim: To design and set up the following circuit using IC 7483.

i) A 4-bit binary parallel adder.
ii) A 4-bit binary parallel subtractor.

Components Required: IC 7483, IC 7486, Patch Cords etc.

Theory:

The Full adder can add single-digit binary numbers and carries. The
largest sum that can be obtained using a full adder is (11)2. Parallel adders
can add multiple-digit numbers. If full adders are placed in parallel, we can
add two- or four-digit numbers or any other size desired. Figure below uses
STANDARD SYMBOLS to show a parallel adder capable of adding two digit
binary numbers. The addend would be input on the A inputs (A2 = MSD,
A1 = LSD), and the augend input on the B inputs (B2 = MSD, B1 = LSD).

To add four bits need four full adders arranged in parallel. IC 7483 is a 4-
bit parallel adder is used.

Procedure for Adding two 4-Bit data:

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Apply augend and addend bits on A and B and cin=0.
5. Verify the results and observe the output of ADDER CIRCUIT

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2. 4-Bit Binary Subtractor.

(i) 4 bit subtraction operation using 7483 for A>B and Cin=1

Example: 8 – 3 = 5 which is equal to (0101)2

•8 is realized at A3 A2 A1 A0 = 1000

•3 is realized at B3 B2 B1 B0 through X-OR gates = 0011

•Output of X-OR gate is 1’s = 1100

complement
•2’s Complement can be obtained by adding Cin 1
=
Therefore Cin =1

A3 A2 A1 A0 = 1 0 0 0

B3 B2 B1 B0 = 1 1 0 0

S3 S2 S1 S0 = 0 1 0 1 Cout = 1 (Ignored)

(ii) 4 bit subtraction operation using 7483 for A<B and Cin=1

Example: 14 – 15 = -1 (1111)2
•14 is realized at A3 A2 A1 A0 = 1110

•15 is realized at B3 B2 B1 B0 through X-OR gates = 1111

•Output of X-OR gate is 1’s complement of 15 = 0000

•2’s Complement can be obtained by adding Cin = 1

Therefore Cin = 1

A3 A2 A1 A0 = 1 1 1 0

B3 B2 B1 B0 = 0 0 0 0

S3 S2 S1 S0 = 1 1 1 1

Since the most significant bit of the result is 1, this is a negative number, so form the two's
complement of (1111)=-(0001)2

Circuit:

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Procedure for subtracting two 4-Bit data:

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Apply Minuend and subtrahend bits on A and B and cin=1.
5. Verify the results and observe the outputs.

Result

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1-BIT COMPARATOR

Truth Table:

A B A>B A=B A<B

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

(i)Realization using Basic Gates:

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Experiment No: 3

COMPARATOR
Aim: To realize 1 Bit magnitude comparator using basic gates.

Components required: ICs, Patch Cords & IC Trainer Kit.

Theory:

Magnitude Comparator is a logical circuit, which compares two signals A

and B and generates three logical outputs, whether A > B, A = B, or A < B. IC
7485 is a high speed 4-bit Magnitude comparator, which compares two 4-bit
words. The A = B Input must be held high for proper compare operation.
Procedure:

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Apply 0 for the bits A5, A6, A7, B5, B6, B7 OR ground them.
5. Apply given data to the rest of the bits.

6. Verify the results and observe the outputs.

Result:

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A. 4 Variable function using IC 74151

Y = F(A,B,C,D) = ∑m(0,1,2,7,8,9,14,15)

Truth table:

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Experiment No: 4

REALIZATION OF 4 VARIABLE FUNCTIONS USING IC 74151

(8:1 MUX)

Aim: To design and set up the following circuit using 4 variable function
using IC 74151 (8:1 MUX)

Components Required: IC74151, Patch Cords & IC Trainer Kit.

Procedure:
1. For the given expression, a truth table is to be written.
2. An expression in SOP format is to be written.
3. The connection is made according to the obtained expression.
4. The truth table is verified for that particular expression.

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1. J-K FLIPFLOP:

Truth Table:

Circuit:

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Experiment No: 5

FLIP FLOPS
Aim: To realize the following Flip-flops using NAND gates: JK and D Flip-
flops.
Components required: IC 7410, IC7400, Patch Cords

Theory:

A flip-flop is a circuit that has two stable states and can be used to store
state information. A flip-flop is a bistable multivibrator. The circuit can be
made to change state by signals applied to one or more control inputs and will
have one or two outputs. It is the basic storage element in sequential logic. Flip-
flops and latches are a fundamental building block of digital electronics systems
used in computers, communications, and many other types of systems.

A flip–flop is a “bit bucket”; it holds a single binary bit .Flip flops are
actually an application of logic gates. With the help of Boolean logic we can
create memory with them. Flip flops can also be considered as the most basic
idea of a Random Access Memory [RAM].

The most commonly used application of flip flops is in the implementation of

a feedback circuit. As a memory relies on the feedback concept, flip flops can be
used to design it.

Procedure:

1. Make the connections as shown in the circuit diagrams.

2. Apply inputs as shown in the truth tables,

3. Check the outputs of the circuits; verify that they match with the truth
tables.

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2. D – FLIPFLOP:

Truth Table:

Circuit:

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SERIAL INPUT SERIAL OUTPUT (SISO): Procedure:

1. Connections are made as shown in the SISO circuit diagram.

2. Make sure the 7495 is operating in SISO mode by ensuring Pin 6 (Mode)
is set to LOW, and connect clock input to Clk 1(Pin 9).

3. The shift register is loaded with 4 bits of data one by one serially.

4. At the end of the 4thclock pulse, the first data ‘d0’ appears at QD.

5. Apply another clock pulse, to get the second data bit, ‘d1’ at QD.
Applying yet another clock pulse gets the third data bit, ‘d2’ at QD, and so
on.

Truth Table: Circuit Diagram:

Serial
CLK QA QB QC QD
I/P
1 do=0 0 X X X
2 d1=1 1 0 X X
3 d2=1 1 1 0 X
4 d3=1 1 1 1 0=do
5 X X 1 1 1=d1
6 X X X 1 1=d2
7 X X X X 1=d3

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Experiment No: 6
SHIFT REGISTERS
Aim: To study IC 74S95, and the realization of Shift left, Shift right, SIPO,
SISO, PISO, PIPO operations using the same.
Components required: IC 7495, patch cords etc.
Theory:

• A shift register is a group of flip-flops (typically 4 or 8) that are

arranged so that the values stored in the flip-flops are shifted from
one flip-flop to the next for every clock.

• Shift registers are used extensively in logic circuits to control digital

displays.

• A classic example is numbers being typed into a calculator. As the

numbers are entered, the digits shift to the left one position. This
shifting is controlled by a shift register.

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1. SERIAL INPUT PARALLEL OUTPUT (SIPO/Right Shift):

Procedure:

1. Connections are made as shown in the SISO circuit diagram.

2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6

(Mode) is set to LOW, and connect clock input to Clk 1(Pin 9).

3. Apply the first data at pin 1 (SD1) and apply one clock pulse. We
observe that this data appears at pin 13 (QA).

4. Now, apply the second data at SD1. Apply a clock pulse. We now
observe that the earlier data is shifted from QA to QB, and the new
data appears at QA.

5. Repeat the earlier step to enter data, until all bits are entered one by
one.

6. At the end of the 4th clock pulse, we notice that all 4 bits are
available at the parallel output pins QA through QD.

Truth Table: Circuit:

Serial
CLK QA QB QC QD
I/P
1 1 1 X X X

2 0 0 1 X X

3 1 1 0 1 X

4 1 1 1 0 1

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2. SERIAL INPUT PARALLEL OUTPUT (SIPO/Left Shift):

Procedure:
1. Connections are made as shown in the SISO circuit diagram.
2. Make sure the 7495 is operating in Parallel mode by ensuring Pin 6
(Mode) is set to HIGH, and connect clock input to Clk 2(Pin 8).
3. Apply the first data at pin 5 (D) and apply one clock pulse. We
observe that this data appears at pin 10 (QD).
4. Now, apply the second data at D. Apply a clock pulse. We now
observe that the earlier data is shifted from QD to QC, and the new
data appears at QD.
5. Repeat the earlier step to enter data, until all bits are entered one by
one.
6. At the end of the 4th clock pulse, we notice that all 4 bits are
available at the parallel output pins QA (MSB), QB, QC, QD (LSB).

Truth Table: Circuit:

Serial
CLK QA QB QC QD
I/P
1 1 X X X 1

2 0 X X 1 0

3 1 X 1 0 1

4 1 1 0 1 1

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3. PARALLEL INPUT PARALLEL OUTPUT (PIPO):

Procedure:

1. Connections are made as shown in the PIPO mode circuit diagram.

2. Set Mode Control M to HIGH to enable Parallel transfer.

3. Apply the 4 data bits as input to pins A, B, C, D.

4. Apply one clock pulse at Clk 2 (Pin 8).

5. Note that the 4 bit data at parallel inputs A, B, C, D appears at the

parallel output pins QA, QB, QC, QD respectively.

Truth Table:

Parallel I/P Parallel O/P

CLK A B C D QA QB QC QD
1 1 0 1 1 1 0 1 1

Circuit:

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Experiment No: 7
ASYNCHRONOUS COUNTER
Aim: Realize 3bit Asynchronous counter using JK flip flop (RIPPLE COUNTER).
Components required: Digital IC trainer kit, IC 7496, patch cords etc.
Theory: A counter in which each flip-flop is triggered by the output goes to previous
flip-flop. As all the flip-flops do not change state simultaneously spike occur at
the
output. To avoid this, strobe pulse is required. Because of the propagation delay
the operating speed of asynchronous counter is low. Asynchronous counter are
easy and simple to construct.

PROCEDUR

1. Check the components for their working.

2. Insert the appropriate IC into the IC base.
3. Rig up the circuit as shown in the logic circuit diagram.
4. Apply various input data to the logic circuit via the input logic
switches.
5. Note down the corresponding output and verify the truth table.

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Circuit Diagram:

Truth Table:

Waveform:

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Experiment No: 8
DIODE CLIPPING CIRCUITS

Aim: To design and test diode clipping circuits for peak clipping and peak detection.

Components required:
-Power Supply

-Diodes IN4007or BY127

-Resistors
Procedure:
 Make the Connections as shown in the circuit diagram
 Apply sinusoidal input Vi of 1 KHz and of amplitude 8V P-P to the circuit.
 Observe the output signal in the CRO and verify it with given waveforms.
 Apply Vi and Vo to the X and Y channel of CRO and observe the transfer characteristic
waveform and verify it.

Positive Clipping Circuits

Circuit Diagram

Waveforms

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Transfer Characteristics:

To find the value of R:

Given: Rf =100Ω, Rr =100KΩ

Rf - Diode forward resistance

Rr - Diode reverse resistance

R= =3.16KΩ

Choose R as 10 KΩ

Let the output voltage be clipped at +3V

Vomax =3V

From the circuit diagram,

Vomax = Vr+Vref

Where Vr is the diode drop = 0.6V

Vref = Vomax -Vr

=3 - 0.7
Vref = 2.3 V

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Analog & Digital E l e c t r o n i c C i r c u i t s Lab(BRI303) 2023-

Experiment No: 9
RC COUPLED AMPLIFIER
Aim: To construct and find band width of RC coupled amplifier.

Equipment Required: 1 Cathode Ray Oscilloscope (CRO) 1No

2 Regulated power supply 1N
3 Function Generator 1No
4 Bread board 1No
5 Connecting wires

Components Required: 1 Resistors: 15k-2no

10k-2no
1k-2no
3.3k-2no
220Ω-2no
2 Transistor :BC107-2no
[Link]-10μf -5no

Circuit Diagram:

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THEORY:
Whenever large amplification with very good impedance matching is
required using an active device such as a transistor or a field effect transistor a single
active device and it s associated circuitry will not be able to cater to the needs. In such
a case single stage amplifier i s not sufficient and one requires more stages o f
amplification i.e., output of one stage is connected to the input of second stage of
amplification circuit and the chain continues until the required characteristics of
amplifier is achieved such an amplifier is called as multistage [Link] multistage
amplifier, the output signal preceding stage is to be coupled to the input circuit of
succeeding stage. For this inter-stage coupling different types of coupling can be
employed. They are
1. RC coupling
2. Transformer coupling
3. Direct coupling
RC coupling i s most popularly used type of coupling because it is cheap and
provides excellent fidelity over a wide range of frequency .it is usually employed
for voltage.

PROCEDURE:

1) Connect the ci rcuit as shown in the figure.

2) Apply 1Khz frequencyand 20mv Vp-p Sine wave from function
gene rator..
3) Observe input and output Waveforms simultaneously on C.R.O
4) Change the frequency of input signal from 10HZ to 1MHZ in
steps and note amplitudes of input and output Waveforms(input
signal should be maintained constant).
5) Calculate Voltage gain (A) for each (in db) verses frequency.

Observations:

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CALCULATIONS:
Maximum gain of the amp:
Upper cutoff frequency F2:
Lower cutoff frequency F1:
Band width=F2-F1:

RESULT: -
1. Frequency response of Two stage RC coupled amplifier is
plotted.
2. Gain = _______dB (maximum).
3. Bandwidth= fH--fL = _________Hz. At stage 2

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Experiment No: 1 0
RC PHASE SHIFT OSCILLATOR
Aim: To construct and check oscillation frequency for RC phase shift oscillator.
.
Equipment Required: 1 Cathode Ray Oscilloscope (CRO) 1No
2 Regulated power supply 1N
3 Function Generator 1No
4 Bread board 1No
5 Connecting wires

Components Required: 1 Transistor BC107

2 Resistors: 10k-3no,8k or 10k,22k ,100k,1.2k
3 Capacitor: 0.001μf – 3 Nos, 10μF – 2Nos, 1μf

Theory:
RC-Phase shift Oscillator has a CE amplifier followed by three sections of RC phase
shift feedback Networks the output of the last stage is return to the input of the amplifier. The values
of R and C are chosen such that the phase shift of each RC section is 60º.Thus The RC ladder network
produces a total phase shift of 180º between its input and output voltage for the given frequencies.
Since CE Amplifier produces 180 º phases shift the total phase shift from the base of the transistor
around the circuit and back to the base will be exactly 360º or 0º. This satisfies the Barkhausen
condition for sustaining oscillations and total loop gain of this circuit is greater than or equal to 1, this
condition used to generate the sinusoidal oscillations.

The frequency of oscillations of RC-Phase Shift Oscillator is,

PROCEDURE:
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Analog & Digital E l e c t r o n i c C i r c u i t s Lab(BRI303) 2023-

1. Make the connection as per the circuit diagram as shown above.

2. Observe the output signal and note down the output amplitude and time period (Td).
3. Calculate the frequency of oscillations theoretically and verify it practically (f=1/Td).
4. Calculate the phase shift at each RC section by measuring the time shifts (Tp) between
the final waveform and the waveform at that section by using the below formula.

OBSERVATIONS:

THEORITICAL CALCULATIONS: R = 10KΩ, C = 0.001 μf

PRACTICAL CALCULATIONS:

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Experiment No: 1 2
ASTABLE MULTIVIBRATORS
Aim: To construct and obtain OPAMP Astable multi-vibrator.

Equipment Required: 1 Cathode Ray Oscilloscope (CRO)

2 Dual Regulated power supply
3 Bread board
4 Connecting wires

Components Required: 1 Op-Amp IC741

2 Resistors: 10k-2no, 4.7k
3 Capacitor: 0.1μf
Theory:

1 Astable multivibrator is a rectangular wave generator. It is also called free running

multivibrator.
2 Astable multivibrator toggles between high and low states.
3 There are no stable states in astable multivibrator.
4 The reference voltage Vref (βVsat or +βVsat) is applied to the non-inverting
terminal.
 5 The resistors R1 and R2 form a voltage divider network and provide a fraction (β)
of the output to the input as feedback.
 6 When input at the inverting terminal just exceeds Vref switching takes place
resulting in rectangular wave output.
 7 The duration the output remains high, is the time required for the capacitor to
charge from -βVsat to +βVsat

Formula:

Procedure:

1. Construct the circuit as shown below in figure.

2. Observe simultaneously the output waveform and the voltage across the capacitor
using
oscilloscope.
3. Measure the amplitude and frequency.

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Circuit Diagram:

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PIN DETAILS

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VIVA QUESTIONS

1. What are Analog Systems? Give Examples.

2. What are Digital Systems? Give Examples.

3. Mention the disadvantages of Analog systems over Digital systems.

4. Explain Boolean algebra.

5. State Principle of Duality.

6. State De – Morgan’s Law.

7. Define Positive Logic and Negative Logic.

8. Define Literal.

9. Define MINTERM and MAX TERM.

10. Define a complementary function.

11. Explain Shannon’s reduction theorem.

12. Which are the basic gates and universal gates.

13. Define combinational network with example.

14. Define Sequential Network with example.

15. Define Double-Rail and Single -Rail logic.

16. When a Boolean Expression is called completely specified?

17. Explain the significance of a Don’t care function.

18. Explain the criteria of minimality.

19. Define implies, Subsumes, implicants.

20. What are Prime Implicants?

21. What is irredundant disjunctive normal formula?

22. What is an implicate?

23. What is a Map?

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24. Explain the significance of Map.

25. What is a Minimal Sum and Minimal product?

26. Explain Quine - McClusky method.

27. Explain VEM method of reduction.

28. Explain Binary Adder and Subtractor.

29. Explain various scales of integration.

30. Define Carry Look Ahead Adder.

31. Define Comparator, Decoder and Encoder.

32. Give an example for Min-term generator.

33. Give an example for Max-term generator.

34. Define priority encoder.

35. Explain Multiplexing action.

36. Define PAL, PLA and PROM.

37. Differentiate between ROM and RAM.

38. What is a Memory?

39. What is internal state and secondary state?

40. Define Flip Flop and Latch.

41. Explain Basic Bi-stable element.

42. What is a metastable state?

43. Define setting and clearing in terms of flip-flop.

44. Explain SR Latch and Give an application.

45. Explain gated SR Latch and gated D Latch.

46. Explain Timing Diagram.

47. Explain Propagation Delay in gates.

48. Explain Set and Hold time in latches.

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49. Explain Master-Slave Flip-Flop.

50. Explain the significance of edge-triggering.

51. Explain Data Lock Out.

52. Give the characteristic equations of JK, D and T Flip Flops.

53. Define Registers with example.

54. Define Counters with example.

55. Explain ripple, asynchronous and synchronous counters.

56. Explain Race Around Condition.

57. List the basic logic series.

58. Explain Semiconductor diode behavior.

59. What is Saturating Logic?

60. Explain Fan-Out and Fan-in in gates.

61. Explain DTL and TTL.

62. What is wired logic?

63. What is Totem pole Output?

64. Explain Schottky TTL.

65. Explain Emitter-Coupled Logic.

66. Which is the fastest of all the logic families?

67. What is a MOSFET?

68. Explain Enhancement and Depletion Mode in MOSFET‟s.

69. Explain Threshold voltage.

70. Explain MOSFET as Resistor.

71. Clearly differentiate between PMOS and NMOS Logic.

72. Explain CMOS Logic.

73. State Moore’s Law.

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74. Differentiate between Moore and Mealy Law.

75. Define FPGA.

76. Define PLD.

77. Define CPLD.

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