CHAPTER 5 ARM7 PROGRAMMING
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SYLLABUS
Topic Fine Detailing No of Week
Hours
ARM 5.1 Addressing mode 10 2.5
Assembly
5.2 Instruction set
Language
5.3 Assembler directives
Programming.
5.4 Programs related to:
arithmetic, logical, delay, input,
output port, serial
communication, and
interrupts
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FEATURES OF ARM PROCESSOR
◎ Load-store architecture
◎ All the instructions are 32-bit in length.
◎ Von-Neumann type bus architecture (ARM7)
◎ Mostly single cycle execution
◎ 8/16/32 bit data types
◎ Three stage pipeline is used.
◎ Simplicity: Arm processor is simple to operate.
◎ Arm processor is power efficient and small in size.
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ADDRESSING MODE
ADDRESSING MODES
ADDRESSING MODES OF ARM7
◎ For Data processing Operands
◉ Unmodified Value
◉ Modified value
◎ For memory access Operands
◉ Register-indirect addressing
◉ Relative Register
◉ Base Index addressing
◉ Base with Scaled Register
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ADDRESSING MODES
◎ Data processing operands :-
◉ Unmodified value :- in this mode the register or a value is
given unmodified i.e. without any shift or rotation
Eg. MOV R0, #1234 H
◉ This instruction will move immediate constant value
(1234)10 into register R0.
◉ Modified value :- in this mode the register or a value is
shifted or rotated.
◉ Different shift & rotate operations are :
◉ Logical shift left :- this will take the value of register and
shift the value towards left most significant by n bits. Eg.
MOV R0, R1, LSL # R2 After the execution of this
instruction R0 will take value of R1 shifted by 2 bits.
◉ Logical shift right :- this will take the value of register and
shift the value towards right by n bits. Eg. MOV R0, R1, LSR
# R2 After the execution of this instruction R0 will take
value of R1 shifted by 2 bits
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ADDRESSING MODES
◎ For Memory Access Operands :-
◉ (i) Register indirect addressing mode :- In this addressing mode, a
register is used to give the address of the memory location to be
accessed. e. g. LDR RO, [R1] This instruction will load the register RO
with the 32-bit word at the memory address held in the register R1
◉ (ii) Relative register indirect addressing mode :- In this addressing
mode the memory address is generated by an immediate value added
to a register. e.g. LDR R0,[R1,#4]
◉ Iii) Base indexed indirect addressing mode :-In this addressing mode
the memory address is generated by adding the values of two
registers. Pre- index and post-index are supported also in this
addressing mode. e.g. LDR R0,[R1, R2] (Pre- index Addressing),LDR R0,
[R1], R2 (Post- index Addressing)
◉ (iv) Base with scaled register addressing mode :-In this addressing
mode the memory address is generated by a register value added
to another register shifted left. Pre-index and post-index are
supported in this addressing mode.
◉ Pre- index and Post Index supports this addressing mode.e.g : LDR R0,
[R1,R2, LSL #2],
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ARM INSTRUCTION SET
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ARM INSTRUCTION SET
◎ Data Processing Instructions
◎ Branch Instructions
◎ Load-Store Instructions
◎ Software Interrupt Instructions
◎ Program Status Register Instructions
◎ Loading Constants
◎ ARMv5 Extensions
◎ Conditional Execution
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DATA PROCESSING INSTRUCTIONS
◎ Manipulate data within registers
◉ Move Instructions
◉ Arithmetic Instructions
◉ Logical Instructions
◉ Comparison Instructions
◉ Multiply Instructions
◎ Most data processing instructions can process one of
their operands using the barrel shifter
◎ S suffix updates the flags in the cpsr
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DATA PROCESSING INSTRUCTION
◎ It consists of
◉ Arithmetic (ADD, SUB, RSB)
◉ Logical (BIC, AND)
◉ Compare (CMP, TST)
◉ Register movement (MOV, MVN)
◎ All operands are 32-bit wide; come from registers or specified
as literal in the instruction itself
◎ Second operand sent to ALU via barrel shifter
◎ 32-bit result placed in register; long multiply instruction
produces 64-bit result
◎ 3-address instruction format
◎ 2 source operands and 1 destination register
◎ One source is always a register, the second may be a register, a
shifted register or an immediate value
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Program to generate square wave using GPIO
#include <LPC210x.H>
delay()
{
int i,j;
for(i = 1;i<= 500;i++)
for(j = 1; j<= 500;j++)
;
}
int main()
{
IODIR = 0x00000700;
while(1)
{
IOCLR = 0x00000700;
delay(); //delay
IOSET = 0x00000700;
delay(); //delay
}
}
MOVE INSTRUCTIONS
◎ <instruction>{<cond>} Rd, <operand2>
◎ Useful for setting values and transferring data
between registers
MOV r0,r2 ;r0:=r2
MVN r0,r2 ;r0:=NOT r2, move 1’s complement
MOV Move a 32 bit value into a register Rd =
operand2
MVN Move the NOT of the 32 bit value into a Rd =
register ~operand2
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SIMPLE REGISTER OPERANDS:
◎ Arithmetic Operations
ADD r0,r1,r2 ;r0:=r1+r2
ADC r0,r1,r2 ;r0:=r1+r2+C
SUB r0,r1,r2 ;r0:=r1–r2
SBC r0,r1,r2 ;r0:=r1–r2-C
RSB r0,r1,r2 ;r0:=r2–r1, reverse subtraction
RSC r0,r1,r2 ;r0:=r2–r1-C
◎ Bit-wise Logical Operations
AND r0,r1,r2 ;r0:=r1ANDr2
ORR r0,r1,r2 ;r0:=r1ORr2
EOR r0,r1,r2 ;r0:=r1XORr2
BIC r0,r1,r2 ;r0:=r1AND(NOT r2), bit clear Logical NAND
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IMMEDIATE OPERANDS
◎ Replace the second source operand with an
immediate operand, which is a literal constant,
preceded by “#”
ADD r3,r3,#1 ;r3:=r3+1
AND r8,r7,#&FF ;r8:=r7[7:0], &:hexadecimal
◎ Since the immediate value is coded within the 32 bits
of the instruction, it is not possible to enter every
possible 32-bit value as an immediate.
Immediate = (0 → 255) × 22n where
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SIMPLE REGISTER OPERANDS
◎ Comparison Operations
◉ Not produce result; omit the destination from the
format
◉ Just set the condition code bits (N, Z, C and V) in CPSR
CMP r1,r2 ;set cc on r1 - r2, compare
CMN r1,r2 ;set cc on r1 + r2, compare negated
TST r1,r2 ;set cc on r1 AND r2, bit test
TEQ r1,r2 ;set cc on r1 XOR r2, test equal
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BARREL SHIFTER
◎ Shift the 32 bit binary pattern
in one of the source registers
left or right by a specific
number of positions before it
enters the ALU
ARM SHIFT OPERATIONS
ARM SHIFT OPERATIONS
◎ LSL: logical shift left :Fill the vacated bits at the least
significant end of the word with zeroes.
◎ LSR: logical shift right :Fill the vacated bits at the most
significant end of the word with zeroes.
◎ ASL: arithmetic Left shift: This is synonym for LSL.
◎ ASR: arithmetic right shift: Fill the vacated bits at the most
significant end of the word with zeroes if the source operand is
positive , or with ones if the source operand was negative.
◎ ROR: rotate right: The bits which fall off the least significant
end of the word are used, in order, to fill the vacated bits at
the most significant end of the word.
◎ RRX: rotate right extended: The vacated bit (Bit 31) is filled
with the old value of the C flag and the operand is shifted one
place to the right.
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ARITHMETIC INSTRUCTIONS
◎ <instruction>{<cond>}{S} Rd, Rn, N
ADC Add two 32 bit values and carry Rd = Rn + N + carry
ADD Add two 32 bit values Rd = Rn + N
RSB Reverse subtract of two 32 bit values Rd = N – Rn
RSC Reverse subtract with carry of two 32 bit Rd = N – Rn -!(carry
values flag)
SBC Subtract with carry of two 32 bit values Rd = Rn -N–!(carry
flag)
SUB Subtract two 32 bit values Rd = Rn -N
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LOGICAL INSTRUCTIONS
◎ <instruction>{<cond>}{S} Rd, Rn, operand2
AND Logical bitwise AND of two 32 bit values Rd = Rn & operand2
ORR Logical bitwise OR of two 32 bit values Rd = Rn | operand2
EOR Logical exclusive OR of two 32 bit Rd = Rn ^ operand2
values
BIC Logical bit clear (AND NOT) Rd = Rn & ~ operand2
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COMPARE INSTRUCTIONS
◎ <instruction>{<cond>} Rn, operand2
CMN Compare negated Flag set as a result of Rn + operand2
CMP Compare Flag set as a result of Rn - operand2
TEQ Test for equality of two 32 Flag set as a result of Rn ^ operand2
bit values
TST Test bits of a 32 bit values Flag set as a result of Rn & operand2
◎ TST r0,r1,LS#2
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MULTIPLY INSTRUCTIONS
◎ MLA{<cond>}{S} Rd, Rm, Rs, Rn
◎ MUL{<cond>}{S} Rd, Rm, Rs
MLA Multiply & accumulate Rd = (Rm * Rs) + Rn
MUL Multiply Rd = Rm * Rs
◎ instruction>{<cond>}{S} RdLo, RdHi, Rm, Rs
SMLAL Signed multiply accumulate long [RdHi,RdLo]=[RdHi,RdLo] + (Rm * Rs)
SMULL Signed multiply long [RdHi,RdLo]=(Rm * Rs)
UMLAL Unsigned multiply accumulate [RdHi,RdLo]=[RdHi,RdLo] + (Rm * Rs)
long
UMULL Unsigned multiply long [RdHi,RdLo]=Rm * Rs
COMPARE INSTRUCTIONS
◎ They update the CPSR flag according to the result but
do not affect other registers
◎ CMP is effectively a subtract instruction with result
discarded
◎ TST is logical AND operation
◎ TEQ is logical EOR
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BRANCH INSTRUCTION
B Branch pc = <target address>
(Allows a conditional branch forward or backward u[to
32MB.). B Label
BCC Branch to label if carry flag is BCC Label
clear
BEQ Branch to label if ZERO flag is BEQ Label
SET
BL Subroutine call function BL FUNC
LDR PC =FUNC Load a 32 bit
value into the program
counter
BRANCH INSTRUCTION
B Branch pc = <target address>
(Allows a conditional branch forward or backward u[to
32MB.). B Label
BL Branch With Link pc = <target address>
lr = address of the next inst. After BL
BX Branch And Exchange pc = Rm & 0xfffffffe,
Instruction T = Rm & 1
(Branches the PC to Rm, with optional switch of Thumb
execution)
BLX Branch With Link And pc=label, T = 1,pc = Rm & 0xfffffffe,
Exchange T = Rm & 1,lr = address of the next inst. After BL
(use to call thumb subroutine from the arm instruction
set and address is specified in the instruction)
SINGLE REGISTER TRANSFER
LDR load word into a register Rd <-mem32[address] LDR R1,[R2]
STR save byte or word from a register Rd ->mem32[address]
LDRB load byte into a register Rd <-mem8[address] LDRB R1,[R2]
STRB save byte from a register Rd ->mem8[address]
LDRH load half word into a register Rd <-mem16[address] LDRH R1,[R2]
STRH save half word from a register Rd ->mem16[address]
LDRSB load signed byte into a register Rd <-SignExtend (mem8[address])
LDRSH load signed half word into a Rd <-SignExtend (mem16[address])
register
Program to generate square wave using GPIO
#include <LPC210x.H>
delay()
{
int i,j;
for(i = 1;i<= 500;i++)
for(j = 1; j<= 500;j++)
;
}
int main()
{
IODIR = 0x00000700;
while(1)
{
IOCLR = 0x00000700;
delay(); //delay
IOSET = 0x00000700;
delay(); //delay
}
}
SWAP INSTRUCTION
◎ Swaps the contents of memory with the contents of
a register
Ms. Rupali Mane
Program to generate square wave using GPIO
#include <LPC210x.H>
delay()
{
int i,j;
for(i = 1;i<= 500;i++)
for(j = 1; j<= 500;j++)
;
}
int main()
{
IODIR = 0x00000700;
while(1)
{
IOCLR = 0x00000700;
delay(); //delay
IOSET = 0x00000700;
delay(); //delay
}
}
Program to generate square wave using GPIO
#include <LPC210x.H>
delay()
{
int i,j;
for(i = 1;i<= 500;i++)
for(j = 1; j<= 500;j++)
;
}
int main()
{
IODIR = 0x00000700;
while(1)
{
IOCLR = 0x00000700;
delay(); //delay
IOSET = 0x00000700;
delay(); //delay
}
}
Program to generate square wave using GPIO
#include <LPC210x.H>
delay()
{
int i,j;
for(i = 1;i<= 500;i++)
for(j = 1; j<= 500;j++)
;
}
int main()
{
IODIR = 0x00000700;
while(1)
{
IOCLR = 0x00000700;
delay(); //delay
IOSET = 0x00000700;
delay(); //delay
}
}
Program to generate square wave using GPIO
#include <LPC210x.H>
delay()
{
int i,j;
for(i = 1;i<= 500;i++)
for(j = 1; j<= 500;j++)
;
}
int main()
{
IODIR = 0x00000700;
while(1)
{
IOCLR = 0x00000700;
delay(); //delay
IOSET = 0x00000700;
delay(); //delay
}
}
Program to generate square wave using GPIO
#include <LPC210x.H>
delay()
{
int i,j;
for(i = 1;i<= 500;i++)
for(j = 1; j<= 500;j++)
;
}
int main()
{
IODIR = 0x00000700;
while(1)
{
IOCLR = 0x00000700;
delay(); //delay
IOSET = 0x00000700;
delay(); //delay
}
}
Program to generate square wave using GPIO
#include <LPC210x.H>
delay()
{
int i,j;
for(i = 1;i<= 500;i++)
for(j = 1; j<= 500;j++)
;
}
int main()
{
IODIR = 0x00000700;
while(1)
{
IOCLR = 0x00000700;
delay(); //delay
IOSET = 0x00000700;
delay(); //delay
}
}
PROGRAM STRUCTURE
DIRECTIVES
ARM PROGRAMMING
FIND1’S COMPLIMENT OF A NUMBER
AREA, Program1, Code, Readonly, Entry
START
LDR R1,= Value1
LDR R2,[R1]
MVN R3, R2
LDR R1, =RESULT
STR R3, [R1]
END
VALUE DCD 00000001
RESULT DCD 11111110
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ADDITION OF TWO 32 BIT NO
AREA, add, Code, Readonly, Entry
LDR R1,= Value1
LDR R2, [R1]
LDR R1,= Value2
ADD R R2, [R1]
LDR R1,= Result
STR R3, [R1]
END
Value 1 DCD 11111111
Value 2 DCD 22222222
Result DCD 33333333 Ms. Rupali Mane
MULTIPLICATION OF TWO 32 BIT
NO
AREA, add, Code, Readonly, Entry
LDR R1,= Value1
LDR R2, [R1]
LDR R1,= Value2
LDR R3, [R1]
UMULL R5,R6,R3,R2
LDR R1,= Result
STR R6, [R1]
STRR R5,[R1,#04]
END
Value 1 DCD 11111111
Value 2 DCD 22222222
Result DCD
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BLOCK TRANSFER
AREA, blocktransfer, Code, Readonly,
Entry
LDR R1,= Block1
LDR R2, [R1]
LDR R1,= Block2
STR R2, [R1]
END
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ADDITION OF TWO 64 BIT NO.
AREA add,CODE,READONLY
ENTRY
START
LDR r0,=VALUE1
LDR r1,[r0]
LDR r2,[r0,#4]
LDR r0,=VALUE2
LDR r3,[r0]
LDR r4,[r0,#4]
ADDS r6,r2,r4
ADC r5,r1,r3
LDR r0,=RESULT
STR r5,[r0]
STR r6,[r0,#4]
END
VALUE1 DCD &11111111,&22222222
VALUE2 DCD &33333333,&44444444
RESULT DCD &44444444, &66666666 Ms. Rupali Mane
LARGEST NO
AREA MAX, CODE, READONLY
ENTRY
START
ADR R0, NUMBERS
MOV R2, #&0A
EOR R1,R1,R1
LOOP1
LDR R3, [R0]
CMP R3,R1
BCC LOOP2
MOV R1,R3
LOOP2
ADD R0,R0,#4
SUBS R2,R2,#1
BNE LOOP1
LDR R4,=RESULT
STR R1,[R4]
NUMBERS DCD
&032,&012,&039,&010,&020,&035,&022,&031,&033,&034
RESULT DCD 39
END
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SMALLEST NO.
AREA MAX, CODE, READONLY
ENTRY
START
ADR R0, NUMBERS
MOV R2, #&0A
EOR R1,R1,R1
LOOP1
LDR R3, [R0]
CMP R3,R1
BNC LOOP2
MOV R1,R3
LOOP2
ADD R0,R0,#4
SUBS R2,R2,#1
BNE LOOP1
LDR R4,=RESULT
STR R1,[R4]
NUMBERS DCD &032,&012,&039,&010,&020,&035,&022,&031,&033,&034
RESULT DCD 12
END
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QUESTIONS
◎ Explain EOR and BIC instructions of ARM 7 with examples
◎ Explain RSB and BCC instructions of ARM 7 with examples
◎ Explain CMP and TEQ instructions of ARM 7 with examples
◎ Explain MLA and MUL instructions of ARM 7 with examples
◎ Explain Load and Store instructions of ARM 7 with example
◎ Explain ADD R2,R3,R3LSL#2 and SMULL R3,R4,R2,R1
◎ Explain LDR and LDRB with example
◎ Explain Directives AREA,ENTRY and END with respect to ARM 7
◎ Explain the following ARM7TDMI architecture-based instructions a) CMP R1,R2 b)SWP
R1,R2,[R3] c) ADD R0,R1,R3 d)LDR R0,=Data
◎ Write an assembly language program for ARM7 to copy memory block from one block
BLOCK 1 to another block BLOCK2(Draw flowchart also)
◎ Explain instructions to perform AND OR XOR operations with example
◎ Explain branch instructions with example of ARM 7 with example
◎ Write an assembly language program for ARM7 to mask 8 to 15 bits of a number stored in
DATA1 and store the result in DATA2
◎ Write an assembly language program for ARM7 to perform AND and OR of two 32 bit
numbers stored at variables Data1& Data 2 and store the result at ANS1 and ANSW2(Draw
flowchart also)
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QUESTIONS
◎ Write an assembly language program for ARM7 to add two 64 bit numbers stored at
variables Data1& Data 2 and store the result at ANS(Draw flowchart also)
◎ Explain following instructions of ARM7 processor with example (considering values in
registers)
a) SMULL R4, R1, R2, R3
b) ADD R2, R1, R0
c) MLA R4, R3, R2, R1,
d) MVN R0, R2, LSL2
e) BEQ R1, R2
◎ Write an assembly language program for ARM7 to multiply two 32 bit numbers stored at
variables Data1& Data 2 and store the result at ANS(Draw flowchart also)
◎ Explain various addressing modes of ARM7 with example
◎ Write an assembly language program for ARM7 to find Largest number among 5 numbers
◎ Write an assembly language program for ARM7 to find smallest number among 5
numbers
◎ Write an assembly language program for ARM7 to divide 32 bit numbers by 8 bit number
stored at variables Data1& Data 2 and store the result at ANS(Draw flowchart also)
Ms. Rupali Mane