Offset and CMRR :
Random and systematic
Willy Sansen
KULeuven, ESAT-MICAS
Leuven, Belgium
[Link]@[Link]
Willy Sansen 10-05 151
Table of contents
• Random offset and CMRRr
• Systematic offset and CMRRs
• CMRR versus frequency
• Design rules
• Comparison MOST and bipolar transistors
Ref: Pelgrom, JSSC Oct.1989, 1433-1439
Croon, JSSC Aug.02, 1056-1064
Croon, Springer, 2005
Willy Sansen 10-05 152
Definition of offset
+ +
vOUT ≠ 0 vOUT = 0
- -
vOS
Offset voltage vos
Willy Sansen 10-05 153
Gain error with offset
RF = 100 kΩ
+
RS = 1 kΩ
vIN = vOUT = - 596 mV
10 mV
vOS =
4 mV
- Offset free
The gain is 59 instead of 100 !
Willy Sansen 10-05 154
Yield of n-bit flash-ADC with offset
Ref: Pelgrom, IEDM 1998, pp.789.
Willy Sansen 10-05 155
Random offset : mismatches
N W
IDS = K’ (VGS - VT)2
L
∆VT AVT
σ∆VT =
WL
4
0 VT VT AVT ~ tox NB
Ref: Keyes, JSSC Aug. 1975, 245-247 AVT ≈ 5 mVµm
Shyu, JSSC Dec 1984, 948-955
Lakshmikumar, JSSC Dec 1986, 1057-1066
for 0.25 µm nMOST
Pelgrom, JSSC Oct.1989, 1433-1439 +50 % for pMOST
Croon, JSSC Aug. 2002, 1056-1064
Willy Sansen 10-05 156
Threshold voltage sigma σ∆VT
mV
AVT
σ∆VT σ∆VT =
WL
σ (∆VT) ≈ 2 mV
W/L = 60/0.7 µm
in 0.7 µm CMOS
1/ WL
1/µm
Willy Sansen 10-05 157
Threshold voltage mismatch AVT
4
mVµm 40 AVT ~ tox NB
20
10
1 mVµm /nm tox
5
?
2.5
1.2
1.25 2.5 5 10 20 40 nm tox
0.06 0.13 0.18 0.25 0.35 0.5 0.7 1.2 2.4 µm L
Willy Sansen 10-05 158
Random offset : mismatches
∆K’ AK’
= AK’ ≈ 0.0056 µm +50 % for pMOST
K’ WL
∆W/L 1 1
= AWL + AWL ≈ 0.02 µm +50 % for pMOST
W/L W2 L2
∆γ Aγ
= Aγ ≈ 0.016 µm -25 % for pMOST
γ WL Negligible if B = S
Ref.: Pelgrom : JSSC Oct.1989, pp.1430-1440
Willy Sansen 10-05 159
Mismatch coefficients for nMOST
Techno L (µm) 2.5 1.2 0.7 0.5 0.35 0.25
tox (nm) 50 25 15 11 8 6
AVT (mV µm) 30 21 13 7.1 6 0
AWL (% µm) 2.5 1.8 2.5 1.3 2 1.8
SVT (mV/mm) 0.3 0.3 0.4 0.2
SWL (%/mm) 0.3 0.2 0.2
Willy Sansen 10-05 1510
Random offset in differential pair
IB
RL vod = ∆RL
RL+∆RL 2
vo1 vo2 vod
- + vos =
vod gmRL
∆RL IB
vos vos =
RL 2gm
IB
∆RL VGS - VT
vos =
RL 2
Ref.: Laker, Sansen : Design of analog …, MacGrawHill 1994
Willy Sansen 10-05 1511
Random offset in differential pair
RL RL+∆RL VGS - VT
vOS = ∆VT + (
vo1 vo2 2
- +
vod ∆K’ ∆W/L ∆VT ∆RL ∆K’ ∆W/L
+ + )
RL K’ W/L
vos
IB
small VGS - VT
Ref.: Laker, Sansen : Design of analog …, MacGrawHill 1994
Willy Sansen 10-05 1512
Random offset in current mirror
∆ Iout
iin =
Iout
iout
∆VT ∆K’ ∆W/L
+ +
M1 M2 (VGS - VT )/2 K’ W/L
∆K’ ∆W/L ∆VT
large VGS - VT
Ref.: Laker, Sansen : Design of analog …, MacGrawHill 1994
Willy Sansen 10-05 1513
More offset in current mirror
iin iin
iout1 2 iout1 2
M1 M1 M2 M3
M2 M3
RS
∆K’ ∆W/L ∆VT ∆K’ ∆W/L ∆VT RS
Willy Sansen 10-05 1514
Mismatch in drain current
β K’ W
IDS = (VGS - VT )2 β =
2 n L
∆IDS ∆β 2
= - ∆VT
IDS β VGS - VT
∆IDS ∆β 4
σ 2 ( ) = σ (
2 ) + σ (∆VT )
2
IDS β (VGS - VT )2
1
in wi
(nkT/q )2
gm
( )2 in general
IDS
Willy Sansen 10-05 1515
Mismatch in drain current for wi and si
∆IDS ∆β 4 1
σ 2 ( ) = σ (
2 ) + σ (∆VT )
2 or
IDS β (VGS - VT )2 (nkT/q )2
in si in wi
Willy Sansen 10-05 1516
Random CMRR in differential pair -1
RL vod = Add vid + Adc vic
RL+∆RL
voc = Acd vid + Acc vic
vo1 vo2
- +
vod ∆K’ ∆W/L
vinc vod
∆VT Add = = gm RL
vid v = 0
ic
vod
Adc = ≈0
vic v = 0
id
RB IB Add
CMRR = ≈∞
Adc
Willy Sansen 10-05 1517
Random CMRR in differential pair -2
vod
RL RL+∆RL Adc = ≠0
vic v = 0
id
vo1 vo2
ic/2
- + ic/2 vinc
vod vic = vinc ic =
vinc RB
vod = ∆RL ic/2
ic ∆RL 2 gm RB
Adc = CMRR =
RB IB 2 RB ∆RL/RL
Willy Sansen 10-05 1518
Random CMRR in differential pair -3
RL RL+∆RL
vo1 vo2
- +
vod ∆K’ ∆W/L
vinc ∆VT
CMRR =
2 gm RB
RB IB 2 ∆VT ∆RL ∆K’ ∆W/L
+ + +
VGS - VT RL K’ W/L
Willy Sansen 10-05 1519
Relation random offset and CMRR
VGS - VT ∆RL ∆K’ ∆W/L
vOSr = ∆VT + ( + + )
2 RL K’ W/L
2 gm RB
CMRRr =
2 ∆VT ∆RL ∆K’ ∆W/L
+ + +
VGS - VT RL K’ W/L
VGS - VT
vOSr CMRRr = 2 gm RB = IB RB = VELB = 5 … 15 V
2
vOSr CMRRr = 10 V
Willy Sansen 10-05 1520
Relation random offset and CMRR
vOSr CMRRr ≈ VELB ≈ 10 V ( ~ LB)
10 mV 60 dB ≈ 10 V as for MOSTs
1 mV 80 dB ≈ 10 V as for Bipolar transistors
10 µV 120 dB ≈ 10 V with trimming : with laser
with Zener zap
with fusible links
Low offset = High CMRR
Willy Sansen 10-05 1521
Table of contents
• Random offset and CMRRr
• Systematic offset and CMRRs
• CMRR versus frequency
• Design rules
• Comparison MOST and [Link]
Willy Sansen 10-05 1522
Systematic offset in current mirror
iDS ∆iout
iin
iout vGS
M1 M2
vDS1 vDS2 vDS
∆K’ ∆W/L ∆VT ∆iout vDS2 - vDS1
=
iout VEL2
Willy Sansen 10-05 1523
Systematic CMRR in differential Pair - 1
vinc iout 2
RB IB ic = =
RB ic gm3ro1
ic ∆K’ ∆W/L ∆VT
vosc ro1
M1 M2 ic/2 ic/2
+-
ic/2 vOUT
vinc
CL 1/gm3 iOUT
M3 M4
iOUT i i
∆K’ ∆W/L ∆VT
Willy Sansen 10-05 1524
Systematic CMRR in differential Pair - 2
RB IB iout 1 2
=
vinc RB gm3ro1
ic
vosc iout
= gm1
M1 M2 vosc
+-
ic/2 vind
vinc vOUT
iout
CL vinc Adc 1
M3 M4
iOUT = =
iout Add CMRRs
vosc
Willy Sansen 10-05 1525
Systematic CMRR in differential Pair - 3
iout 1
CMRRs = gm1RB gm3ro1
vinc vosc Adc 1 2
= = =
iout vinc Add CMRRs CMRRs vosc = vinc
vosc
vOUT = 0 vOUT = 0
vosc vinc
Willy Sansen 10-05 1526
Total CMRR
1 1 1
= +
CMRR CMRRr CMRRs
vOUT = 0 vOUT = 0
vosc vinc
Willy Sansen 10-05 1527
Offset Miller CMOS OTA
1 : B
Av1= gm1 r02//r04
M7
M5 ∆VDS1
vOS = +
4
vOUT Av1
- 3 M2 + Cc CL gm3
M1
∆VT1 + ∆VT3* +
gm1
+ ∆VDS1 -
VGS1 - VT
2 1 + S
M6
2
M3 M4
∆K’n ∆K’p ∆W/L1 ∆W/L3
S= + + +
K’n K’p W/L1 W/L3
Willy Sansen 10-05 1528
Offset Folded cascode CMOS OTA
∆VDS3
vOS = + ∆VT1 +
M9 M5 M6 Av
gm6 gm11
M1 M2 M7 + ∆VT5 + ∆VT11*
M8 gm1 gm1
- 3 + 4 vOUT
5
VGS1 - VT
+ ∆VDS3 -
M3 M4
+ S
+ CL 2
2 1
∆K’n ∆K’p ∆W/L1,6,11
S= + +
K’n K’p W/L1,6,11
M11
M10
Willy Sansen 10-05 1529
Table of contents
• Random offset and CMRRr
• Systematic offset and CMRRs
• CMRR versus frequency
• Design rules
• Comparison MOST and [Link]
Ref.: Laker, Sansen : Design of analog …, MacGrawHill 1994
Willy Sansen 10-05 1530
CMRR vs frequency
A CMRR 1
- + fB =
vod 2πRBCB
vinc Add
f
fB
Adc
IB
RB CB
CB ≈ CGS RB ≈ 100/gm >> fB ≈ fT/100
BUT CB includes Cwell, bulk !!!
Willy Sansen 10-05 1531
Table of contents
• Random offset and CMRRr
• Systematic offset and CMRRs
• CMRR versus frequency
• Design rules
• Comparison MOST and bipolar transistors
Willy Sansen 10-05 1532
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
Hastings,
9. End dummies “The Art of Analog Layout”
10. Bipolar always better ! Prentice Hall 2001
R. Soin, ..”A-D Asics, .. ”
Peregrinus, 1991
Willy Sansen 10-05 1533
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
9. End dummies
10. Bipolar always better !
Willy Sansen 10-05 1534
On same isotherm
Solomon, JSSC Dec 74, 314-332
Willy Sansen 10-05 1535
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
9. End dummies
10. Bipolar always better !
Willy Sansen 10-05 1536
Layout resistor
B R1 R2
Source/drain
p+
diffusion
n+
p resistor
W in CMOS
W
Ref.: Laker, Sansen :
Design of analog …,
MacGrawHill 1994
Table 2-6
Willy Sansen 10-05 1537
Table resistors
Willy Sansen 10-05 1538
Mismatch vs size for resistors
∆(R2/R1)
%
R2/R1 10
Local errors :
jagged edges, ..
3 Error ~ 1/size
Diffused
1
0.3
Ion-implanted
0.1
1 3 10 30 100 µm W
Willy Sansen 10-05 1539
Layout capacitors
B C1 C2
Poly to S/D capacitor
p+ n+
p
S
n+ poly
B C1 C2
Poly to poly capacitor
1
p+ Cpar ≈ Cpp
p
n+ 6 …15
Willy Sansen 10-05 1540
Table capacitors
Ref.: Laker, Sansen :
Design of analog …,
MacGrawHill 1994
Table 2-7
Willy Sansen 10-05 1541
Mismatch vs size for capacitors
∆(C2/C1)
%
C2/C1 1
Local errors :
Wet etched jagged edges, ..
0.3 Error ~ 1/size
Global errors :
0.1 oxide thickness,
bulk doping, ..
Dry etched
0.03
0.01
1 3 10 30 100 µm S
Willy Sansen 10-05 1542
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
9. End dummies
10. Bipolar always better !
Willy Sansen 10-05 1543
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
9. End dummies
10. Bipolar always better !
Willy Sansen 10-05 1544
Matching of transistor pairs
Bad Better Better
Willy Sansen 10-05 1545
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
9. End dummies
10. Bipolar always better !
Willy Sansen 10-05 1546
Matching of current mirrors
1 : 4
Willy Sansen 10-05 1547
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
9. End dummies
10. Bipolar always better !
Willy Sansen 10-05 1548
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
9. End dummies
10. Bipolar always better !
Willy Sansen 10-05 1549
Cross-coupled differential pair
Oxide
thickness
Less sensitive
to global variations :
Oxide thickness
Substrate doping level
……..
Willy Sansen 10-05 1550
Centroide layout of capacitors
Ratio:
1
2
4
8
16
Willy Sansen 10-05 1551
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
9. End dummies
10. Bipolar always better !
Willy Sansen 10-05 1552
Matching of current mirrors
Willy Sansen 10-05 1553
Layout capacitance ratio
Ratio 7/2 = 3.5
Courtesy Vittoz
Willy Sansen 10-05 1554
Layout rules for low offset
1. Equal nature
2. Same temperature
3. Increase size
4. Minimum distance
5. Same orientation
6. Same area/perimeter ratio
7. Round shape
8. Centroide layout
9. End dummies
10. Bipolar always better !
Willy Sansen 10-05 1555
Table of contents
• Random offset and CMRRr
• Systematic offset and CMRRs
• CMRR versus frequency
• Design rules
• Comparison MOST and bipolar transistors
Willy Sansen 10-05 1556
Offset of MOST and bipolar transistors
VGS - VT ∆RL ∆K’ ∆W/L
MOST : vOS = ∆VT + ( + + )
2 RL K’ W/L
kT ∆RL ∆IS
Bipolar : vOS = ( + ) is much smaller !!
q RL IS
1) no VT
2) kT/q << (VGS-VT)/2
∆ vOS vOS
3) Drift decreases with vOS : =
∆T T
Bipolar : Base current !
Willy Sansen 10-05 1557
Bias or base currents
Ibias
pA
Bipolar JFET or
1000 MOST with
protection diode :
100 X 2 every 8 oC
10
Super β Bipolar
1
MOST
0.1
5 25 45 65 85 105 oC T
Willy Sansen 10-05 1558
Base current compensation
OP07
Willy Sansen 10-05 1559
Common-mode base current compensation
OP27
Willy Sansen 10-05 1560
Tracking base current compensation
Q29 & Q30
provide a
voltage clamp
to track
the input
bias currents
for changes in
CM input voltage.
Ref. Gross, JSSC, Feb. 2004, 404.
Willy Sansen 10-05 1561
OP-97 : input current compensation
Low input currents
because
Q3 super- β transistors
Q1 Q2
at the input !
I2
Require low VCE !
I1 Q4
Q5 VCE1,2 = VBEon ≈ 0.7 V
I1 + I2
Willy Sansen 10-05 1562
OP-97 : input current compensation
2IB
Q3
≈0
Q1 Q2
IB IB
IB / β
IB / β
Q4 IB / β Same β and VCE
≈0
Q5 as input transistors
3IB IB
Willy Sansen 10-05 1563
Limits because of device mismatch
1 ∆IDS 4 AVT 2
≈ σ (
2 ) ≈
(Accuracy)2 IDS WL (VGS - VT )2
2 IDS VDD
Speed ≈ fT =
2π WL 2/3 Cox (VGS - VT ) 2
Speed x (Accuracy)2 1 1
= ~
Power Cox AVT2 tox
= Technological constant
Willy Sansen 10-05 1564
Limits because of device noise
Vpp2/ 2 Vpp2/ 8
S/N = S/N =
4kT R BW kT / C
Vpp2
Pmin = Pmin = VDD BW Vpp C
R
Pmin ≈ 8kT BW S/N
Willy Sansen 10-05 1565
Noise versus mismatch for high DR
Mismatch
Noise
Ref. [Link], ...
“Analog VLSI ..”
page 67,
Kluwer 1997.
Willy Sansen 10-05 1566
Reduced DR in deep submicron CMOS
Willy Sansen 10-05 1567
Table of contents
• Random offset and CMRRr
• Systematic offset and CMRRs
• CMRR versus frequency
• Design rules
• Comparison MOST and bipolar transistors
Ref: Pelgrom, JSSC Oct.1989, 1433-1439
Croon, JSSC Aug.02, 1056-1064
Croon, Springer, 2005
Willy Sansen 10-05 1568