0% found this document useful (0 votes)

15 views164 pages

Basic Debugging Training Manual

The document is a training manual for the TRACE32 debugging tool, detailing various debugging features, tools, and configurations. It covers topics such as on-chip debug interfaces, memory display, breakpoints, and debugging optimized code. Additionally, it provides guidance on starting a TRACE32 PowerView instance and configuring parameters for effective debugging.

Uploaded by

Anand Kopparthi

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

15 views164 pages

Basic Debugging Training Manual

Uploaded by

Anand Kopparthi

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

Training Basic Debugging

Release 09.2024

MANUAL
Training Basic Debugging

TRACE32 Online Help

TRACE32 Directory

TRACE32 Index

TRACE32 Training ............................................................................................................................ 

Debugger Training ........................................................................................................................ 

Training Basic Debugging ......................................................................................................... 1

System Concept ...................................................................................................................... 6

On-chip Debug Interface 7
Debug Features 7
TRACE32 Tools 8
On-chip Debug Interface plus On-chip Trace Buffer 10
On-chip Debug Interface plus Trace Port 12
NEXUS Interface 13

Starting a TRACE32 PowerView Instance ............................................................................. 14

Basic TRACE32 PowerView Parameters 14
Configuration File 14
Standard Parameters 15
Examples for Configuration Files 16
Additional Parameters 20
Application Properties (Windows only) 21
Configuration via T32Start (Windows only) 22
About TRACE32 23
Version Information 23
Prepare Full Information for a Support Email 24

TRACE32 PowerView .............................................................................................................. 25

TRACE32 PowerView Components 25
Main Menu Bar and Accelerators 26
Main Tool Bar 28
Window Area 30
Command Line 33
Message Line 36
Softkeys 37
State Line 38

Registers .................................................................................................................................. 39
Core Registers 39
Display the Core Registers 39
Colored Display of Changed Registers 40

©1989-2024 Lauterbach Training Basic Debugging | 2

Modify the Contents of a Core Register 41
Special Function Register 42
Display the Special Function Registers 42
Details about a Single Special Function Register 45
Modify a Special Function Register 46
The PER Definition File 47

Memory Display and Modification ......................................................................................... 48

The [Link] Window 49
Display the Memory Contents 49
Modify the Memory Contents 54
Run-time Memory Access 55
Colored Display of Changed Memory Contents 65
The List Window 66
Displays the Source Listing Around the PC 66
Displays the Source Listing of a Selected Function 67

Breakpoints .............................................................................................................................. 69
Breakpoint Implementations 69
Software Breakpoints in RAM 69
Software Breakpoints in FLASH 71
Onchip Breakpoints in NOR Flash 72
Onchip Breakpoints on Read/Write Accesses 75
Onchip Breakpoints by Processor Architecture 76
ETM Breakpoints for ARM or Cortex-A/-R 77
Breakpoint Types 80
Program Breakpoints 81
Read/Write Breakpoints 83

Breakpoint Handling ............................................................................................................... 85

Breakpoint Setting at Run-time 85
Real-time Breakpoints vs. Intrusive Breakpoints 86
[Link] Dialog Box 88
The HLL Check Box - Function Name 89
The HLL Check Box - Program Line Number 92
The HLL Check Box - Variable 94
The HLL Check Box - HLL Expression 96
Implementations 99
Actions 100
Options 104
DATA Breakpoints 108
Advanced Breakpoints 112
TASK-aware Breakpoints 113
Intrusive TASK-aware Breakpoint 113
Real-time TASK-aware Breakpoint 116

©1989-2024 Lauterbach Training Basic Debugging | 3

COUNTer 117
Software Counter 117
On-chip Counter 120
CONDition 121
CMD 129
memory/register/var 132
Display a List of all Set Breakpoints 137
Delete Breakpoints 138
Enable/Disable Breakpoints 138
Store Breakpoint Settings 139

Debugging ................................................................................................................................ 140

Debugging of Optimized Code 140
Basic Debug Control 143

Sample-based Profiling .......................................................................................................... 155

Program Counter Sampling 155
Standard Procedure 156
Details 160
TASK Sampling 162

©1989-2024 Lauterbach Training Basic Debugging | 4

Training Basic Debugging

Version 05-Oct-2024

©1989-2024 Lauterbach Training Basic Debugging | 5

System Concept

A single-core processor/multi-core chip can provide:

• An on-chip debug interface

• An on-chip debug interface plus an on-chip trace buffer

• An on-chip debug interface plus an off-chip trace port

• A NEXUS interface including an on-chip debug interface

Depending on the debug resources different debug features can be provided and different TRACE32 tools
are offered.

©1989-2024 Lauterbach Training Basic Debugging | 6

On-chip Debug Interface

The TRACE32 debugger allows you to test your embedded hardware and software by using the on-chip
debug interface. The most common on-chip debug interface is JTAG.

A single on-chip debug interface can be used to debug all cores of a multi-core chip.

Debug Features

Depending on the processor architecture different debug features are available.

Debug features provided by all processor architectures:

• Read/write access to registers

• Read/write access to memories

• Start/stop of program execution

Debug features specific for a processor architecture:

• Number of on-chip breakpoints

• Read/write access to memory while the program execution is running

• Additional features as benchmark counters, triggers etc.

©1989-2024 Lauterbach Training Basic Debugging | 7

TRACE32 Tools

The TRACE32 debugger hardware always consists of:

• Universal debugger hardware

• Debug cable specific to the processor architecture

Debug Only Modules

PC or
Workstation

Target

POWER DEBUG E40

Debug Cable

USB

Connector
Cable

Debug
POWER DEBUG E40

Current module:

• POWER DEBUG E40

Deprecated modules:

• POWER DEBUG INTERFACE / USB 3

• POWER DEBUG INTERFACE / USB 2

©1989-2024 Lauterbach Training Basic Debugging | 8

Debug Modules with Option for Off-chip Trace Extension

SWITCH PC or
Workstation

1 GBit Ethernet

Target

POWER DEBUG X50

Debug Cable
Ethernet
Cable

Connector
Debug

POWER DEBUG X50

Current module:

• POWER DEBUG X50

Deprecated modules:

• POWER DEBUG PRO (USB 3 and 1 GBit Ethernet)

• POWER DEBUG II (USB 2 and 1 GBit Ethernet)

• POWER DEBUG / ETHERNET (USB 2 and 100 MBit Ethernet)

©1989-2024 Lauterbach Training Basic Debugging | 9

On-chip Debug Interface plus On-chip Trace Buffer

A number of single-core processors/multi-core chips offer in addition to the on-chip debug interface an on-
chip trace buffer.

On-chip Trace Features

The on-chip trace buffer can store information:

• On the executed instructions.

• On task/process switches.

• On load/store operations if supported by the on-chip trace generation hardware.

In order to analyze and display the trace information the debug cable needs to provide a Trace License. The
Trace Licenses use the following name convention:

• <core>-TRACE e.g. ARM-TRACE

• or <core>-MCDS) e.g. TriCore-MCDS

©1989-2024 Lauterbach Training Basic Debugging | 10

The display and the evaluation of the trace information is described in the following training manuals:

• “Training Arm CoreSight ETM Tracing” (training_arm_etm.pdf).

• “Training Cortex-M Tracing” (training_cortexm_etm.pdf).

• “Training AURIX Tracing” (training_aurix_trace.pdf).

• “Training Hexagon ETM Tracing” (training_hexagon_etm.pdf).

• “Training MPC5xxx/SPC5xx Nexus Tracing” (training_nexus_mpc5500.pdf).

©1989-2024 Lauterbach Training Basic Debugging | 11

On-chip Debug Interface plus Trace Port

A number of single-core processors/multi-core chips offer in addition to the on-chip debug interface a so-
called trace port. The most common trace port is the TPIU for the ARM/Cortex architecture.

Off-chip Trace Features

The trace port exports in real-time trace information:

• On the executed instructions.

• On task/process switches.

• On load/store operations if supported by the on-chip trace generation logic.

The display and the evaluation of the trace information is described in the following training manuals:

• “Training Arm CoreSight ETM Tracing” (training_arm_etm.pdf)

• “Training Cortex-M Tracing” (training_cortexm_etm.pdf)

• “Training AURIX Tracing” (training_aurix_trace.pdf)

• “Training Hexagon ETM Tracing” (training_hexagon_etm.pdf)

©1989-2024 Lauterbach Training Basic Debugging | 12

NEXUS Interface

NEXUS is a standardized interface for on-chip debugging and real-time trace especially for the automotive
industry.

NEXUS Features

Debug features provided by all single-core processors/multi-core chips:

• Read/write access to the registers

• Read/write access to all memories

• Start/stop of program execution

• Read/write access to memory while the program execution is running

Debug features specific for single-core processor/multi-core chip:

• Number of on-chip breakpoints

• Benchmark counters, triggers etc.

Trace features provided by all single-core processors/multi-core chips:

• Information on the executed instructions.

• Information on task/process switches.

Trace features specific for the single-core processor/multi-core chip:

• Information on load/store operations if supported by the trace generation logic.

The display and the evaluation of the trace information is described in “Training MPC5xxx/SPC5xx Nexus
Tracing” (training_nexus_mpc5500.pdf).

©1989-2024 Lauterbach Training Basic Debugging | 13

Starting a TRACE32 PowerView Instance

Basic TRACE32 PowerView Parameters

This chapter describes the basic parameters required to start a TRACE32 PowerView instance.

The parameters are defined in the configuration file. By default the configuration file is named config.t32. It
is located in the TRACE32 system directory (parameter SYS).

Configuration File

Open the file config.t32 from the system directory (default c:\T32\config.t32) with any ASCII editor.

The following rules apply to the configuration file:

• Parameters are defined paragraph by paragraph.

• The first line/headline defines the parameter type.

• Each parameter definition ends with an empty line.

• If no parameter is defined, the default parameter will be used.

©1989-2024 Lauterbach Training Basic Debugging | 14

Standard Parameters

Parameter Syntax Description

Host interface PBI= Host interface type of TRACE32 tool

<host_interface> hardware (USB or ethernet)

PBI=ICD Full parameter syntax which is not in use.

<host_interface>

Environment OS=
variables ID=<identifier> (ID) Prefix for all files which are saved by
TMP=<temp_directory> the TRACE32 PowerView instance into the
SYS=<system_directory> TMP directory
HELP=<help_directory>
(TMP) Temporary directory used by the
TRACE32 PowerView instance (*)

(SYS) System directory for all TRACE32

files

(HELP) Directory for the TRACE32 help

PDFs (**)

Printer PRINTER=WINDOWS All standard Windows printer can be used

definition from TRACE32 PowerView

License file LICENSE=<license_directory> Directory for the TRACE32 license file

(not required for new tools)

(*) In order to display source code information TRACE32 PowerView creates a

copy of all loaded source files and saves them into the TMP directory.

(**) The TRACE32 online help is PDF-based.

©1989-2024 Lauterbach Training Basic Debugging | 15

Examples for Configuration Files

Configuration File for USB

Single debugger hardware module connected via USB:

; Host interface
PBI=
USB

; Environment variables
OS=
ID=T32
TMP=C:\temp ; temporary directory for TRACE32
SYS=C:\t32 ; system directory for TRACE32
HELP=C:\t32\pdf ; help directory for TRACE32

; Printer settings
PRINTER=WINDOWS ; all standard windows printer can be
; used from the TRACE32 user interface

Multiple debugger hardware modules connected via USB:

; Host interface
PBI=
USB
NODE=training1 ; NODE name of TRACE32

; Environment variables
OS=
ID=T32_training1
TMP=C:\temp ; temporary directory for TRACE32
SYS=C:\t32 ; system directory for TRACE32
HELP=C:\t32\pdf ; help directory for TRACE32

; Printer settings
PRINTER=WINDOWS ; all standard windows printer can be
; used from TRACE32 PowerView

©1989-2024 Lauterbach Training Basic Debugging | 16

Use the IFCONFIG command to assign a device name (NODE=) to a debugger hardware module. The
manufacturing default device name is the serial number of the debugger hardware module:

• e.g. E18110012345 for a debugger hardware module with ethernet interface, such as PowerDebug
PRO.

• e.g. C18110045678 for a debugger hardware module with USB interface only, such as PowerDebug
USB 3.

Enter device name

Save device name to

debugger hardware module

IFCONFIG Dialog to assign USB device name

Please be aware that USB device names are case-sensitive

©1989-2024 Lauterbach Training Basic Debugging | 17

Remote Control for POWER DEBUG INTERFACE / USB

TRACE32 allows to communicate with a POWER DEBUG INTERFACE USB from a remote PC. For an
example, see “Example: Remote Control for POWER DEBUG INTERFACE / USB” in TRACE32
Installation Guide, page 46 ([Link]).

©1989-2024 Lauterbach Training Basic Debugging | 18

Configuration File for Ethernet

; Host interface
PBI=
NET
NODE=training1

; Environment variables
OS=
ID=T32 ; temp directory for TRACE32
SYS=C:\t32 ; system directory for TRACE32
HELP=C:\t32\pdf ; help directory for TRACE32

; Printer settings
PRINTER=WINDOWS ; all standard windows printer can be
; used from the TRACE32 user interface

Ethernet Configuration and Operation Profile

IFCONFIG Dialog to display and change information for the Ethernet interface

©1989-2024 Lauterbach Training Basic Debugging | 19

Additional Parameters

Changing the font size can be helpful for a more comfortable display of TRACE32 windows.

; Screen settings
SCREEN=
FONT=SMALL ; Use small fonts

Display with normal font:

Display with small font:

©1989-2024 Lauterbach Training Basic Debugging | 20

Application Properties (Windows only)

The Properties window allows you to configure some basic settings for the TRACE32 software.

To open the Properties window, right-click the desired TRACE32 icon in the Windows Start menu.

Configuration File

Working Directory

Window Size

Definition of the Configuration File

By default the configuration file config.t32 in the TRACE32 system directory (parameter SYS) is used. The
option -c allows you to define your own location and name for the configuration file.

C:\T32_ARM\bin\windows\[Link] -c j:\and\config.t32

Definition of a Working Directory

After its start TRACE32 PowerView is using the specified working directory. It is recommended not to work in
the system directory.

PWD TRACE32 command to display the current working directory

Definition of the Window Size for TRACE32 PowerView

You can choose between Normal window, Minimized and Maximized.

©1989-2024 Lauterbach Training Basic Debugging | 21

Configuration via T32Start (Windows only)

The basic parameters can also be set up in an intuitive way via T32Start.

A detailed online help for [Link] is available via the Help button or in “T32Start” (app_t32start.pdf).

Parameters

©1989-2024 Lauterbach Training Basic Debugging | 22

About TRACE32

If you want to contact your local Lauterbach support, it might be helpful to provide some basis information
about your TRACE32 tool.

Version Information

The VERSION window informs you about:

1. The version of the TRACE32 software.

2. The debug licenses programmed into the debug cable and the expiration date of your software
warranty respectively the expiration date of your software warranty.

3. The serial number of the debug cable.

[Link] Display the VERSION window.

[Link] Display more details about the TRACE32 hardware modules.
[Link] Display more details about the TRACE32 software.

©1989-2024 Lauterbach Training Basic Debugging | 23

Prepare Full Information for a Support Email

Be sure to include detailed system information about your TRACE32 configuration.

1. To generate a system information report, choose Help > Support > Systeminfo.

2. Preferred: click Save to File, and send the system information as an attachment to your e-mail.

3. Click Save to Clipboard, and then paste the system information into your e-mail.

©1989-2024 Lauterbach Training Basic Debugging | 24

TRACE32 PowerView

TRACE32 PowerView Components

Main Menu Bar

Main Tool Bar

Local Buttons

Window Area

Context Menu

Command Line
Message Line
SoftkeyLine
State Line

The structure of the menu bar and the tool bar are defined by the file [Link]
which is located in the TRACE32 system directory.

TRACE32 allows you to modify the menu bar and the tool bar so they will better
fit your requirements. Refer to “Training Menu Programming”
(training_menu.pdf) for details.

©1989-2024 Lauterbach Training Basic Debugging | 25

Main Menu Bar and Accelerators

The main menu bar provides all important TRACE32 functions sorted by groups.

For often used commands accelerators are defined.

Accelerators

©1989-2024 Lauterbach Training Basic Debugging | 26

A user specific menu can be defined very easily:

[Link] <name> <command> Add a user menu

[Link] Reset menu to default

; user menu
[Link] "Set PC to main" "[Link] PC main"

; user menu with accelerator

[Link] "Set PC to main, ALT+F10" "[Link] PC main"

User Menu

For more complex changes to the main menu bar refer to “Training Menu
Programming” (training_menu.pdf).

Videos about the menu programming can be found here:

[Link]/kb/articles/trace32-user-interface-customization

©1989-2024 Lauterbach Training Basic Debugging | 27

Main Tool Bar

The main tool bar provides fast access to often used commands.

The user can add his own buttons very easily:

[Link] <tooltip_text> <tool_image> <command> Add a button to the toolbar

[Link] Reset menu to default

; <tooltip text> here: Set PC to main

; <tool image> here: button with capital letters PM in black
; <command> here: [Link] PC main

[Link] "Set PC to main" "PM,X" "[Link] PC main"

User specific
button

Information on the <tool image> can be found in Help -> Contents

TRACE32 Documents -> IDE User Interface -> PowerView Command Reference -> MENU ->
Programming Commands -> TOOLITEM.

©1989-2024 Lauterbach Training Basic Debugging | 28

All predefined TRACE32 icons can be inspected as follows:

Or by following TRACE32 command:

[Link] ~~/demo/menu/internal_icons.cmm

The predefined icons can easily be used to create new icons.

; overprint the icon colorpurple with the character v in White color

[Link] "Set PC to main" "v,W,colorpurple" "[Link] PC main"

For more complex changes to the main tool bar refer to “Training Menu
Programming” (training_menu.pdf).

Videos about the menu programming can be found here:

[Link]/kb/articles/trace32-user-interface-customization

©1989-2024 Lauterbach Training Basic Debugging | 29

Window Area

Save Page Layout

No information about the window layout is saved when you exit TRACE32 PowerView. To save the window
layout use the Store Windows to … command in the Window menu.

Store Windows to … generates a script, that

allows you to reactivate the window-configuration
at any time.

Script example:

// andT32_1000003 Sat Jul 21 16:59:55 2012

B::

TOOLBAR ON
STATUSBAR ON
FramePOS 68.0 5.2857 107. 45.
[Link]

WinCLEAR
WinPOS 0.0 0.0 80. 16. 15. 1. W000
WinTABS 10. 10. 25. 62.
List

WinPOS 0.0 21.643 80. 5. 25. 1. W001

WinTABS 13. 0. 0. 0. 0. 0. 0.
[Link]

[Link] P000

ENDDO

©1989-2024 Lauterbach Training Basic Debugging | 30

Run the script to reactivate the stored
window-configuration

©1989-2024 Lauterbach Training Basic Debugging | 31

Modify Window

The window header

displays the command
which was executed to
open the window

By clicking with the right

mouse button to the window
header, the command which
was executed to open the
window is re-displayed in the
command line and can be
modified there

©1989-2024 Lauterbach Training Basic Debugging | 32

Command Line

Command line

Command Structure

Device prompt: the default device prompt is B::. It stands for BDM which was the first on-chip debug
interface supported by Lauterbach.

A TRACE32 command has the following structure:

[Link] 0x1000--0x1fff /Byte

Option(s)

Parameter(s)
Subcommand
Command group

©1989-2024 Lauterbach Training Basic Debugging | 33

Command Examples

Data Command group to display, modify … memory

[Link] Displays a hex dump

[Link] Modify memory

[Link] Loads code to the target memory

Break Command group to set, list, delete … breakpoints

[Link] Sets a breakpoint

[Link] Lists all set breakpoint

[Link] Deletes a breakpoint

Each command can be abbreviated. The significant letters are always written in upper case letters.

Examples for the parameter syntax and the use of options will be presented throughout this training.

©1989-2024 Lauterbach Training Basic Debugging | 34

The Online Help for a Specific Command

Enter the command to the command line.

Add one blank.
Push F1 to get the online help for the specified command.

©1989-2024 Lauterbach Training Basic Debugging | 35

Message Line

Message Area

Message Line

• Message line for system and error messages

• Message Area window for the display of the last system and error messages

©1989-2024 Lauterbach Training Basic Debugging | 36

Softkeys

The softkey line allows to enter a specific command step by step. Here an example:

Select the command group, here Data.

Select the subcommand, here dump.

Angle brackets request an entry from the user,

here e.g. the entry of a <range> or an <address>.

The display of the hex. dump can be adjusted to your needs by an option.

Select the option formats to get a list of all format options.

Select a format option, here Byte.

The command is complete now.

©1989-2024 Lauterbach Training Basic Debugging | 37

State Line

Cursor Debug Mode

field field field

The Cursor field of the state line provides:

• Boot information (Booting …, Initializing … etc.).

• Information on the item selected by one of the TRACE32 PowerView cursors.

The Debug field of the state line provides:

• Information on the debug communication (system down, system ready etc.)

• Information on the state of the debugger (running, stopped, stopped at breakpoint etc.)

The Mode field of the state line indicates the debug mode. The debug mode defines how source code
information is displayed.

• Asm = assembler code

• Hll = programming language code/high level language

• Mix = a mixture of both

It also defines how single stepping is performed (assembler line-wise or programming language
line-wise).

The debug mode can be changed by using the Mode pull-down.

©1989-2024 Lauterbach Training Basic Debugging | 38

Registers

Core Registers

Display the Core Registers

[Link]

©1989-2024 Lauterbach Training Basic Debugging | 39

Colored Display of Changed Registers

The option /SpotLight advises TRACE32 PowerView to mark changes.

[Link] /SpotLight ; The registers changed by the last

; step are marked in dark red.

; The registers changed by the

; step before the last step are
; marked a little bit lighter.

; This works up to a level of 4.

Establish /SpotLight as default setting

[Link] %SpotLight Establish the option SpotLight as default setting for

- all Variable windows
- Register window
- PERipheral window
- the HLL Stack Frame
- [Link] window

©1989-2024 Lauterbach Training Basic Debugging | 40

Modify the Contents of a Core Register

By double clicking to the register contents

a [Link] command is automatically displayed
in the command line.
Enter the new value and press return to modify the
register contents.

[Link] <register> <value> Modify register

©1989-2024 Lauterbach Training Basic Debugging | 41

Special Function Register

Display the Special Function Registers

TRACE32 supports a free configurable window to display/manipulate configuration registers and the on-chip
peripheral registers at a logical level. Predefined peripheral files are available for most standard
processors/chips.

Tree Display

The individual configuration registers/on-chip peripherals are organized by TRACE32 PowerView in a tree
structure. On demand, details about a selected register can be displayed.

Please be aware, that TRACE32 permanently updates all windows. The default
update rate is 10 times per second.

©1989-2024 Lauterbach Training Basic Debugging | 42

Full Display

Sometimes it might be useful to expand the tree structure from the start.

Use the right mouse and

select Show all

Commands:

[Link] <filename> [<tree_item>] Display the configuration registers/on-chip peripherals

; Display all functional units in expanded mode

; , advises TRACE32 PowerView to use the default peripheral file
; * stands for all <tree-items>
[Link] , "*"

©1989-2024 Lauterbach Training Basic Debugging | 43

; Display the functional unit "ID Registers" within "Core Registers"
; in expanded mode
[Link] , "Core Registers,ID Registers"

; Display the functional unit "DMA_Channel_0" within "sDMA_Module,sDMA"

; in expanded mode
[Link] , "sDMA_Module,sDMA,DMA_Channel_0"

The following command sequence can be used to save the contents of all configuration registers/on-chip
peripheral registers to a file.

; [Link] ASCIIE ; Select ASCII ENHANCED as output

; format
; (default output format)

[Link] [Link] ; Define [Link] as output file

[Link] ; Save contents of all

; configuration registers/on-chip
; peripheral registers to the
; specified file

©1989-2024 Lauterbach Training Basic Debugging | 44

Details about a Single Special Function Register

The access class, address, bit position and the full name of the selected item are
displayed in the state line; the full name of the selected item is taken from the
processor/chip manual.

©1989-2024 Lauterbach Training Basic Debugging | 45

Modify a Special Function Register

You can modify the contents of a configuration/on-chip peripheral register:

• By pressing the right mouse button and selecting one of the predefined values from the pull-
down menu.

• By a double-click to a numeric value. A [Link] command to change the contents of the

selected register is displayed in the command line. Enter the new value and confirm it with return.

[Link] <address>|<range> [%<format>] <value> Modify configuration register/on-

chip peripheral
[Link] <address>|<range> [%<format>] <value> Modify memory

[Link] is equivalent to [Link] if the configuration register is memory mapped.

[Link] D:0xF87FFF10 %Long 0x00000b02

©1989-2024 Lauterbach Training Basic Debugging | 46

The PER Definition File

The layout of the PER window is described by a PER definition file.

The definition can be changed to fit to your requirements using the PER command group.

The path and the version of the actual PER definition file can be displayed by using:

[Link]

[Link] <filename> Display the configuration registers/on-chip peripherals specified by

[Link] C:\T32_ARM\[Link]

©1989-2024 Lauterbach Training Basic Debugging | 47

Memory Display and Modification

This training section introduces the most often used methods to display and modify memory:

• The [Link] command, that displays a hex dump of a memory area, and
the [Link] command that allows to modify the contents of a memory address.

• The [Link] command, that displays the memory contents as source code listing.

A so-called access class is always displayed together with a memory address. The following access
classes are available for all processor architectures:

P:1000 Program address 0x1000

D:6814 Data address 0x6814

For additional access classes provided by your processor architecture refer to your “Processor
Architecture Manuals”.

©1989-2024 Lauterbach Training Basic Debugging | 48

The [Link] Window

Display the Memory Contents

©1989-2024 Lauterbach Training Basic Debugging | 49

Use an Address to Specify the Start Address for the [Link] Window

Please be aware, that TRACE32 permanently updates all windows. The default
update rate is 10 times per second.

©1989-2024 Lauterbach Training Basic Debugging | 50

Use an Address Range to Specify the Addresses for the [Link] Window

If you enter an address range, only data for the specified address range are displayed. This is useful if a
memory area close to memory-mapped I/O registers should be displayed and you do not want TRACE32
PowerView to generate read cycles for the I/O registers.

Conventions for address ranges:

• <start_address>--<end_address>

• <start_address>..<end_address>

• <start_address>++<offset_in_byte>

• <start_address>++<offset_in_word> (for DSPs)

©1989-2024 Lauterbach Training Basic Debugging | 51

Use a Symbol to Specify the Start Address for the [Link] Window

Use i to select any symbol name or label known to TRACE32 PowerView.

By default an oriented display

is used (line break at 2x).
A small arrow indicates
the specified dump address.

©1989-2024 Lauterbach Training Basic Debugging | 52

[Link] <address> | <range> [/<option>] Display a hex dump of the memory

[Link] 0x6814 ; Display a hex dump starting at

; address 0x6814

[Link] 0x6810--0x682f ; Display a hex dump of the

; specified address range

[Link] 0x6810..0x682f ; Display a hex dump of the

; specified address range

[Link] 0x6810++0x1f ; Display a hex dump of the

; specified address range

[Link] ast ; Display a hex dump starting at

; the address of the label ast

[Link] ast /Byte ; Display a hex dump starting at

; the address of the label ast in
; byte format

©1989-2024 Lauterbach Training Basic Debugging | 53

Modify the Memory Contents

By a left mouse double-click to the memory contents

a [Link] command is automatically
displayed in the command line,
you can enter the new value and
confirm it with return.

[Link] <address>|<range> [%<format>] <value> [/<option>]

[Link] 0x6814 0xaa ; Write 0xaa to the address

; 0x6814

[Link] 0x6814 %Long 0xaaaa ; Write 0xaaaa as a 32 bit value to

; the address 0x6814, add the
; leading zeros automatically

[Link] 0x6814 %LE %Long 0xaaaa ; Write 0xaaaa as a 32 bit value to

; the address 0x6814, add the
; leading zeros automatically

; Use Little Endian mode

©1989-2024 Lauterbach Training Basic Debugging | 54

Run-time Memory Access

TRACE32 PowerView updates the displayed memory contents by default only if the cores is stopped.

A hatched window frame

indicates that the information
display is brozen because the
core is executing the program.

The plain window frame

indicates that the information
is updated, because the
program execution is
stopped.

©1989-2024 Lauterbach Training Basic Debugging | 55

Non-intrusive Run-time Memory Access

Various cores allow a debugger to read and write physical memory (not cache) while the core is executing
the program. The debugger has in most cases direct access to the processor/chip internal bus, so no extra
load for the core is generated by this feature.

Open the SYStem window in order to check if your processor architecture allows a debugger to read/write
memory while the core is executing the program:

MemAccess Enable/NEXUS/DAP
indicates that the core allows
the debugger to read/write the
memory while the core is
executing the program.

Please be aware that caches, MMUs, tightly-coupled memories and suchlike add conditions to the run-time
memory access or at worst make its use impossible.

Restrictions

The following description is only a rough overview on the restrictions. Details about your core can be found in
the Processor Architecture Manual.

©1989-2024 Lauterbach Training Basic Debugging | 56

Cache

If run-time memory access for a cached memory location is enabled the debugger acts as follows:

• Program execution is stopped

The data is read via the cache respectively written via the cache.

• Program execution is running

Since the debugger has no access to the caches while the program execution is running, the
data is read from physical memory. The physical memory contains the current data only if the
cache is configured as write-through for the accessed memory location, otherwise out-dated data
is read.
Since the debugger has no access to the cache while the program execution is running, the data
is written to the physical memory. The new data has only an effect on the current program
execution if the debugger can invalidate the cache entry for the accessed memory location. This
useful feature is not available for most cores.

MMU

Debuggers have no access to the TLBs while the program execution is running. As a consequence run-time
memory access can not be used, especially if the TLBs are dynamically changed by the program.

In the exceptional case of static TLBs, the TLBs can be scanned into the debugger. This scanned copy of
the TLBs can be used by the debugger for the address translation while the program execution is running.

Tightly-coupled Memory

Tightly-coupled memory might not be accessible via the system memory bus.

Usage

The usage of the non-intrusive run-time memory access has to be configured explicitly. Two methods are
provided:

• Configure the run-time memory access for a specific memory area.

• Configure run-time memory access for all windows that display memory contents (not available
for all processor architectures).

©1989-2024 Lauterbach Training Basic Debugging | 57

Configure the run-time memory access for a specific memory area:

Enable the E check box to switch

the run-time memory access to ON

A plain window frame

indicates that the
information is updated
while the core is
executing the program

If the E check box is enabled, the attribute E is added to the memory class:

EP:1000 Program address 0x1000 with run-time memory access

ED:6814 Data address 0x6814 with run-time memory access

Write accesses to the memory work correspondingly:

[Link] via run-time

memory access
(attribute E)

©1989-2024 Lauterbach Training Basic Debugging | 58

[Link] Enable ; Enable the non-intrusive
; run-time memory access

;…

Go ; Start program execution

[Link] E:0x6814 ; Display a hex dump starting at

; address 0x6814 via run-time
; memory access

[Link] E:0x6814 0xAA ; Write 0xAA to the address

; 0x6814 via run-time memory
; access

©1989-2024 Lauterbach Training Basic Debugging | 59

Configure the run-time memory access for all windows that display memory
(not available for all cores):

If MemAccess Enable/NEXUS/DAP is
selected and DUALPORT is checked,
run-time memory is configured for
all windows that display memory

All windows that display memory

have a plain window frame,
because they are updated while
the core is executing the program

Write access is possible for all

memories while the core is
executing the program

©1989-2024 Lauterbach Training Basic Debugging | 60

[Link] Enable ; Enable the non-intrusive
; run-time memory access

[Link] ON ; Activate the run-time memory

; access for all windows that
; display memory

; this [Link] is only

; available for some processor
; architectures

;…

Go ; Start program execution

[Link] 0x6814 ; Display a hex dump starting at

; address 0x6814 via run-time
; memory access

[Link] 0x6814 0xAA ; Write 0xAA to the address

; 0x6814 via run-time memory
; access

©1989-2024 Lauterbach Training Basic Debugging | 61

Intrusive Run-Time Memory Access

If your processor architecture doesn’t allow a debugger to read or write memory while the core is executing
the program, you can activate an intrusive run-time memory access if required.

CpuAccess Enable allows an

intrusive run-time memory access

If an intrusive run-time memory access is activated, TRACE32 stops the program execution periodically to
read/write the specified memory area. Each update takes at least 50 us.

core(s) is core(s) is stopped to allow

executing the program TRACE32 PowerView to read/write
the specified memory

The time taken by a short stop depends on various factors:

• The time required by the debugger to start and stop the program execution on a processor/core
(main factor).

• The number of cores that need to be stopped and restarted.

• Cache and MMU assesses that need to be performed to read the information of interest.

• The type of information that is read during the short stop.

©1989-2024 Lauterbach Training Basic Debugging | 62

An intrusive run-time memory access is only possible for a specific memory area.

Enable the E check box to switch

the run-time memory access to ON

A plain window frame

indicates that the
information is updated
while the core(s) is
executing the program

A red S in the state line indicates that a TRACE32 feature is

activated that requires short-time stops of the program execution

Write accesses to the memory work correspondingly:

[Link] via run-time

memory access with short
stop of the program
execution

©1989-2024 Lauterbach Training Basic Debugging | 63

[Link] Enable ; Enable the intrusive
; run-time memory access

;…

Go ; Start program execution

[Link] E:0x6814 ; Display a hex dump starting at

; address 0x6814 via an intrusive
; run-time memory access

[Link] E:0x6814 0xAA ; Write 0xAA to the address

; 0x6814 via an intrusive
; run-time memory access

©1989-2024 Lauterbach Training Basic Debugging | 64

Colored Display of Changed Memory Contents

Enable the option SpotLight to mark the

memory contents changed by the last 4 single
steps in orange, older changes being lighter.

[Link] flags /SpotLight ; Display a hex dump starting at

; the address of the label flags

; Mark changes

©1989-2024 Lauterbach Training Basic Debugging | 65

The List Window

Displays the Source Listing Around the PC

If MIX mode is selected for

debugging, assembler and HLL
information is displayed

If HLL mode is selected for

debugging, only HLL
information is displayed

©1989-2024 Lauterbach Training Basic Debugging | 66

Displays the Source Listing of a Selected Function

Select the function you

want to display

[Link] [<address>] [/<option>] Display source listing

©1989-2024 Lauterbach Training Basic Debugging | 67

List ; Display a source listing
; around the PC

List E: ; Display a source listing,

; allow scrolling while the
; program execution is running

List * ; Open the symbol browser to

; select a function for display

List func17 ; Display a source listing of

; func17

©1989-2024 Lauterbach Training Basic Debugging | 68

Breakpoints

Videos about the breakpoint handling can be found here:

[Link]/kb/articles/using-breakpoints-in-trace32

Breakpoint Implementations

A debugger has two methods to realize breakpoints: Software breakpoints and Onchip breakpoints.

Software Breakpoints in RAM

The default implementation for breakpoints on instructions is a Software breakpoint. If a Software breakpoint
is set the original instruction at the breakpoint address is patched by a special instruction (usually TRAP) to
stop the program and return the control to the debugger.

©1989-2024 Lauterbach Training Basic Debugging | 69

The number of software breakpoints is unlimited.
.

Breakpoints on instructions are called Program breakpoints by TRACE32 PowerView.

Please be aware that TRACE32 PowerView always tries to set an Onchip

breakpoint, when the setting of a Software Breakpoint fails.

©1989-2024 Lauterbach Training Basic Debugging | 70

Software Breakpoints in FLASH

TRACE32 allows to set Software breakpoints to FLASH. Please be aware that the affected FLASH sector
has to be erased and programmed in order to patch the break instruction used by the Software breakpoint.
This usually takes some time and reduces the number of FLASH erase cycles. For details refer to
“Software Breakpoints in FLASH” ([Link]).

©1989-2024 Lauterbach Training Basic Debugging | 71

Onchip Breakpoints in NOR Flash

Most core(s) provide a small number of Onchip breakpoints in form of breakpoint registers. These Onchip
breakpoints can be used to set breakpoints to instructions in read-only memory like onchip or NOR FLASH.

©1989-2024 Lauterbach Training Basic Debugging | 72

Since Software breakpoints are used by default for Program breakpoints, TRACE32 PowerView can be
informed explicitly where to use Onchip breakpoints. Depending on your memory layout, the following
methods are provided:

1. If the code is completely located in read-only memory, the default implementation for the
Program breakpoints can be changed.

Change the implementation of Program breakpoints to Onchip

[Link] Program Onchip Advise TRACE32 PowerView to

implement Program breakpoints
always as Onchip breakpoints

©1989-2024 Lauterbach Training Basic Debugging | 73

2. If the code is located in RAM and onchip/NOR FLASH you can define code ranges where
Onchip breakpoints are used.

[Link] <range> Advise TRACE32 PowerView to implement Program

breakpoints as Onchip breakpoints within the defined
address range
[Link] Check your settings

[Link] 0x0++0x1FFF

[Link] 0xA0000000++0x1FFFFF

Check your settings as follows:

For the specified address ranges Program breakpoints are

implemented as Onchip breakpoints. For all other memory areas
Software breakpoints are used.

©1989-2024 Lauterbach Training Basic Debugging | 74

Onchip Breakpoints on Read/Write Accesses

Onchip breakpoints can be used to stop the core at a read or write access to a memory location.

©1989-2024 Lauterbach Training Basic Debugging | 75

Onchip Breakpoints by Processor Architecture

Refer to your Processor Architecture Manual for a detailed list of the available Onchip breakpoints.

For some processor architectures Onchip breakpoints can only mark single addresses (e.g Cortex-A9).
Most processor architectures, however, allow to mark address ranges with Onchip breakpoints. It is very
common that one Onchip breakpoint marks the start address of the address range while the second Onchip
breakpoint marks the end address (e.g. MPC57xx).

The command [Link] ([Link] in older software versions) allows to

control how range breakpoints are set for scalars (int, float, double).

[Link] If a breakpoint is set to a scalar variable (int, float, double) the

ON breakpoint is set to the start address of the variable.
+ Requires only one single address breakpoint.
- Program will not stop on unintentional accesses to the variable’s
address space.

[Link] If a breakpoint is set to a scalar variable (int, float, double) breakpoints

OFF are set to all memory addresses that store the variable value.

+ The program execution stops also on any unintentional accesses

to the variable’s address space.
- Requires two onchip breakpoints since a range breakpoint is
used.

The current setting can be inspected and changed from the [Link] window.

Example: the red line in the [Link] window shows the range of the Onchip breakpoint.

; Set an Onchip breakpoint to the start address of the variable vint

[Link] ON
[Link] vint /Write
[Link] vint

; Set an Onchip breakpoint to the whole memory range address of the

; variable vint
[Link] OFF
[Link] vint /Write
[Link] vin

©1989-2024 Lauterbach Training Basic Debugging | 76

A number of processor architectures provide only bit masks or fixed range sizes to mark an address range
with Onchip breakpoints. In this case the address range is always enlarged to the smallest bit mask/next
allowed range that includes the address range.

It is recommended to control which addresses are actually marked with breakpoints by using the
[Link] /Onchip command:

Breakpoint setting:

[Link] str2

[Link]

[Link] /Onchip

ETM Breakpoints for ARM or Cortex-A/-R

ETM breakpoints extend the number of available breakpoints. Some Onchip breakpoints offered by ARM
and Cortex-A/-R cores provide restricted functionality. ETM breakpoints can help you to overcome some of
these restrictions.

ETM breakpoints always show a break-after-make behavior with a rather large delay. Thus, use ETM
breakpoints only if necessary.

©1989-2024 Lauterbach Training Basic Debugging | 77

Program Breakpoints Read/Write Data Value
Breakpoints Breakpoints

ARM7 Onchip breakpoints: Onchip breakpoints: Onchip Breakpoint:

ARM9 up to 2, but address up to 2, but address up to 2, but address range
range only as bit mask range only as bit mask only as bit mask
(Reduced to 1 if soft-
ware breakpoints are ETM breakpoints: ETM breakpoints:
used) up to 2 exact address up to 2 data value breakpoints
ranges for exact address ranges
ETM breakpoints:
up to 2 exact address
ranges

ARM11 Onchip breakpoints: Onchip breakpoints: Onchip breakpoints:

6, but only single 2, but only single no data value breakpoints
addresses addresses possible

ETM breakpoints: ETM breakpoints: ETM breakpoints:

up to 2 exact address up to 2 exact address up to 2 data value breakpoints
ranges possible ranges possible for exact address ranges

Cortex-A5 Onchip breakpoints: Onchip breakpoints: Onchip breakpoints:

3, but only single 2, but address range no data value breakpoints
addresses only as bit mask possible

ETM breakpoints: ETM breakpoints: ETM breakpoints:

up to 2 exact address up to 2 exact address up to 2 data value breakpoints
ranges ranges for exact address ranges

Cortex-A7 Onchip breakpoints: Onchip breakpoints: Onchip breakpoints:

Cortex-R7 6, but only single 4, but address range no data value breakpoints
addresses only as bit mask possible

ETM breakpoints: ETM breakpoints: ETM breakpoints:

up to 2 exact address up to 2 exact address up to 2 data value breakpoints
ranges ranges for exact address ranges

Cortex-A8 Onchip breakpoints: Onchip breakpoints: Onchip breakpoints:

6, but address range 2, but address range no data value breakpoints
only as bit mask only as bit mask possible

ETM breakpoints: ETM breakpoints: ETM breakpoints:

up to 2 exact address up to 2 exact address up to 2 data value breakpoints
ranges ranges for exact address ranges

©1989-2024 Lauterbach Training Basic Debugging | 78

Program Breakpoints Read/Write Data Value
Breakpoints Breakpoints

Cortex-R4 Onchip breakpoints: Onchip breakpoints: Onchip breakpoints:

Cortex-R5 2..8, but address 1..8, but address no data value breakpoints
range only as bit mask range only as bit mask possible

ETM breakpoints: ETM breakpoints: ETM breakpoints:

up to 2 exact address up to 2 exact address up to 2 data value breakpoints
ranges ranges for exact address ranges

Cortex-A9 Onchip breakpoints: Onchip breakpoints: Onchip breakpoints:

Cortex-A15 6, but only single 4, but address range no data value breakpoints
Cortex-A17 addresses only as bit mask possible

ETM breakpoints: ETM breakpoints: ETM breakpoints:

2 exact address ranges — —

Program Breakpoints Read/Write Data Value

Breakpoints Breakpoints

Cortex-A3x Onchip breakpoints: Onchip breakpoints: Onchip breakpoints:

Cortex-A5x 6, but only single 4, but address range no data value breakpoints
Cortex-A6x addresses only as bit mask possible
Cortex-A7x
Cortex-R82 ETM breakpoints: ETM breakpoints: ETM breakpoints:
Cortex-X 2 exact address ranges — —
Neoverse (more on request)

Cortex-R52 Onchip breakpoints: Onchip breakpoints: Onchip breakpoints:

8, but only single 8, but address range no data value breakpoints
addresses only as bit mask possible

ETM breakpoints: ETM breakpoints: ETM breakpoints:

up to 2 exact address — —
ranges

No ETM breakpoints are available for the Cortex-M family.

Please refer to the description of the [Link] command, if you want to use the ETM
breakpoints.

©1989-2024 Lauterbach Training Basic Debugging | 79

Breakpoint Types

TRACE32 PowerView provides the following breakpoint types for standard debugging.

Breakpoint Types Possible Implementations

Program Software (Default)

Onchip

Read, Write, Onchip (Default)

ReadWrite

©1989-2024 Lauterbach Training Basic Debugging | 80

Program Breakpoints

Set a Program breakpoint

by a left mouse
double-click
to the instruction

The red program breakpoint indicator marks all code lines for which a Program breakpoint is set.

The program stops before the instruction marked by the breakpoint is executed (break before make).

Disable the Program

breakpoint by a
left mouse double-click
to the red program
breakpoint indicator.
The program breakpoint
indicator becomes grey.

[Link] <address> /Program [/DISable] Set a Program breakpoint to the specified address.
The Program breakpoint can be disabled if required.

©1989-2024 Lauterbach Training Basic Debugging | 81

[Link] 0xA34f /Program ; set a Program breakpoint to
; address 0xA34f

[Link] func1 /Program ; set a Program breakpoint to the

; entry of func1
; (first address of function func1)

[Link] func1+0x1c /Program ; set a Program breakpoint to the

; instruction at address
; func1 plus 28 bytes
; (assuming that byte is the
; smallest addressable unit)

[Link] func11\7 ; set a Program breakpoint to the

; 7th line of code of the function
; func11
; (line in compiled program)

[Link] func17 /Program /DISable ; set a Program breakpoint to the

; entry of func17
; diable Program breakpoint

[Link] ; list all breakpoints

©1989-2024 Lauterbach Training Basic Debugging | 82

Read/Write Breakpoints

Core stops at
a read access
to the variable

Core stops at
a write access
to the variable

On most core(s) the program stops after the read or write access (break after make).

©1989-2024 Lauterbach Training Basic Debugging | 83

If an HLL variable is displayed,
a small red breakpoint indicator
marks an active Read/Write breakpoint.

A small grey breakpoint indicator

marks a disabled Read/Write breakpoint.

[Link] <address> | <range> /Read | /Write | /ReadWrite [/DISable]

; allow HLL expression to specify breakpoint
[Link] <hll_expression> /Read | /Write | /ReadWrite [/DISable]

[Link] 0x0B56 /Read

[Link] ast /Write

[Link] vpchar+5 /ReadWrite /DISable

[Link] flags /Write

[Link] flags[3] /Read

[Link] ast->count /ReadWrite /DISable

[Link]

©1989-2024 Lauterbach Training Basic Debugging | 84

Breakpoint Handling

Breakpoint Setting at Run-time

Software breakpoints

• If MemAccess Enable/NEXUS/DAP is enabled, Software breakpoints can be set while the

core(s) is executing the program. Please be aware that this is not possible if an instruction cache
and an MMU is used.

• If CpuAccess is enabled, Software breakpoints can be set while the core(s) is executing the
program. If the breakpoint is set via CpuAccess the real-time behavior is influenced.

• If MemAccess and CpuAccess is Denied Software breakpoints can only be set when the
program execution is stopped.

The behavior of Onchip breakpoints is core dependent. E.g. on all ARM/Cortex cores Onchip breakpoints
can be set while the program execution is running.

©1989-2024 Lauterbach Training Basic Debugging | 85

Real-time Breakpoints vs. Intrusive Breakpoints

TRACE32 PowerView offers in addition to the basic breakpoints (Program/Read/Write) also complex
breakpoints. Whenever possible these breakpoints are implemented as real-time breakpoints.

Real-time breakpoints do not disturb the real-time program execution on the core(s), but they require a
complex on-chip break logic.

If the on-chip break logic of a core does not provide the required features or if Software breakpoints are
used, TRACE32 has to implement an intrusive breakpoint.

Intrusive breakpoint perform as follows:

Program execution

Stop program execution Continue with

at breakpoint hit program execution

Check not ok
Perform
required check

Check ok

Stay stopped

Each stop to perform the check suspends the program execution for at least 1 ms. For details refer to
“StopAndGo Mode” in TRACE32 Concepts, page 57 (trace32_concepts.pdf)

The (short-time) display of a red S in the state line indicates that an intrusive breakpoint was hit.

©1989-2024 Lauterbach Training Basic Debugging | 86

Intrusive breakpoints are marked with a special breakpoint indicator:

©1989-2024 Lauterbach Training Basic Debugging | 87

[Link] Dialog Box

There are two standard ways to open a [Link] dialog.

©1989-2024 Lauterbach Training Basic Debugging | 88

The HLL Check Box - Function Name

[Link] func11 ; display symbol information

; for function func11

Function Name/HLL Check Box OFF

Program breakpoint is set to the function entry (first address of the function).

©1989-2024 Lauterbach Training Basic Debugging | 89

[Link] func11

©1989-2024 Lauterbach Training Basic Debugging | 90

Function name/HLL Check Box ON (only for special use cases)

• If the on-chip break logic supports ranges for Program breakpoints, a Program breakpoint
implemented as Onchip is set to the full address range covered by the function.

• If the on-chip break logic provides only bitmasks to realizes breakpoints on instruction ranges, a
Program breakpoint implemented as Onchip is set by using the smallest bitmask that covers the
complete address range of the function.

• otherwise this breakpoint is rejected with an error message.

[Link] func11

©1989-2024 Lauterbach Training Basic Debugging | 91

The HLL Check Box - Program Line Number

[Link] func10\7 ; display debug information

; for 7th program line in
; function func10

Program Line Number/HLL Check Box OFF

Program breakpoint is set to the first assembler instruction generated for the program line number.

[Link] func10\7

Program Line Number/HLL Check Box ON

• If the on-chip break logic supports ranges for Program breakpoints, a Program breakpoint
implemented as Onchip is set to the full address range covered by all assembler instructions
generated for the program line number.

• If the on-chip break logic provides only bitmasks to realizes breakpoints on instruction ranges, a
Program breakpoint implemented as Onchip is set by using the smallest bitmask that covers the

©1989-2024 Lauterbach Training Basic Debugging | 92

complete address range of the program line.

• otherwise this breakpoint is rejected with an error message.

©1989-2024 Lauterbach Training Basic Debugging | 93

The HLL Check Box - Variable

[Link] flags ; display symbol information

; for variable flags

Variable/HLL Check Box OFF

Selected breakpoint (ReadWrite/Read/Write) is set to the start address of the variable.

[Link] flags

©1989-2024 Lauterbach Training Basic Debugging | 94

Variable/HLL Check Box ON

• If the on-chip break logic supports ranges for Read/Write breakpoints, the specified breakpoint is
set to the complete address range covered by the variable.

• If the on-chip break logic provides only bitmasks to realizes Read/Write breakpoints on address
ranges, the specified breakpoint is set by using the smallest bitmask that covers the address
range used by the variable.

[Link] flags

©1989-2024 Lauterbach Training Basic Debugging | 95

The HLL Check Box - HLL Expression

[Link] flags ; display symbol information

; for variable flags

Variable/HLL Check Box Must Be ON

If you want to use an HLL expression to specify the address range for a Read/Write breakpoint, the HLL
check box has to be checked.

• If the on-chip break logic supports ranges for Read/Write breakpoints, the specified breakpoint is
set to the complete address range covered by the HLL expression.

©1989-2024 Lauterbach Training Basic Debugging | 96

[Link] flags[3]

©1989-2024 Lauterbach Training Basic Debugging | 97

Allow Wildcards in address/expression

Set Program breakpoints the all function that match the defined name pattern.

Check * to enable wildcard usage

Requires sufficient resources if Onchip breakpoints are used.

[Link] func2*

©1989-2024 Lauterbach Training Basic Debugging | 98

Implementations

Implementation

auto Use breakpoint implementation as predefined in TRACE32 PowerView.

SOFT Implement breakpoint as Software breakpoint.

Onchip Implement breakpoint as Onchip breakpoint.

©1989-2024 Lauterbach Training Basic Debugging | 99

Actions

By default the program execution is stopped when a breakpoint is hit (action stop). TRACE32 PowerView
provides the following additional reactions on a breakpoint hit:

Action (debugger)

Spot The program execution is stopped shortly at a breakpoint hit to update the
screen. As soon as the screen is updated, the program execution continues.

Alpha Set an Alpha breakpoint.

Beta Set a Beta breakpoint.

Charly Set a Charly breakpoint.

Delta Set a Delta breakpoint.

Echo Set an Echo breakpoint.

WATCH Trigger the debug pin at the specified event (not available for all processor
architectures).

Alpha, Beta, Charly, Delta and Echo breakpoint are only used in very special cases. For this reason no
description is given in the general part of the training material.

©1989-2024 Lauterbach Training Basic Debugging | 100

Action (on-chip or off-chip trace)

TraceEnable Advise on-chip trace logic to generate trace information on the specified event.

TraceON Advise on-chip trace logic to start with the generation of trace information at the
specified event.

TraceOFF Advise on-chip trace logic to stop with the generation of trace information at the
specified event.

TraceTrigger Advise on-chip trace logic to generate a trigger at the specified event.
TRACE32 PowerView stops the recording of trace information when a trigger is
detected.

A detailed description for the Actions (on-chip and off-chip trace) can be found in the following manuals:

• “Training Arm CoreSight ETM Tracing” (training_arm_etm.pdf).

• “Training Cortex-M Tracing” (training_cortexm_etm.pdf).

• “Training AURIX Tracing” (training_aurix_trace.pdf).

• “Training Hexagon ETM Tracing” (training_hexagon_etm.pdf).

• “Training MPC5xxx/SPC5xx Nexus Tracing” (training_nexus_mpc5500.pdf).

or with the description of the [Link] command.

©1989-2024 Lauterbach Training Basic Debugging | 101

Example for the Action Spot

The information displayed within TRACE32 PowerView is by default only updated, when the core(s) stops
the program execution.

The action Spot can be used to turn a breakpoint into a watchpoint. The core stops the program execution at
the watchpoint, updates the screen and restarts the program execution automatically. Each stop takes
50 … 100 ms depending on the speed of the debug interface and the amount of information displayed on
the screen.

Example: Update the screen whenever the program executes the instruction sieve\11.

©1989-2024 Lauterbach Training Basic Debugging | 102

spotted indicates a breakpoint with the action Spot

[Link] sieve\11 /Spot

©1989-2024 Lauterbach Training Basic Debugging | 103

Options

Temporary OFF: Set a permanent breakpoint (default).

ON: Set a temporary breakpoint. All temporary breakpoints are deleted
the next time the core(s) stops the program execution.

DISable OFF: Breakpoint is enabled (default).

ON: Set breakpoint, but disabled.

DISableHIT ON: Disable the breakpoint after the breakpoint was hit.

Example for the Option Temporary

Temporary breakpoints are usually not set via the [Link] dialog, but they are often used while
debugging.

Examples:

• Go Till

Go <address> [ <address> …]

; set a temporary Program breakpoint to

; the entry of the function func4
; and start the program execution
Go func4

; set a temporary Program breakpoints to

; the entries of the functions func4, func8 and func9
; and start the program execution
Go func4 func8 func9

• Go Till -> Write

[Link] <hll_expression> [/Write]

; set a temporary write breakpoint to the variable

; vtripplearray[0][1][0] and start the program execution
[Link] vtripplearray[0][1][0] /Write

• [Link] and similar commands

[Link]

; first [Link]
; set a temporary breakpoint to the start of the function epilogue
; and start the program execution
[Link]
; stopping at the function epilog first has the advantage that the
; local variables are still valid at this point.

; second [Link]
; set a temporary breakpoint to the function return
; and start the program execution
[Link]

DATA Breakpoints

The DATA field offers the possibility to combine a Read/Write breakpoint with a specific data value.

• DATA breakpoints are implemented as real-time breakpoints if the core supports Data Value
Breakpoints (for details on your core refer to “Onchip Breakpoints by Processor Architecture”,
page 76).

TRACE32 PowerView indicates a real-time breakpoints by a full red bar.

TRACE32 PowerView allows inverted data values if this is supported by the on-chip break logic.

• DATA breakpoints are implemented as intrusive breakpoints if the core does not support Data
Value Breakpoints. For details on the intrusive DATA breakpoints refer to the description of the
[Link] command.

TRACE32 PowerView indicates an intrusive breakpoint by a hatched red bar.

TRACE32 PowerView allows inverted data values for intrusive DATA breakpoints.

Example: Stop the program execution if a 1 is written to flags[3].

[Link] flags[3] /Write /[Link] 1.

Example: Stop the program execution if another value then 1 is written to flag[3].

[Link] flags[3] /Write /[Link] !1.

If an HLL expression is used TRACE32 PowerView gets the information if the data is written via a byte, word
or long access from the symbol information.

If an address or symbol is used the user has to specify the access width, so that the correct number of bits is
compared.

[Link] 0x11dcf /Write /[Link] 1234.

Advanced Breakpoints

If the advanced button is pushed

additional input fields are provided

Advanced breakpoint input fields

TASK-aware Breakpoints

If OS-aware debugging is configured (refer to “OS-aware Debugging” in TRACE32 Concepts, page 34

(trace32_concepts.pdf)), TASK-aware breakpoints allow to stop the program execution at a breakpoint if the
specified task/process is running.

TASK-aware breakpoints are implemented on most cores as intrusive breakpoints. A few cores support real-
time TASK-aware breakpoints (e.g. ARM/Cortex). For details on the real-time TASK-aware breakpoints refer
to the description of the [Link] command.

Intrusive TASK-aware Breakpoint

Processing:

Program execution stops at TASK-aware

breakpoint

Specified No
task Continue with
running? program execution

Yes

Keep stop of program execution

Each stop at the TASK-aware breakpoint takes at least [Link]. This is why the red S is displayed in the
TRACE32 PowerView state line whenever the breakpoint is hit.

Example: Stop the program execution at the entry to the function EE_oo_TerminateTask only if the
task/process “Task3” is running.

[Link] EE_oo_TerminateTask /Program /TASK "Task3"

The red S indicates that an
intrusive breakpoint is used

Real-time TASK-aware Breakpoint

Example for ARM9: Stop the program execution at the entry to the function Func_2 only if the taskF “main” is
running (Onchip breakpoint).

COUNTer

Counters allow to stop the program execution on the n th hit of a breakpoint.

Software Counter

If the on-chip break logic of the core does not provide counters or if a Software breakpoint is used, counters
are implemented as software counters.

Processing:

Program execution stops at

a breakpoint with counter

Increment
counter

Counter No
reached final Continue with
program execution
value?

Yes

Keep stop of program execution

Each stop at a Counter breakpoint takes at least [Link]. This is why the red S is displayed in the TRACE32
PowerView state line whenever the breakpoint is hit.

Example: Stop the program execution after the function sieve was entered 1000. times.

[Link] sieve /COUNT 1000.

The current counter
value is displayed
in the [Link]
window

The red S indicates an

intrusive breakpoint

On-chip Counter

The on-chip break logic of some cores e.g. MPC55xx provides counters. They are used together with
Onchip breakpoints.

Example: Stop the program execution after the function sieve was entered 1000. times.

[Link] sieve /COUNT 1000. /Onchip

The counters run completely in real-time. No current counter value can be displayed while the program
execution is running. As soon as the counter reached its final value, the program execution is stopped.

CONDition

The program execution is stopped at the breakpoint only if the specified condition is true.

CONDition breakpoints are always intrusive.

Processing:

Program execution stops

at a breakpoint with condition

AfterStep No
check box
ON?

Yes

Perform assembler
single step

Verify
condition

Condition No
is Continue with
true? program execution

Yes

Keep stop of program execution

Each stop at a CONDition breakpoint takes at least [Link]. This is why the red S is displayed in the TRACE32
PowerView state line whenever the breakpoint is hit.

Example: Stop the program execution on a write to flags[3] only if flags[12] is equal to 0 when the
breakpoint is hit.

The red S indicates
an intrusive breakpoint

[Link] flags[3] /Write /VarCONDition flags[12]==0

Example: “Break-before-make” Read/Write breakpoints only

Stop the program execution at a write access to the variable mstatic1 only if flags[12] is equal to 0 and
mstatic1 is greater 0.

Perform an assembler single step because the processor architecture stops before the write access is
performed.

AfterStep checked

[Link] mstatic1 /Write /VarCONDition (flags[12]==0)&&(mstatic1>0)

/AfterStep

The red S indicates
an intrusive breakpoint

Conditions not in HLL Syntax

It is also possible to write register-based or memory-based conditions.

Examples: Stop the program executions on a write to the address flags if Register R11 is equal to 1.

Switch HLL OFF ->

TRACE32 syntax can be used
to specify the condition

; stop the program execution at a write to the address flags if the

; register R11 is equal to 1
[Link] flags /Write /CONDition Register(R11)==0x1

; stop program execution at a write to the address flags if the long

; at address D:0x1000 is larger then 0x12345
[Link] flags /Write /CONDition [Link](D:0x1000)>0x12345

Example: Stop the program execution if an register-indirect call calls the function func3.

[Link] main\31+0x8 /CONDition Register(PC)==[Link](func3)

/AfterStep

The field CMD allows to specify one or more commands that are executed when the breakpoint is hit.

Example: Write the contents of flags[12] to a file whenever the write breakpoint at the variable flags[12] is
hit.

OPEN #1 [Link] /Create ; open the file for writing

The specified command(s) is executed

whenever the breakpoint is hit. With RESUME
ON the program execution will continue after
the execution of the command(s) is finished.

The cmd field in the [Link] window

informs the user which command(s) is
associated with the breakpoint. R indicates
that RESUME is ON.

[Link] flags[12] /Write /CMD "WRITE #1 ""flags[12]="" %Decimal

[Link](flags[12])" /RESUME

It is recommended to set RESUME to OFF, if CMD

• starts a PRACTICE script with the command DO

• commands are used that open processing windows like

[Link], [Link] or [Link]

because the program execution is restarted before these commands are

completed.

The state of the debugger toggles between

running and stopped

CLOSE #1 ; close the file when you are done

Display the result:

memory/register/var

The on-chip break logic of some cores allows to combine data accesses and instructions to form a complex
breakpoint (e.g. ARM or PowerArchitecture).

Preconditions

• Harvard architecture.

• The on-chip break logic supports a logical AND between Program and Read/Write breakpoints.

Advantageous

• Program breakpoints on address ranges are possible.

• Read/Write breakpoints on address ranges are possible.

Example: Stop the program execution when the function sieve writes a 1 to variable flags[3]. (If your core
does not support this feature, the radio buttons (MemoryWrite, MemoryRead etc.) are grey.)

1. Define the address (range) of the

instructions here

2. Select MemoryWrite

3. Define the address (range) for the

MemoryWrite accesses

4. Define the data value for the

MemoryWrite accesses

[Link] sieve /VarWrite flags[3] /[Link] 1.

Exclude (Advanced users only, not available on all cores)

The breakpoint is inverted.

• by the inverting logic of the on-chip break logic

• by setting the specified breakpoint type to the following

2 address ranges
0x0--(start_of_breakpoint_range-1)
(end_of_breakpoint_range+1)--end_of_memory

The EXclude option applies only to Onchip breakpoints.

If the on-chip breakpoint logic does not provide an inverting logic, the
core has to provide the facility to set the specified breakpoint type on
2 address ranges.

Example for the Option EXclude

Stop the program execution when code outside of the function sieve writes 1 to the variable flags[3].

[Link] sieve /VarWrite flags[3] /[Link] 1. /EXclude

The function sieve is marked with Exclude memoryWrite breakpoints

The following command allows to check how the option EXclude is implemented.

[Link] /Onchip

Inverting logic of on-chip break logic:

Two address range breakpoints:

If your TRACE32 PowerView does not accept the option EXclude, delete all other Onchip breakpoints, to
make sure that enough resources are available.

Display a List of all Set Breakpoints

address Address of the breakpoint

types Type of the breakpoint

impl Implementation of the breakpoint or disabled

action Action selected for the breakpoint (if not stop)

options Option defined for the breakpoint

data Data value that has to be read/written to stop the program execution by
the breakpoint

count Current value/final value of the counter that is combined with a

breakpoint

condition Condition that has to be true to stop the program execution by the
breakpoint
A (AfterStep) A ON: Perform an assembler single step before condition is evaluated

cmd (command) Commands that are executed after the breakpoint hit
R (resume) R ON: continue the program execution after the specified commands
were executed

task Name of the task for a task-aware breakpoint

Symbolic address of the breakpoint

[Link] [/<option>] List all breakpoints

Delete Breakpoints

[Link] <address>|<address_range> [/<type>] [/<implem.>] [/<option>] Delete breakpoint

[Link] <hll_expression> [/<type>] [/<implem.>] [/<option>] Delete HLL breakpoint

Enable/Disable Breakpoints

[Link] [<address>|<address_range>] [/<option>] Enable breakpoint

[Link] [<address>|<address_range>] [/<option>] Disable breakpoint

Store Breakpoint Settings

// AndT32 Fri Jul 04 13:17:41 2003

B::

[Link]
[Link] func4 /Program /DISableHIT
[Link] sieve /Program
[Link] \\diabp555\Global\flags[3]; /Write /[Link] 0x1;

ENDDO

STOre <filename> Break Generate a script for breakpoint settings

Debugging

Debugging of Optimized Code

A video tutorial about debugging optimized code can be found here:

[Link]/kb/articles/debugging-optimized-code-in-trace32

HLL mode and MIX mode debugging is simple, if the compiler generates a continuous block of assembler
code for each HLL code line.

If compiler optimization flags are turned on, it is highly likely that two or more detached blocks of assembler
code are generated for individual HLL code lines. This makes debugging laboriously.

TRACE32 PowerView displays a tree button, whenever two or more detached blocks of assembler code are
generated for an HLL code line.

tree button

The following background information is fundamental if you want to debug optimized code:

• In HLL debug mode, the HLL code lines are displayed as written in the compiled program (source
line order).

• In MIX debug mode, the target code is disassembled and the HLL code lines are displayed
together with their assembler code blocks (target line order). This means if two or more detached
blocks of assembler code are generated for an HLL code line, this HLL code line is displayed
more than once in a MIX mode source listing.

The expansion of the tree button shows how many detached blocks of assembler code are generated for the
HLL line (e.g. two in the example below).

[Link] Display source listing, display HLL code lines only.

[Link] /Track Display source listing, display disassembled code and the assigned
HLL code lines.

The blue cursor in the MIX mode display follows the cursor movement
of the HLL mode display (Track option).

To keep track when debugging optimized code, it is recommended to work with an HLL mode and a MIX
mode display of the source listing in parallel.

[Link]

[Link] /Track

Please be aware of the following:

If a Program breakpoint is set to an HLL code line for which two or more detached blocks of assembler code
are generated, a Program breakpoint is set to the start address of each assembler block.

Basic Debug Control

There are local buttons in the List window for all basic debug commands

Step Single stepping (command: Step)

Over Step over call (command [Link]).

Diverge Exit loops or fast forward to not yet stepped code lines. [Link] is performed
repeatedly.

More details on [Link]

TRACE32 maintains a list of all assembler/HLL lines which were already reached by a Step. These reached
lines are marked with a slim grey line in the List window.

The following command allows you to get more details:

[Link] /DIVERGE

Drag this handle to see the DIVERGE details

Column layout

s Step type performed on this line

a: Step on assembler level was started from this code line
h: Step on HLL level was started from this code line

state done: code line was reached by a Step and a Step was started from
this code line.
hit: code line was reached by a Step.
target: code line is a possible destination of an already started Step,
but was not reached yet (mostly caused by conditional branches).

stop: program execution stopped at code line.

i indirect branch taken

(return instructions are not marked).

Example 1: Diverge through function sieve.

1. Run program execution until entry to function sieve.

stop indicates that the

program execution was
stopped at this code line

2. Start a [Link] command.

h indicates that a Step

command in HLL mode was
started in this line

hit indicates that this

code line was reached by
Step command

3. Continue with [Link].

done indicates that the

code line was reached by
a Step command and that
a Step command was
started from this code line

The tree button
indicates that two or
more detached blocks of
assembler code are
generated for an HLL
code line

4. Continue with [Link].

The drill-down tree is

expanded and the HLL
code line representing
the reached block of
assembler code is marked as hit

This HLL code line includes a
conditional branch

5. Continue with [Link].

The reached code line is

marked as hit

The not-reached code line is

marked as target

6. Continue with [Link] (several times).

All code lines are now

either marked as done,
hit or target

7. Continue with [Link].

A code line former marked

as target changes to hit
when it is reached

When all reachable code lines are marked as done, the following message is displayed:

The DIVERGE marking is cleared when you use the [Link] command without address or the Break
command while the program execution is stopped.

Example 2: Exit a loop.

DIVERGE marking is
done whenever you
single step.

If all code lines of

a loop are marked as
done/hit, a
[Link] will
exit the loop

Return Return sets a temporary breakpoint to the last instruction of a function and then
starts the program execution.

Up This command is used to return to the function that called the current function.
For this a temporary breakpoint is set to the instruction directly after the function
call. Afterwards the program execution is started.

Display the HLL stack to

check the function nesting

Step [<count>] Single step
[Link] <expression> Step until <expression> changes
[Link] <condition> Step until <condition> becomes true,
<condition> written in TRACE32 syntax
[Link] <hll_expression> Step until <hll_expression> changes
[Link] <hll_condition> Step until <hll_condition> becomes true,
<hll_condition> as allowed in used programming
language

Step 10.

[Link] Register(R11)

[Link] Register(R11)>0xAA

[Link] flags[3]

[Link] flags[3]==1

[Link] Step over call

Go [<address>|<label>] Start program execution

[Link] Set a temporary breakpoint to the next code line
and start the program execution
[Link] Set a temporary breakpoint to the return
instruction and start the program execution
[Link] [<level>|<address>] Run program until it returns to the caller function

Sample-based Profiling

Program Counter Sampling

Task: get the percentage of time used by a high-level language function.

Measurement procedure: The Program Counter is sampled periodically. This is implemented in two ways.

• Snoop: Processor architecture allows to read the Program Counter while the program execution
is running.

• StopAndGo: The program execution is stopped shortly in order to read the Program Counter.

Standard Procedure

Steps to be taken:

1. Open the PERF configuration window.

[Link] Display PERF configuration window

The PERF METHOD Snoop is automatically selected, if the processor architecture supports reading
the Program Counter while the program execution is running.

The default METHOD for all other processor architectures is StopAndGo.

Remarks on the StopAndGo method

StopAnd Go means that the core is stopped periodically in order to get the actual Program Counter.

STREAM ON The software running on the TRACE32 debug hardware

initiates the periodic stops. This has the following advantages:

• Low intrusive (approx. 50. to [Link])

• More samples per second are possible

STREAM OFF The software running on the host initiates the periodic stops.

• More intrusive (1 ms in a worst case scenario)

• Less samples per second are possible

The display of a red S in the TRACE32 state line indicates that the program execution is periodically
interrupted by the sample-based profiling.

TRACE32 tunes the sampling rate so that more the 99% of the run-time is retained for the actual
program run (runtime). The smallest possible sampling rate is nevertheless 10 (snoops/s).

2. Enable the sample-based profiling by selecting the OFF state.

[Link] Enable the sample-based profiling

3. Open a result window by pushing the ListFunc button.

[Link] Open an HLL function profiling window

4. Start the program execution and the sampling.

Details

In-depth Result

Push the Detailed button, to get more detailed information on the result.

[Link] ALL Open a detailed HLL function profiling window

name Function name

time Time in function

watchtime Time the function is observed

ratio Ratio of time spent by the function in percent

dratio Similar to Ratio, but only for the last second

address Function´s address range

hits Number of samples taken for the function

(other)

TRACE32 assigns all samples that can not be assigned to a high-level language function to (other).
Especially if the ratio for (other) is quite high, it might be interesting what code is running there. In this case
pushing the button ListLABEL is recommended.

[Link] Open a window for label-based profiling

TASK Sampling

If OS-aware debugging is configured (refer to “OS-aware Debugging” in TRACE32 Concepts, page 34

(trace32_concepts.pdf)), TASK information can be sampled.

Steps to be taken:

1. Open the PERF configuration window.

2. Select Mode TASK.

Since every OS has a variable that contains the information which task/process is currently running,
this variable has to be sampled while the program execution is running in order to perform TASK
sampling.

TRACE32 fills the following fields when TASK mode is selected:

- the SnoopAddress field with the address of the variable.

- the SnoopSize field with the size of the variable.

The PERF METHOD Snoop is automatically selected, if the processor architecture supports reading
physical memory while the program execution is running. For details refer to “Run-time Memory
Access” in TRACE32 Concepts, page 45 (trace32_concepts.pdf)).

The default METHOD for all other processor architectures is StopAndGo.

[Link] TASK

3. Enable sample-based profiling by switching to OFF state and open the result window by
pushing the ListTask button.

[Link] Enable the sample-based profiling

[Link]

4. Start the program execution and the sampling.

Manual: Training - Debugger Basics
No ratings yet
Manual: Training - Debugger Basics
164 pages
Training Debugger
No ratings yet
Training Debugger
173 pages
Training Debugger
No ratings yet
Training Debugger
169 pages
Training Debugger
No ratings yet
Training Debugger
213 pages
Debugger Tricore
No ratings yet
Debugger Tricore
135 pages
Manual: Tricore Debugger and Trace
No ratings yet
Manual: Tricore Debugger and Trace
139 pages
Debugger Tricore
100% (1)
Debugger Tricore
145 pages
TRACE32 Debugger Setup Tutorial
No ratings yet
TRACE32 Debugger Setup Tutorial
33 pages
Debugger Arc
No ratings yet
Debugger Arc
46 pages
RH850 Debugger User Manual 09.2023
No ratings yet
RH850 Debugger User Manual 09.2023
101 pages
Lauterbach Trace32 Debugging Overview
No ratings yet
Lauterbach Trace32 Debugging Overview
35 pages
Debugger Andes
No ratings yet
Debugger Andes
46 pages
Debugger Hexagon
No ratings yet
Debugger Hexagon
79 pages
Debugger Arm
No ratings yet
Debugger Arm
223 pages
Debugger Mcore
No ratings yet
Debugger Mcore
39 pages
Debugger Xtensa
No ratings yet
Debugger Xtensa
68 pages
Debugger 166cbc
No ratings yet
Debugger 166cbc
58 pages
Debugger Riscv
No ratings yet
Debugger Riscv
131 pages
Debugger Cortexm
No ratings yet
Debugger Cortexm
145 pages
MPC5xx/8xx Debugger Manual 09.2024
No ratings yet
MPC5xx/8xx Debugger Manual 09.2024
56 pages
Debugger Armv8a
No ratings yet
Debugger Armv8a
168 pages
Debugger M8051ew
No ratings yet
Debugger M8051ew
41 pages
Debugger Hc12
No ratings yet
Debugger Hc12
52 pages
Debugger Microblaze
No ratings yet
Debugger Microblaze
49 pages
Debugger m32r
No ratings yet
Debugger m32r
34 pages
Debugger Hc08
100% (1)
Debugger Hc08
31 pages
Debugger Cevax
No ratings yet
Debugger Cevax
57 pages
Debugger Ppc600
No ratings yet
Debugger Ppc600
81 pages
Debugger 68k
No ratings yet
Debugger 68k
64 pages
TRACE32 ICD Debugger Setup Guide
No ratings yet
TRACE32 ICD Debugger Setup Guide
42 pages
Debugger c6000
No ratings yet
Debugger c6000
60 pages
Debugger User
No ratings yet
Debugger User
109 pages
Debugger Mips
No ratings yet
Debugger Mips
79 pages
Debugger v850
No ratings yet
Debugger v850
58 pages
Debugger Ppcqoriq
No ratings yet
Debugger Ppcqoriq
90 pages
Understanding Debugging Techniques
No ratings yet
Understanding Debugging Techniques
22 pages
Training Rtos Linux
No ratings yet
Training Rtos Linux
56 pages
ARM Cortex-M3 Debugging Techniques
No ratings yet
ARM Cortex-M3 Debugging Techniques
6 pages
OllyDbg Crash Course Overview
100% (1)
OllyDbg Crash Course Overview
45 pages
Debugger x86
No ratings yet
Debugger x86
115 pages
Debugger Microblaze
No ratings yet
Debugger Microblaze
49 pages
App T32start
No ratings yet
App T32start
78 pages
Debugger Etpu
No ratings yet
Debugger Etpu
42 pages
14-Training Rtos Linux x86
No ratings yet
14-Training Rtos Linux x86
48 pages
Interactive Debugging Systems Overview
No ratings yet
Interactive Debugging Systems Overview
16 pages
Debugger 78k
No ratings yet
Debugger 78k
40 pages
Debugger c2000
No ratings yet
Debugger c2000
58 pages
Debugger Xc800
No ratings yet
Debugger Xc800
25 pages
TriCore Simulator User Manual
No ratings yet
TriCore Simulator User Manual
21 pages
APU API Developer's Guide
No ratings yet
APU API Developer's Guide
40 pages
Debugger Blackfin
No ratings yet
Debugger Blackfin
26 pages
CoreSight ETM Tracing Manual
No ratings yet
CoreSight ETM Tracing Manual
186 pages
JTAG Remote Control API in C
No ratings yet
JTAG Remote Control API in C
195 pages
Debugger PPC
No ratings yet
Debugger PPC
73 pages
LOGGER Trace Application Note
No ratings yet
LOGGER Trace Application Note
20 pages
Introduction to Assembly Language Basics
100% (3)
Introduction to Assembly Language Basics
22 pages
80386 Debug and Memory Management Registers
No ratings yet
80386 Debug and Memory Management Registers
35 pages
UDE Manual
100% (1)
UDE Manual
177 pages
80386DX Initialization & Debugging Guide
No ratings yet
80386DX Initialization & Debugging Guide
43 pages
CX-900-Operator Guide
No ratings yet
CX-900-Operator Guide
92 pages
Photoshop Scroll Animation Guide
No ratings yet
Photoshop Scroll Animation Guide
9 pages
C# Function Overloading for Swapping
No ratings yet
C# Function Overloading for Swapping
17 pages
Kohana PHP ORM Guide: Class Creation
100% (8)
Kohana PHP ORM Guide: Class Creation
26 pages
E-Commerce Security Essentials Guide
No ratings yet
E-Commerce Security Essentials Guide
3 pages
PMBusGUI Manual
No ratings yet
PMBusGUI Manual
81 pages
SMA22 en
No ratings yet
SMA22 en
166 pages
Architectural Design Patterns Overview
No ratings yet
Architectural Design Patterns Overview
15 pages
FaceOff State Machine Template
No ratings yet
FaceOff State Machine Template
16 pages
SQL Lab Exercises for Database Management
No ratings yet
SQL Lab Exercises for Database Management
16 pages
NextEngine 3D Scanner Tutorial Guide
No ratings yet
NextEngine 3D Scanner Tutorial Guide
36 pages
Asc Timetables Full Crack Downloads
No ratings yet
Asc Timetables Full Crack Downloads
2 pages
Digital Literacy - Fundamentals Notes - Lessons 1 and 2
No ratings yet
Digital Literacy - Fundamentals Notes - Lessons 1 and 2
21 pages
Maximo Asset Management Essentials V7.1 Implementer's Guide: Front Cover
100% (2)
Maximo Asset Management Essentials V7.1 Implementer's Guide: Front Cover
160 pages
Excel Functions Quick Reference Guide
No ratings yet
Excel Functions Quick Reference Guide
8 pages
Web Page Analysis for Data Scraping
No ratings yet
Web Page Analysis for Data Scraping
9 pages
Fixing Fatal Trap 12 on FreeNAS RAID5
No ratings yet
Fixing Fatal Trap 12 on FreeNAS RAID5
1 page
WhatsAd365: Earn by Watching Ads
No ratings yet
WhatsAd365: Earn by Watching Ads
28 pages
Cloud Architect's Guide To Office 365 Backup: Cover Image
No ratings yet
Cloud Architect's Guide To Office 365 Backup: Cover Image
6 pages
SAP HANA MCQ Interview Questions
50% (2)
SAP HANA MCQ Interview Questions
3 pages
Adobe Photoshop Tools Overview
No ratings yet
Adobe Photoshop Tools Overview
4 pages
Gamifying Software Testing Education
No ratings yet
Gamifying Software Testing Education
6 pages
Software Engineering Lab Manual 2019-20
No ratings yet
Software Engineering Lab Manual 2019-20
149 pages
2017 MacBook Pro Trackpad Issues
No ratings yet
2017 MacBook Pro Trackpad Issues
1 page
JavaScript Rollover Effects Guide
No ratings yet
JavaScript Rollover Effects Guide
3 pages
Numpy Tutorial PDF
71% (7)
Numpy Tutorial PDF
34 pages
AC12010 UserGuide En-Us
No ratings yet
AC12010 UserGuide En-Us
978 pages
Android UI Components Overview
No ratings yet
Android UI Components Overview
78 pages
Revit 2016 BIM Management-Template and Family Creation PDF
No ratings yet
Revit 2016 BIM Management-Template and Family Creation PDF
54 pages
Convert Word to PDF with WinZip
No ratings yet
Convert Word to PDF with WinZip
2 pages