Module-4
Integrated peripherals of MCS 51
Integrated peripherals such as Timers/Counters:
8051 Timers
Introduction
8051 microcontrollers have two timers/counters which work on the clock
frequency. Timer/counter can be used for time delay generation, counting external events, etc.
Clock
Every Timer needs a clock to work, and 8051 provides it from an external crystal which is the
main clock source for Timer. The internal circuitry in the 8051 microcontrollers provides a clock
source to the timers which are 1/12th of the frequency of crystal attached to the microcontroller,
also called Machine cycle frequency.
For example, suppose we have a crystal frequency of 11.0592 MHz then the microcontroller will
provide 1/12th i.e.
Timer clock frequency= (Xtal [Link])/12 = (11.0592 MHz)/12 = 921.6 KHz
period T= 1/(921.6 kHz)=1.085 μS
Timer
8051 has two timers Timer0 (T0) and Timer1 (T1), both are 16-bit wide. Since 8051 has 8-bit
architecture, each of these is accessed by two separate 8-bit registers as shown in the figure
below. These registers are used to load timer count.
8051 has a Timer Mode Register and Timer Control Register for selecting a mode of operation
and controlling purpose.
Let's see these registers,
TMOD register
TMOD is an 8-bit register used to set timer mode of timer0 and timer1.
Its lower 4 bits are used for Timer0 and the upper 4 bits are used for Timer1
Bit 7, 3 – GATE:
1 = Enable Timer/Counter only when the INT0/INT1 pin is high and TR0/TR1 is set.
0 = Enable Timer/Counter when TR0/TR1 is set.
Bit 6, 2 - C/ (Counter/Timer): Timer or Counter select bit
1 = Use as Counter
0 = Use as Timer
Bit 5:4 & 1:0 - M1:M0: Timer/Counter mode select bit
These are Timer/Counter mode select bit as per the below table.
TCON is an 8-bit control register and contains a timer and interrupt flags.
Bit 7 - TF1: Timer1 Overflow Flag
1 = Timer1 overflow occurred (i.e. Timer1 goes to its max and roll over back to zero).
0 = Timer1 overflow not occurred.
It is cleared through software. In the Timer1 overflow interrupt service routine, this bit will get
cleared automatically while exiting from ISR.
Bit 6 - TR1: Timer1 Run Control Bit
1 = Timer1 start.
0 = Timer1 stop.
It is set and cleared by software.
Bit 5 – TF0: Timer0 Overflow Flag
1 = Timer0 overflow occurred (i.e. Timer0 goes to its max and roll over back to zero).
0 = Timer0 overflow not occurred.
It is cleared through software. In the Timer0 overflow interrupt service routine, this bit will get
cleared automatically while exiting from ISR.
Bit 4 – TR0: Timer0 Run Control Bit
1 = Timer0 start.
0 = Timer0 stop.
It is set and cleared by software.
Bit 3 - IE1: External Interrupt1 Edge Flag
1 = External interrupt1 occurred.
0 = External interrupt1 Processed.
It is set and cleared by hardware.
Bit 2 - IT1: External Interrupt1 Trigger Type Select Bit
1 = Interrupt occurs on falling edge at INT1 pin.
0 = Interrupt occur on a low level at the INT1 pin.
Bit 1 – IE0: External Interrupt0 Edge Flag
1 = External interrupt0 occurred.
0 = External interrupt0 Processed.
It is set and cleared by hardware.
Bit 0 – IT0: External Interrupt0 Trigger Type Select Bit
1 = Interrupt occurs on falling edge at INT0 pin.
0 = Interrupt occur on a low level at INT0 pin.
8051 Interrupts
An interrupt is an event that occurs randomly in the flow of continuity. It is just like a call you
have when you are busy with some work and depending upon call priority you decide whether to
attend or neglect it.
The same thing happens in microcontrollers. 8051 architecture handles 5 interrupt sources, out of
which two are internal (Timer Interrupts), two are external and one is a serial interrupt. Each of
these interrupts has its interrupt vector address. The highest priority interrupt is the Reset, with
vector address 0x0000.
Vector Address: This is the address where the controller jumps after the interrupt to serve the
ISR (interrupt service routine).
Reset
Reset is the highest priority interrupt, upon reset 8051 microcontroller start executing code from
0x0000 address.
Internal interrupt (Timer Interrupt)
8051 has two internal interrupts namely timer0 and timer1. Whenever timer overflows, timer
overflow flags (TF0/TF1) are set. Then the microcontroller jumps to their vector address to serve
the interrupt. For this, global and timer interrupt should be enabled.
Serial interrupt
8051 has a serial communication port and have related serial interrupt flags (TI/RI). When the
last bit (stop bit) of a byte is transmitted, the TI serial interrupt flag is set, and when the last bit
(stop bit) of the receiving data byte is received, the RI flag gets set.
IE register: Interrupt Enable Register
IE register is used to enable/disable interrupt sources.
Bit 7 – EA: Enable All Bit
1 = Enable all interrupts
0 = Disable all interrupts
Bit 6,5 – Reserved bits
Bit 4 – ES: Enable Serial Interrupt Bit
1 = Enable serial interrupt
0 = Disable serial interrupt
Bit 3 – ET1: Enable Timer1 Interrupt Bit
1 = Enable Timer1 interrupt
0 = Disable Timer1 interrupt
Bit 2 – EX1: Enable External1 Interrupt Bit
1 = Enable External1 interrupt
0 = Disable External1 interrupt
Bit 1 – ET0: Enable Timer0 Interrupt Bit
1 = Enable Timer0 interrupt
0 = Disable Timer0 interrupt
Bit 0 – EX0: Enable External0 Interrupt Bit
1 = Enable External0 interrupt
0 = Disable External0 interrupt
Interrupt priority
Priority to the interrupt can be assigned by using the interrupt priority register (IP)
Interrupt priority after Reset:
In the table, interrupts priorities upon reset are shown. As per 8051 interrupt priorities, the lowest
priority interrupts are not served until the microcontroller is finished with higher priority ones. In
a case when two or more interrupts arrive microcontroller queues them according to priority.
IP Register: Interrupt priority register
8051 has an interrupt priority register to assign priority to interrupts.
Bit 7,6,5 – Reserved bits.
Bit 4 – PS: Serial Interrupt Priority Bit
1 = Assign a high priority to serial interrupt.
0 = Assign low priority to serial interrupt.
Bit 3 – PT1: Timer1 Interrupt Priority Bit
1 = Assign high priority to Timer1 interrupt.
0 = Assign low priority to Timer1 interrupt.
Bit 2 – PX1: External Interrupt 1 Priority Bit
1 = Assign high priority to External1 interrupt.
0 = Assign low priority to External1 interrupt.
Bit 1 – PT0: Timer0 Interrupt Priority Bit
1 = Assign high priority to Timer0 interrupt.
0 = Assign low priority to Timer0 interrupt.
Bit 0 – PX0: External0 Interrupt Priority Bit
1 = Assign high priority to External0 interrupt.
0 = Assign low priority to External0 interrupt.
External interrupts in 8051:
8051 has two external interrupt INT0 and INT1.
8051 controller can be interrupted by external Interrupt, by providing level or edge on
external interrupt pins PORT3.2, PORT3.3.
External peripherals can interrupt the microcontroller through these external interrupts if
global and external interrupts are enabled.
Then the microcontroller will execute current instruction and jump to the Interrupt
Service Routine (ISR) to serve to interrupt.
In the polling, method the microcontroller has to continuously check for a pulse by
monitoring pin, whereas, in the interrupt method, the microcontroller does not need to
poll. Whenever an interrupt occurs microcontroller serves the interrupt request.
External interrupt has two types of activation level
1. Edge triggered (Interrupt occur on rising/falling edge detection)
2. Level triggered (Interrupt occur on high/low-level detection)
In 8051, two types of activation levels are used. These are,
Low level triggered
Whenever a low level is detected on the INT0/INT1 pin while global and
external interrupts are enabled, the controller jumps to interrupt service routine
(ISR) to serve interrupt.
Falling edge triggered
Whenever falling edge is detected on the INT0/INT1 pin while global and ext.
interrupts are enabled, the controller jumps to interrupt service routine (ISR) to
serve interrupt.
There are lower four flag bits in the TCON register required to select and monitor
the external interrupt type and ISR status.
TCON: Timer/ counter Register
Bit 3- IE1:
External Interrupt 1 edge flag, set by hardware when interrupt on INT1 pin occurred and
cleared by hardware when interrupt get processed.
Bit 2- IT1:
This bit selects the external interrupt event type on INT1 pin,
1= sets interrupt on falling edge
0= sets interrupt on low level
Bit 1- IE0:
Interrupt0 edge flag, set by hardware when interrupt on INT0 pin occurred and cleared by
hardware when an interrupt is processed.
Bit 0 - IT0:
This bit selects the external interrupt event type on the INT0 pin.
1= sets interrupt on falling edge
0= sets interrupt on low level