MODULE – 3

Interrupt & Interrupt handling – Hardware and Software interrupt

Interrupt
• Interrupt is signals send by an external device to the processor, to request the
processor to perform a particular task or work.

Interrupt Process in 8085

• The processor will check the interrupts always at the last machine cycle of each
instruction.
• ̅̅̅̅̅̅̅ signal to the
If there is any interrupt, it accepts the interrupt and sends the 𝐼𝑁𝑇𝐴
peripheral.
• The current value of program counter will be saved to stack and starting address
(vector address) of interrupt service routine (ISR) will be copied to program counter.
• The processor executes an interrupt service routine (ISR) addressed in program
counter.
• It returned to main program by last instruction of ISR (RET) after retrieving the
address stored at the stack.

Maskable Interrupts and Non – Maskable Interrupt

Maskable Interrupt
• An Interrupt that can be disabled or ignored by the instructions of CPU is called as Maskable
Interrupt.

• Eg: RST 7.5, RST 6.5, RST 5.5 and INTR are maskable Interrupts.

Non-Maskable Interrupts
• An interrupt that cannot be disabled or ignored by the instructions of CPU is called as Non
Maskable Interrupt.

• Eg. TRAP interrupt is one of the non-maskable interrupts.

Vectored Interrupts
• Vectored Interrupts have fixed vector addresses, which is the starting address of the
sub-routine.
• In vectored interrupts, the processor automatically branches to the specific address in
response to an interrupt.
• Eg: TRAP, RST 7.5, RST 6.5, RST 5.5
 Non-Vectored Interrupts
• But in non -vectored interrupts the interrupted device should give the address of the
interrupt service routine (ISR).
• Non-Vectored Interrupts are those that do not have a predefined vector address.
• The INTR is not a vectored interrupt. It receives the address of the subroutine from
the external device.

Types of Interrupt
• The 8085 has multilevel interrupt system. It supports two types of interrupts
1. Hardware Interrupt 2. Software Interrupt

Software Interrupt:
• The software interrupts are program instructions. These instructions are inserted at
desired locations in a program. While running a program, lf a software interrupt
instruction is encountered, then the processor executes an interrupt service routine
(ISR)
• The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for
these interrupts can be calculated as follows.
• Interrupt number * 8 = vector address
• For eg:- for RST1, 1 * 8 = 08 = 08H So, Vector address for interrupt RST 5 is 0008H.

Hardware Interrupt:
An external device initiates the hardware interrupts by applying an appropriate signal at the
interrupt pin of the processor.
If the interrupt is accepted then the processor executes an interrupt service routine.
The 8085 has five hardware interrupts
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR

Overall interrupt structure (or) Hardware Interrupt in 8085

 • The 8085 has five hardware interrupts :
(a) TRAP (b) RST 7.5 (c) RST 6.5 (d) RST 5.5 (e) INTR
TRAP:

• This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt

enable.
• TRAP is a vectored interrupt.
• TRAP bas the highest priority.
• TRAP interrupt is edge and level triggered.
• The vector address of TRAP is 0024H
RST 7.5:
• The RST 7.5 interrupt is a maskable interrupt
• It has the second highest priority.
• It is edge sensitive.
• Maskable interrupt. It can be disabled by DI instruction.
• Enabled by EI instruction.
• The vector address of RST 7.5 is 003CH
RST 6.5 and RST 5.5
• The RST 6.5 and RST 5.5 both are level triggered.
• RST 6.5 and RST 5.5 are maskable interrupts. These can be disabled by DI
instruction.
• The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
• The vector addresses of RST 6.5 and RST 5.5 are 0034H and 002CH respectively.

INTR:

• INTR is a maskable interrupt. It can be disabled by DI instruction.

• It can be enabled by EI instruction.
• ̅̅̅̅̅̅̅ signal, it has to supply the address of
Non- vectored interrupt. After receiving 𝐼𝑁𝑇𝐴
ISR.
• It has lowest priority.
• It is a level sensitive interrupts.
The following sequence of events occurs when INTR signal goes high.

1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends an interrupt
acknowledge signal INTA to the device that interrupted.
3. In response to the acknowledge signal, interrupted device places an RST instruction on the
data
bus.
4. On receiving the instruction, the 8085 save the address of next instruction on stack and
execute received instruction.
5. Then the microprocessor executes the interrupt service routine.

Masking / Unmasking of Interrupts:

• There are four instructions used for control of interrupts :

1. EI
2. DI
3. RIM
4. SIM
EI (Enable Interrupt)

• RST 7.5, RST 6.5, RST 5.5 and INTR are enabled using EI instruction.

DI (DISABLE INTERRUPT)
• RST 7.5, RST 6.5, RST 5.5 and INTR are disabled using DI instruction.

SIM and RIM for interrupts:

• The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using
SIM instruction.
• The status of these interrupts can be read by executing RIM instruction.
• The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be
performed by moving an 8-bit data to accumulator and then executing SIM
instruction.
• The status of pending interrupts can be read from accumulator after executing RIM
instruction.
• When RIM instruction is executed an 8-bit data is loaded in accumulator, which can
be interpreted as shown in fig.
 I/O Interfacing
• Interfacing is the process of connecting devices together such that they can exchange
information.
• There are various communication devices like keyboard, printer etc. So we need to
interface these devices with microprocessor by using latches and buffers. This type of
interfacing is known as I/O interfacing.

I/O Interfacing Techniques:

I/O devices can be interfaced with microprocessor by two ways:
➢ Memory mapped I/O and
➢ I/O mapped I/O or isolated I/O.

Memory mapped IO

➢ With memory mapped I/O there is a single address space for memory and I/O devices
as shown in figure.
➢ The processor treats the I/O devices just like memory locations and uses same
instructions to access both memory and I/O devices.
➢ Single read line and single write line are required on the bus to access both memory
and I/O devices.
I/O mapped I/O or isolated I/O:

➢ With I/O mapped I/O, the memory and I/O devices are addressed separately.
➢ Processor uses different instructions for memory and I/O devices. (ie, MOV for
memory and IN,OUT for I/O)
➢ Different read and write control signals are used for memory and I/O devices as
shown in the figure below.

MEMORY INTERFACING

➢ The process of interconnecting memory with microprocessor through buses and other
hardware components is known as memory interfacing.

Address Decoding:
Address decoding is the way by which microprocessor decodes an address to select a memory
location among the total available memory locations. Two types of address decoding
techniques are there.
 • Absolute Decoding or Full Decoding
• Partial Decoding or Linear Decoding
Absolute Decoding or Full Decoding:
➢ The decoding in which all available address lines are used for decoding to select a
location is called absolute decoding technique.
➢ The figure below shows the absolute decoding technique.

This decoding technique is normally used in large memory systems.

➢ The memory map for absolute decoding is shown below.
Partial Decoding or Linear Decoding:
➢ The decoding in which all available address lines are not used for decoding to select a
location is called partial decoding technique.
➢ The figure below shows the partial decoding technique.

➢ In small systems, the hardware for decoding circuit can be eliminated by using
individual high order address lines to select memory chips. This is the partial
decoding technique.
➢ The cost of the decoding circuit can be reduced with this technique.
➢ Drawback is the possibility of having multiple addresses.
➢ The memory map for partial decoding technique is shown below.
Comparison Between Memory Mapped I/O and I/O Mapped
I/O
The table summarizes the memory capacity and address lines required for memory
interfacing.

Memory Capacity Address Lines

Required

1K= 1024 memory locations 10

2K= 2048 memory locations 11

4K= 4096 memory locations 12

8K= 8192 memory locations 13

16K= 16384 memory 14

locations

32K= 32768 memory 15

locations

64K = 65536 memory 16

locations

Example
1. Consider a system in which 32KB memory space is
implemented using four numbers of 8KB memory.
Interface the EPROM and RAM with 8085 processor

• The total memory capacity is 32KB. So, let two numbers of 8KB n memory be
EPROM and the remaining two numbers be RAM.
• Each 8KB memory requires 13 address lines and so the address lines A0 – A12 of
the processor are connected to 13 address pins of all the memory.
• The address lines and A13 – A14 can be decoded using a 2 to 4 decoder to
generate four chip select signals.
• These four chip select signals can be used to select one of the four memory IC at
any one time.
• The address line A15 is used as enable for decoder.
• The simplified schematic memory organization is shown.
 INTERFACING I/O PORTS

PROGRAMMABLE PERIPHERAL INTERFACE (PPI)-8255

Features:
• The 8255A is a general purpose programmable I/O device designed to transfer the
data from I/O to interrupt I/O under certain conditions as required. It can be used with
almost any microprocessor.
• It consists of three 8-bit bidirectional I/O ports (24 I/O lines) which can be configured
as per the requirement.

Pin Diagram
Function of pins:
• Data bus(D0-D7): These are 8-bit bi-directional buses, connected to 8086 data bus for
transferring data.
• CS: This is Active Low signal. When it is low, then data is transfer from 8085.
• Read: This is Active Low signal, when it is Low read operation will be start.
• Write: This is Active Low signal, when it is Low Write operation will be start.
• Address (A0-A1):This is used to select the ports. like this

• RESET: This is used to reset the device. That means clear control registers.
• PA0-PA7:It is the 8-bit bi-directional I/O pins used to send the data to peripheral or to
receive the data from peripheral.
• PB0-PB7: Similar to PA
 • PC0-PC7: This is also 8-bit bidirectional I/O pins. These lines are divided into two
groups.
1. PC0 to PC3(Lower Groups)
2. PC4 to PC7 (Higher groups)
These two groups can be worked separately.

Data Bus buffer:

• It is a 8-bit bidirectional Data bus.

• This tristate bi – directional buffer is used to interface the internal data bus of 8255 to
the system data bus.
• Input or Output instructions executed by the CPU either Read data from, or write data
into the buffer.
• Output data from the CPU to the ports or control register, and input data to the CPU
from the ports or status register are all passed through the buffer.
• The internal data bus and Outer pins D0-D7 pins are connected in internally.
 • The direction of data buffer is decided by Read/Control Logic.

Read/Write Control Logic:

• The control logic blocks accepts control bus signals as well as inputs from the
address bus, and issue commands to the individual group control blocks (Group A
control and Group B control).
• It issues appropriate enabling signals to access the required data/control words or
status word.
• Control signal are RD and WR
• Address signal are A0, A1 and CS
• 8255 operation is enabled or disabled by CS

Group A and Group B Controls

• Each of the Group A and Group B control blocks receives control words from the
CPU and issues appropriate commands to the ports associated with it.
• The Group A control block controls Port A and PC7 – PC4 while the Group B control
block controls Port B and PC3 – PC0.

PORT A:
• This is a 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1, mode 2 .

PORT B:
• This is a 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode 1.

PORT C:
• This is a 8-bit Unlatched buffer Input and an Output latch.
• Port C can be splitted into two parts and each can be used as control signals for Ports
A and B in the handshake mode.
• It can be programmed by bit set/reset operation.

Modes of Operation :
• Basically, there are two modes, BSR mode and I/O mode.
 BIT SET/RESET MODE:
Any one of the 8-bits of PORT C can be Set or Reset depending upon the select bits
on control word register.
• For the BSR mode, the MSB of the control word must be 0. The BSR mode handles
only the bit set and resets operations for port C: PC0 to PC7 (both upper and lower).
• In this mode, the IC functions in such a way that it can assign any binary value to any
bit of the Port C.
I/O MODE:

3 types of I/O modes are there, mode0, mode1 and mode2.

• When MSB of the control register is one (1), 8255 works in Input-Output [Link] is
further divided into three categories.
MODE 0(Simple input / Output):

• In this mode, all the three ports can be programmed either as the input or the output
port.
• In mode 0, the outputs are latched and the inputs are not latched.
• Any port can be used as an input or output port. The ports do not have handshake or
interrupt capability.
• The ports in mode – 0 can be used to interface DIP switches, Hexa – keypad, LEDs
and 7 – segment LEDs to the processor.
MODE 1 :(Strobed I/O mode)
• In this mode, only ports A and B can be programmed either as the input or output
port. In mode – 1 handshake signals are exchanged between the processor and
peripherals prior to data transfer.
• The port C pins are used for handshake signals.
• Two groups-group A and group B are available for strobed data transfer.
• Each group contains one 8-bit data I/O port and one 4 bit control port.
• Out of 8 bit port C, PC3-PC5 are used to generate control signals for port A and PC0-
PC2 are used to generate control signals for port B. The lines PC6 and PC7 may be
used as independent I/O lines.

MODE 2: Strobed bi-directional I/O mode:

• This mode allows bidirectional data transfer over a single 8-bit data bus (port A) using
handshake signals.
 • Port A is working as 8-bit bidirectional. 5 bit control port PC3-PC7 is used for
generating/accepting handshaking signals of port A.
• Here, port B and three lines of port C (PC2-PC0) may be used in either simple I/O
mode or strobed mode.
• This mode is used primarily in applications such as data transfer between two
computers or floppy disk controller interface.
• Here, port B and three lines of port C (PC2‐PC0) may be used in either simple I/O
mode or strobed mode.

Control word register format.

For Bit Set/Reset Mode(BSR)

• The eight possible combinations of the states of bits D3 – D1 (B2 B1 B0) in the Bit
Set – Reset format (BSR) determine particular bit in PC0 – PC7 being set or reset as
per the status of bit D0.
• A BSR word is to be written for each bit that is to be set or reset.
• For example, if bit PC3 is to be set and bit PC4 is to be reset, the appropriate BSR
words that will have to be loaded into the control register will be, 0xxx0111 and
0xxx1000 respectively, where x is don’t care.
• The BSR word can also be used for enabling or disabling interrupt signals generated
by Port C when the 8255 is programmed for Mode 1 or Mode 2 operation.
• This is done by setting or resetting the associated bits of the interrupts.
For I/O mode

Bit No. 0
It is for Port Clower
To make Port Clower an input port, the bit is set to 1
To make Port Clower an output port, the bit is set to 0
Bit No. 1
It is for Port B
To make Port B an input port, the bit is set to 1
To make Port B an output port, the bit is set to 0
Bit No. 2
It is for the selection of the mode for the Port B. If the Port B has
to operate in Mode 0, the bit is set to 0. For Mode 1 operation of the
port B, it is set to 1.
Bit No.3
It is for the Port CUpper
To make Port CUpper an input port, the bit is set to 1
To make Port CUpper an output port, the bit is set to 0
Bit No. 4
It is for Port A
To make Port A an input port, the bit is set to 1
To make Port A an output port, the bit is set to 0
Bit No. 5 and 6
These bits are to define the operating mode of the Port A. For the
various modes of Port A these bits are defined as follows
Mode of Port A Bit No.6 Bit No.5
Mode 0 0 0
Mode 1 0 1
Mode 2 1 0 or 1

For Mode 2 bit No.5 is set to either 0 or 1

For Example: Write the 8 bit control word to configure 8255 with the
following requirement.
PORTA as output port, PORTB as input port and PORTC as input port.
 Answer: D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 1 0 1 1

What are handshaking signals?

Handshaking signals are dedicated signals to coordinate data transfer between two devices
with different speed. The following are the commonly used handshaking signals:

STB (Strobe Input) :

This signal is generated by a peripheral device that it has transmitted a byte of data.

IBF (Input buffer full) :

This signal is an acknowledgement by the 8255 to indicate that the input latch has received
the data byte.

OBF(Output Buffer Full) :

This is an output signal that goes low when the microprocessor writes data into the output
latch of the 8255.

ACK (Acknowledge) :
This is an input signal from a peripheral that must output a low when the peripheral receives
the data from the 8255 ports.

INTERFACING SEVEN SEGMENT DISPLAY WITH 8051

➢ A seven segment display consists of seven LEDs arranged in the form of a
squarish ’8′.
➢ Different characters can be displayed by selectively glowing the required LED
segments.
➢ Seven segment displays are of two types,common cathode and common
anode.
➢ In common cathode type , the cathode of all LEDs are tied together to a single
terminal which is usually labeled as ‘com‘ and the anode of all LEDs are left
alone as individual pins labelled as a, b, c, d, e, f, g & h (or dot) .
➢ In common anode type, the anode of all LEDs are tied together as a single
terminal and cathodes are left alone as individual pins.
➢ Seven segment LED display is interfaced with 8085 using 8255 PPI.
➢ 8255 PPI is interfaced using address lines, data lines and control line RD and WR.
➢ Seven segment LED display is connected to any one of the port by configuring the
port in simple IO mode.
 ➢ Seven segment LED display used here is a common cathode type, hence When logic
1 is send to any pin of Port A, the LED will conduct the current and it will glow.
➢ When logic 0 is send to any pin of Port A, then the LEDs will be off.

Program to display various digits from 0 to 9 with a delay

The 8255 control word is written as follows:

D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0
The required ALP is as follows:

MVI A, 80 ; Initialize 8255 as output port in simple IO mode

OUT CWR

AGAIN: MVI A, 3FH

OUT Port A
CALL DELAY
MVI A, 06H
OUT Port A
CALL DELAY
MVI A, 5BH
OUT Port A
CALL DELAY
MVI A, 4FH
OUT Port A
CALL DELAY
MVI A, 66H
OUT Port A
CALL DELAY
MVI A, 6DH
OUT Port A
CALL DELAY
MVI A, 7D
OUT Port A
CALL DELAY
MVI A, 07
OUT Port A
CALL DELAY
MVI A, 7F
OUT Port A
CALL DELAY
MVI A, 67
OUT Port A
CALL DELAY

JMP AGAIN ; repeat

DELAY: MVI C, FFH ; Delay routine

BACK: DCR C
NOP
NOP

JNZ BACK
RET

Embedded System
Introduction to Embedded System

• An Embedded system is a system that has software embedded into computer hardware
which makes a system dedicated for an application.
• Embedded systems are a combination of hardware and software where software is
usually known as firmware that is embedded into the hardware.
• Software is programmed into the on chip ROM of the single chip computer.
• This software is not accessible to the user , and software solves only a limited range
of problems .
• Here the microcomputer is embedded or hidden inside the system.
• Every embedded microcomputer system , accepts inputs, performs computations,
and generates outputs and runs in “real time.”
 • Embedded systems can be classified into the following 4 categories based on their
functional and performance requirements.
1. Stand-alone embedded systems
2. Real-time embedded systems -- Hard real-time systems & Soft real-time system
3. Networked embedded systems and
4. Mobile Embedded systems.

• Based on the performance of the Microcontroller they are also classified into (i) Small
scaled embedded system (ii) Medium scaled embedded system and (iii) Large scaled
embedded system.

Stand alone Embedded systems :

• A stand-alone embedded system works by itself.
• It is a self- contained device which do not require any host system like a computer.
• It takes either digital or analog inputs from its input ports, calibrates, converts, and
processes the data, and outputs the resulting data to its attached output device, which
either displays data, or controls and drives the attached devices.

Real-time embedded systems :

• An embedded system which gives the required output in a specified time or which
strictly follows the time dead lines for completion of a task is known as a Real time
system.
• There are two types of Real time systems.(i) Soft real time system and (ii) Hard real
time system.
• Soft Real-Time system : A Real time system in which the violation of time
constraints will cause only the degraded quality, but the system can continue to
operate is known as a Soft real time system.
• Hard Real-Time system : A Real time system in which ,the violation of time
constraints will cause critical failure and loss of life or property damage or
catastrophe is known as a Hard Real time system.
• Networked embedded systems : The networked embedded systems are related to a
network with network interfaces to access the resources.
• The connected network can be a Local Area Network (LAN) or a Wide Area Network
(WAN), or the Internet.
• The connection can be either wired or wireless.

Mobile Embedded systems :

 • The portable embedded devices like mobile and cellular phones , digital camaras,MP3
players, PDA (Personal Digital Assistants) are the example for mobile embedded
systems.
• Small scaled embedded system : An embedded system supported by a single 8–16
bit Microcontroller with on-chip RAM and ROM designed to perform simple tasks is
a Small scale embedded system.
Medium scaled embedded system : An embedded system supported by 16–32 bit
Microcontroller / Microprocessor with external RAM and ROM that can perform
more complex operations is a Medium scale embedded system.
• Large scaled embedded system: An embedded system supported by 32-64 bit
multiple chips which can perform distributed jobs is considered as a Large scale
embedded system.

APPLICATION DOMAIN OF EMBEDDED SYSTEM

• The embedded systems have a huge variety of application domains. So, the embedded
systems span all aspects of our modern life. The following are various applications of
embedded systems.
1. Home Appliances Dishwasher, washing machine, microwave, Top-set box, security
system, DVD, garden sprinkler systems etc..
2 . Office Automation Fax, copy machine, smart phone system, modern, scanner,
printers.

3. Security Face recognition, finger recognition, eye recognition, building security system,
airport security system, alarm system.
4. Academia Smart board, smart room, calculator, smart cord.
5. Instrumentation Signal generator, signal processor, power supplier, Process
instrumentation,
6. Telecommunication Router, hub, cellular phone, IP phone, web camera
7. Automobile: Fuel injection controller, anti-locking brake system, airbag system, GPS,
cruise control.
8. Entertainment: MP3, video game, smart toy.
9. Aerospace: Navigation system, automatic landing system, flight attitude controller, space
explorer, space robotics.
10. Industrial automation: Assembly line, data collection system, monitoring systems on
pressure, voltage, current, temperature, hazard detecting system, industrial robot.
11. Personal: PDA, iPhone, palmtop, data organizer.
12. Medical: CT scanner, ECG, EEG, EMG, MRI, Glucose monitor, blood pressure
monitor, medical diagnostic device.
13. Banking & Finance: ATM, smart vendor machine, cash register, Share market
14. Military: control and monitoring of military equipments
15. Miscellaneous: Elevators, tread mill, smart card, security door etc.

Current trends in Embedded systems

With the fast developments in semiconductor industry and VLSI technology ,one can
find tremendous changes in the embedded system design in terms of processor speed, power,
communication interfaces including network capabilities and software developments like
operating systems and programming languages etc.

Processor speed and Power :

• With the advancements in processor technology ,the embedded systems are now days
designed with 16,32 bit processors which can work in real time environment.
• These processors are able to perform high speed signal processing activities which
resulted in the development of high definition communication devices like 3G
mobiles etc.
• Also the recent developments in VLSI technology has paved the way for low power
battery operated devices which are very handy and have high longevity.
• Also , the present day embedded systems are provided with higher memory
capabilities, so that most of them are based on tiny operating systems like android.

Communication interfaces :
• Most of the present day embedded systems are aimed at internet based
applications.
• So, the communication interfaces like Ethernet, USB, wireless LAN [Link]
become very common resources in almost all the embedded systems.
• The developments in memory technologies also helped in porting the TCP/IP
protocol stack and the HTTP server software on to the embedded systems. Such
embedded systems can provide a link between any two devices any where in the
globe.

Operating systems :
• With recent software developments, there is a considerable growth in the availability
of operating systems for embedded systems.
• Mainly new operating systems are developed which can be used in real time
applications.
 • There are both commercial RTOSes like Vx Works , QNX,WIN-CE and open source
RTOSes like RTLINUX etc.
• The Android OS in mobiles has revolutionized the embedded industry.

Programming Languages :
• There is also a remarkable development in the programming languages.
• Languages like C++, Java etc. are now widely used in embedded application
programming. For example by having the Java virtual machine in a mobile phones,
one can download Java applets from a server and can be executed on your mobile.
• In addition to these developments, now a days we also find new devices like ASICs
and FPGAs in the embedded system market. These new hardware devices are popular
as programmable devices and reconfigurable devices.

Wireless technology
• Includes all sorts of wireless devices like cellular communications, networking with
computers with wireless adapters, accessories etc

Multi core processor

• It is an integrated circuit to which two or more processors have been attached for
enhanced performance, reduced power consumption and efficient processing of
multiple task.

Multi language support

• Embedded system provides us facility of multiple languages. For example ATM is a
typical example of embedded system.
• Eg; In ATM there are three types of languages are used like English, Hindi,
Malayalam

Automation
• Automation or automatic control, is the use of various control systems for operating
equipment such as machinery, processes in factories, switching in telephone
networks, steering and stabilization of ships, aircraft and other applications with
minimal or reduced human intervention. Some processes have been completely
automated.
• The biggest benefit of automation is that it saves labor, however, it is also used to
save energy & materials, and to improves quality, accuracy & precision.

Security
• Develop a secure architecture
• Ensure system is analysed without bias and expert knowledge
• Uncover problems early and avoid defects in code
Power consumption
• Power consumption has traditionally been something influenced only by hardware
developers. But power consumption depends not only on hardware, but also on how it
is used and how it is controlled by the system software.
• It must be reduced as minimum.

User interface
• Visual part of computer application or operating system through which a user
interacts with a computer or a software.
• It determines how commands are given to the computer or the program and how
information is displayed on the screen.

Use of open source technology

• open source technology refers to a program in which the source code is available to
the general public for use and/or modification from its original design free of cost.
[Link]

Inter operatability
• Ability to work with each other
• Services can be interacting with each other without any error or misunderstanding.

Challenges in Embedded system design

• These are the challenges faced during an embedded system design

Amount and type of hardware needed

• Optimizing the microprocessors according to the performance, power dissipation, cost
and other design metrics the system.
• Optimizing hardware (memory RAM, ROM or internal and external flash or
secondary memory in the system, peripherals and devices internal and external to the
system, ports and buses in the system and power source or battery in the system).

Power Dissipation
• An embedded system need to run continuously without being switched off. So power
dissipation must be minimized.

Energy consumption
 • Challenge is to optimise energy consumption by appropriate hardware and software
design.

Process Deadlines
• Meeting the deadline of all processes in the system while keeping the memory, power
dissipation, processor clock rate and cost at minimum is a challenge

Flexibility
• A product needs to be flexible at minimum cost is a challenge.

Upgradeability
• Ability to offer the different versions of a product for marketing and offering the
product in advanced versions later on with minimum cost is a challenge.

Reliability
• Designing reliable product by appropriate design and thorough testing, verification
and validation is a challenge.

Testing, Verification and Validation

• Testing – to find errors and to validate that the implemented software is as per the
specifications and requirements to get reliable product.

Real-time embedded systems

• An embedded system which gives the required output in a specified time or which strictly
follows the time dead lines for completion of a task is known as a Real time system

• Real time system is divided into two systems

1. Hard Real Time Systems.
2. Soft Real Time Systems.
Hard Real Time Systems:
• A Hard Real-Time System guarantees that critical tasks complete on time. This goal
requires that all delays in the system be bounded from the retrieval of the stored data
to the time that it takes the operating system to finish any request made of it.
Hard real time system is purely deterministic and time constraint system for
example users expected the output for the given input in 10sec then system should
process the input data and give the output exactly by 10th second. Here in the above
example 10 sec. is the deadline to complete process for given data. Hard real systems
should complete the process and give the output by 10th second. It should not give the
output by 11th second or by 9th second, exactly by 10th second it should give the
output. In the hard real time system meeting the deadline is very important if deadline
is not met the system performance will fail.
 • Another example is defence system if a country launched a missile to another
country the missile system should reach the destiny at 4:00 to touch the ground what
if missile is launched at correct time but it reached the destination ground by 4:05
because of performance of the system, with 5 minutes of difference destination is
changed from one place to another place or even to another country. Here system
should meet the deadline.
• Another example consider the Antilock braking system in the car. When we apply
brake if the system doesn’t execute the program on time it will create severe damage.

Soft Real Time System:

• A Soft Real Time System where a critical real-time task gets priority over other tasks
and retains that priority until it completes.
• In soft real time system, the meeting of deadline is not compulsory for every time for
every task but process should get processed and give the result. Even the soft real time
systems cannot miss the deadline for every task or process according to the priority it
should meet the deadline or can miss the deadline. If system is missing the deadline
for every time the performance of the system will be worse and cannot be used by the
users. Best example for soft real time system is personal computer, audio and video
systems, etc.
• Another example of a soft real-time task is a task handling a request for a seat
reservation in a railway reservation application. Once a request for reservation is
made, the response should occur within 20 seconds on the average.
• The response may either be in the form of a printed ticket or an apology message on
account of unavailability of seats. Alternatively, we might state the constraint on the
ticketing task as: At least in case of 95% of reservation requests, the ticket should be
processed and printed in less than 20 seconds.
• Another example consider a DVD player. Suppose you give a command to the DVD
player from a remote control and there is a delay of few milliseconds in executing that
command. But this delay won’t lead to a serious problems.

HARD vs SOFT REAL TIME SYSTEM

 HARD RTS SOFT RTS
HARD RTS SOFT RTS
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Example: a car engine control system, Example: the software that maintains and
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and industrial process controllers. airliners, Live audio-video systems

8051 MICROCONTROLLER

Features of 8051
(1) 8 bit microcontroller originally developed by Intel in 1980.
(2) Highperformance CMOS Technology.
(3) Contains Total 40 pins.
(4) Address bus is of 16 bit & data bus is of 8 bit.
(5) 4K bytes internal ROM (program).
(6) 128 bytes internal RAM (data).
(7) Four 8 bit I/O ports.
(8) Two 16 bit timers.
(9) Serial interface Communication.
(10) 64K external code & data memory space.
(11) 210 bit addressable locations.
(12) Internal memory consists of on chip ROM and on chip data RAM.
(13) 8051 implements a separate memory space for programs (code) and data.
(14) Operating frequency is 24MHz-33MHz.
(15) +5V Regulated DC power supply is required to operate .
(16) It has four 8 bit ports, total 32 I/O lines.
(17) RAM, ROM, I/O ports, one serial port and timers are all on-chip.
(18) 6 interrupts (2 are external with 2 priority levels).
(19) Low power Idle and Power down Modes.
(20) Full duplex UART.
(21) 8051 has 21 special function registers (SFRs).
Registers
• The 8051 contains 34 general – purpose, or working, registers.
• Two of these, registers A and B, comprise the mathematical core of the 8051 central
processing unit (CPU).
• The other 32 are arranged as part of internal RAM in four banks, B0 -B3, of eight
registers each, named R0 to R7.

ALU
• It performs the arithmetic operations such as addition, subtraction, multiplication and
division.
• The unit can perform logical operations such as AND, OR; and Exclusive‐OR, as well
as rotate, clear, and complement.
• The ALU can also manipulate one bit as well as eight‐bit data types.
• Individual bits may be set, cleared, complemented, tested, and used in logic
computation.
Accumulator
• It is a 8 bit register
• It is used for data transfer and arithmetic operations
• All arithmetic and logic operations will be carried out in the accumulator.
• The A register is also used for all data transfers between the 8051 and any external
memory.
• Results of arithmetic and logical operations are stored in accumulator.
B Register
• An 8‐bit general‐purpose register.
• The B register is used with the A register for multiplication and division operations
and has no other function other than as a location where data may be stored.
Program Status Word:
• Many instructions implicitly or explicitly affect (or are affected by) several status
flags, which are grouped together to form the Program Status Word ( Flag
register).
• It also used to select the memory bank.
CY, the carry flag
- This flag is set whenever there is a carry out from the D7 bit.

AC, the auxiliary carry flag

- If there is a carry from D3 to D4 during an ADD or SUB operation, this bit is set; otherwise,
it is cleared.

P, the parity flag

- The parity flag reflects the number of 1 s in the A (accumulator) register only. If the A
register contains an odd number of Is, then P = 1. Therefore, P = 0 if A has an even number
of 1s.
OV, the overflow flag
- This flag is set whenever the result of a signed number operation is too large.
F0, User flag
- This flag is user defined flag. Programmer can use this flag as per the requirements.

RS1 and RS0 are used to select the register bank as follows:

Stack pointer
• The stack pointer register is 8 bit wide. Stack pointer always holds the 8 bit address at
the top of the stack.
• The 8051 microcontroller supports the LIFO(Last in first out) stack, and the stack
may reside anywhere in on chip RAM(i.e., the programmer can reserve any portion of
on chip RAM as stack)
 • After a reset the stack pointer is initialized to 07H.
• The stack can be accessed using PUSH and POP instructions.
• It is incremented before data is stored during PUSH and CALL instructions.
• During PUSH operation, the stack pointer is automatically incremented by one and
during POP operation the stack pointer is automatically decremented by one.
• The data pointer is a 16-bit register used to hold the 16-bit address of external data
memory.
• If necessary it can be used as separate two eight bit registers, DPH and DPL
• The DPH register will hold high order eight bit address and DPL register will hold
low order eight bit address.
• The 8-bit data pointers are used for accessing internal RAM and SFR.
• The 16-bit data pointer is used for accessing external data memory.
Program Counter (PC):
• It is a 16 – bit register
• PC holds the address of next instruction to be executed.
• PC automatically increments (+1) after every instruction byte is fetched.
• Program counter is the only register which does not have an internal address.
I/O Ports:
• The 8051 has four numbers of 8-bit ports namely port-0, port- 1, port-2 and port-3.
• Each port has a latch and driver (or buffer).
• When external memory is employed the port-0 lines will function as multiplexed low byte
address/data lines and port-2 lines will function as high byte address lines.
• Also the port pins P3.7 and P3.6 are used to output read and write control signals
respectively.
• The port-1 is dedicated I/O port and does not have any alternate function.

Instruction Register (IR) & timing and control unit:

• The controller will fetch the instructions one by one, starting from the address stored in PC
and store in Instruction Register, which decodes the instructions and give information to
timing and control unit.
• Using the information supplied by the IR unit the control signals necessary for internal and
external operations are generated by the timing and control unit.
Timer/Counter:
• The 8031/8051 has two 16-bit programmable timer/counter namely timer-1 and timer 0.
• In the counter mode of operation, they can count the number of high to low transitions of
the signal applied to the timer pins.
• In timer mode of operation, they can be independently programmed to work in any one of
the four operation modes. They are called mode-0, mode-1, mode-2 and mode-3.

Serial port:
• The 8031/8051 has a serial data communication circuit that uses pins RXD (P3.0) and TXD
(P3.0) for
connecting serial communication device.
• Special function registers related to serial port are SBUF, SCON and PCON.

Special function registers

• There are 21 SFRs.
In addition to I/O ports, the most frequently used SFRs to control and configure 8051
operations are:
• TCON (Timer CONtrol)
• TMOD (Timer MODe)
• TH0/TH1 and TL0/TL1 (Timer’s high and low bytes)
• SCON (Serial port CONtrol)
• IP (Interrupt Priority)
IE ( Interrupt Enable)

I/O PORTS

➢ 8051 has 32 I/O pins configured as four 8 bit parallel ports (P0 – P3).
➢ All 4 ports are bidirectional, can be configured as either input or output or both.
➢ All port pins are multifunctional except pins of Port 1.
➢ Each port consists of latch, output driver and input buffer.

PORT0:
➢ Port -0 has 8 pins identified as P0.0-P0.7.
➢ The structure of a Port-0 pin is shown below.
➢ Port-0 can be configured as a normal bidirectional I/O port or it can be used for
address/data interfacing for accessing external memory.
➢ When control is '1', the port is used for address/data interfacing. When the control is '0',
the port can be used as a normal bidirectional I/O port.
PORT 0 as an Input Port
Let us assume that control is '0'. When the port is used as an input port, '1' is written to the
latch. In this situation both the output MOSFETs are 'off'. Hence the output pin has floats
hence whatever data written on pin is directly read by read pin.

PORT 0 as an Output Port

Suppose we want to write 1 on pin of Port 0, a '1' written to the latch which turns 'off' the
lower FET while due to '0' control signal upper FET also turns off as shown in fig. above.
Here we wants logic '1' on pin but we getting floating value so to convert that floating value
into logic '1' we need to connect the pull up resistor parallel to upper FET . This is the reason
why we needed to connect pull up resistor to port 0 when we want to initialize port 0 as
an output port .

If we want to write '0' on pin of port 0 , when '0' is written to the latch, the pin is pulled down by the
lower FET. Hence the output becomes zero.

PORT-1
➢ Port-1 has 8 pins (P1.1-P1.7) .The structure of a port-1 pin is shown in fig
Port-1 does not have any alternate function i.e. it is dedicated solely for I/O interfacing.
➢ When used as output port, the pin is pulled up or down through internal pull-up.
➢ To use port-1 as input port, '1' has to be written to the latch. In this input mode the bit
written to the pin by the external device can be read the processor.
PORT-2
The structure of a port-2 pin is shown in fig. below. It has 8-pins (P2.0-P2.7) .

Port-2 is used for higher external address byte or a normal input/output port.
➢ The I/O operation is similar to Port-1.
➢ Port-2 latch remains stable when Port-2 pin are used for external memory access.
PORT-3
➢ Port-3 (P3.0-P3.7) having alternate functions to each pin. The internal structure of a port-3 pin is
shown in fig below.
Each pin of Port-3 can be individually programmed for I/O operation or for alternate
function.
➢ The alternate function can be activated only if the corresponding latch has been written
to '1'.
➢ To use the port as input port, '1' should be written to the latch.
➢ Alternate functions of Port-3 pins:

REGISTER ORGANIZATION

The 8051’s on-chip memory consists of 256 memory bytes organised as follows:

First 128 bytes: 00h to 1Fh Register Banks

 20h to 2Fh Bit Addressable RAM
30 to 7Fh General Purpose RAM

Next 128 bytes: 80h to FFh Special Function Registers

Internal RAM:
The first 128 bytes of internal memory is organised as shown in figure, and is referred
to as Internal RAM.
Register banks:
• A total of 32 bytes of RAM are set aside for the register banks and stack.
• These 32 bytes are divide into 4 banks of registers in which each bank has 8
registers, R0 – R7.
• RAM locations from 0 to 7 are set aside for bank 0 of R0 - R7 where R0 is
RAM location 0, R1 is RAM location 1, R2 is location 2, and so on, until
memory location 7, which belongs to R7 of bank 0.
• The second bank of registers R0 to R7 starts at RAM location 08 and goes to
location 0FH.
 • The third bank of R0 – R7 starts at memory location 10H and goes to location
17H.
• Finally, RAM locations 18H to 1FH are set aside for allocated into 4 banks.
• Bits RS0 and RS1 in the PSW determine which bank of registers is currently
in use at any time when program is running.
• Register banks not selected can be used as general purpose RAM.
• Bank0 is selected by default on reset.

Bit addressable memory:

• A bit addressable area of 16 bytes occupies RAM byte addresses 20h to 2Fh, forming
total of 128 bits.
• This is where individual memory bits in Internal RAM can be set or cleared.
• A bit variable can be set with a command such as SETB and cleared with a command
such as CLR. Example instructions are:
SETB 25h ; sets the bit with address 25h (becomes 1)
CLR 25h ; clears bit with address 25h (becomes 0)
• Of the 128 – byte RAM of the 8051, only 16 bytes are bit addressable. The rest must
be accessed in byte format. The bit – addressable RAM locations are 20H to 2FH.
• These 16 bytes provide 128 bits of RAM bit - addressability since 16*8 = 128.
 • They are addressed as 0 to 127 (in decimal) or 00 to 7FH. Therefore, the bit
addresses 0 to 7 are for the first byte of internal RAM location 20H, and 8 to 0FH
are the bit addresses of the second byte of RAM location 21H, and so on.
• The last byte of 2FH has bit addresses of 78H to 7FH. In the figure the internal RAM
locations 20 – 2FH are both byte – addressable and bit addressable.

A general purpose RAM:

• The RAM area above bit addressable area from 30H to 7FH is called general purpose
RAM.
• It is addressable as byte.
• These 80 bytes of Internal RAM memory are available for general-purpose data
storage.
• The only problem is that we have only 4 banks and very often the task of bank
switching and keeping track of register bank usage is tedious and prone to errors,
• For this reason in many applications we use RAM locations 30 7FH as scratch pad
and leave addresses 8 – 1FH for stack usage.
• That means that we use R0 – R7 of bank 0, and if we need more registers we simply
use RAM locations 30 – 7FH.
• The general purpose RAM can be accessed using direct or indirect addressing modes.

Examples of direct and indirect addressing:

MOV A, 6Ah ; reads contents of address 6Ah to accumulator
MOV A, @R1 ; move indirect: R1 contains address of Internal RAM which
contains data that is moved to A.

Special Function Registers (SFRs)

• The group of registers, used to perform special functions and are located immediately
above the 128 bytes of RAM are called special function registers.
• The second 128 bytes are used to store Special Function Registers (SFR) that 8051
controller program can configure and control the ports, timer, interrupts, serial
communication, and other tasks.
• The SFR is the upper area of addressable memory, from address 0x80 to 0xFF. This
area consists of a series of memory-mapped ports and registers.
• Out of these 128 Memory Locations (80H to FFH), there are only 21 locations that are
actually assigned to SFRs. Each SFR has one Byte Address and also a unique name
which specifies its purpose.
• All port input and output can therefore be performed by get and set operations on SFR
port name such as P3.
• Also, different status registers are mapped into the SFR for checking the status of the
8051, and changing some operational parameters of the 8051.
• All 8051 CPU registers, I/O ports, timers and other architecture components are
accessible in 8051 controller through SFRs
• They are accessed in normal internal RAM (080H – 0FFH) by 8051 Controller, and
they all are defined in the header file reg51.h
• The 21 Special Function Registers of 8051 Microcontroller are categorized in to seven
groups. They are:
• Math or CPU Registers: A and B
• Status Register: PSW (Program Status Word)
• Pointer Registers: DPTR (Data Pointer – DPL, DPH) and SP (Stack Pointer)
• I/O Port Latches: P0 (Port 0), P1 (Port 1), P2 (Port 2) and P3 (Port 3)
• Peripheral Control Registers: PCON, SCON, TCON, TMOD, IE and IP