Advanced STA Interview Questions & Solutions (3
Years Experience - Static Timing Analysis)
Prepared by VLSI FOR ALL / Rajat Kumar Singh
1. Explain setup and hold checks in detail. Why is hold fixing more critical?
Setup check ensures data arrives before the capturing clock edge (data_time + clock_latency +
path_delay < clock_period - setup_time). Hold check ensures data remains stable after the capturing
edge (data_time + path_delay > clock_edge + hold_time). Hold fixing is often more critical post-
route because routing reduces delay (creating faster paths), making hold failures more likely and
harder to fix without adding delays that can impact timing across many paths.
2. What is the difference between min delay and max delay analysis?
Max delay (setup) analysis checks worst-case (slow) conditions to ensure data meets setup. Min delay
(hold) analysis checks best-case (fast) conditions to ensure data doesn't change too early. They use
different corners: slow-slow for setup and fast-fast for hold (with appropriate OCV/derates).
3. Explain the concept of slack. How do negative slacks affect chip performance?
Slack = required_time - arrival_time. Positive slack means timing margin; negative slack means
violation. Negative slack (NS) indicates that the path misses timing and can cause functional
failures at the target frequency; it must be fixed by optimization (buffering, upsizing,
restructuring paths).
4. What are the differences between early mode and late mode analysis?
Early mode computes launch edge at earliest and capture at earliest—used for hold (min delay)
analysis. Late mode computes launch at latest and capture at latest—used for setup (max delay)
analysis. They reflect different timing scenarios and PVT corners.
5. How do you handle unconstrained paths?
Identify them via reports, then decide: constrain legitimately (add falsepath/MCP), remove
unexpected clocks or add proper clock definitions, or add source/primary input and sink/primary
output constraints. Unconstrained paths can cause misleading timing reports and must be resolved.
6. What is the purpose of SDC constraints? Common mistakes?
SDC captures timing intent (create_clock, set_input_delay, set_output_delay, set_false_path,
set_multicycle_path). Common mistakes: wrong clock definitions, missing generated clocks, incorrect
I/O delays, using overly broad false paths, or wrong clock groups causing mis-analysis.
7. Explain generated clocks and when they are used.
Generated clocks are derived from primary clocks (e.g., divided clocks, PLL outputs, DCC-generated
clocks). Use generated_clock in SDC to model their relationship (multiply/divide, phase/offset) so
STA tools can analyze paths involving derived clocks correctly.
8. What is the role of clock latency (source vs network)?
Source latency is delay from the clock source to the clock pin (e.g., PLL/clock buffer). Network
latency is delay within the clock tree to the sink. Clock latency affects required times and arrival
times; modeling them correctly influences setup/hold margins and insertion delay calculations.
9. What is clock uncertainty? How is it modeled in STA?
Clock uncertainty accounts for jitter and clock distribution variation—modeled as an uncertainty
term (additive margin) subtracted from available time. It can be specified as a static value or
derived from PLL/jitter reports and applied via set_clock_uncertainty or
set_clock_uncertainty_fractional.
10. Difference between propagated and ideal clocks in STA.
Propagated clocks model delays through clock buffers/CTS (more realistic) and are traced through the
netlist. Ideal clocks are instantaneous and used only for abstract analysis. Propagated clocks are
needed for accurate insertion delay/latency modeling and reconvergence analysis.
11. What are false paths and multi-cycle paths? Practical use cases.
False path: a path that cannot be sensitized for functional reasons—used to exclude non-functional
timing checks. Multi-cycle path (MCP): paths that are allowed more than one cycle to capture (e.g.,
divider outputs or register-transfer every N cycles). Both are used to reduce unnecessary fixes on
non-critical logic.
12. How do you debug a wrongly declared false path?
Revisit design intent and functional model; simulate to confirm path is unreachable, remove/adjust
false-path if incorrectly masking real violations, check clock domain crossings and handshake logic,
and use path-tracing to inspect gate-level behavior before changing SDC.
13. What is the impact of multi-cycle constraints on setup and hold checks?
MCP relaxes setup by increasing required_time (allowing multiple cycles), but hold checks may need
additional handling because launch/capture phases change—tools often require explicit handling
(set_multicycle_path with -setup or -hold flags) to manage both checks correctly.
14. Explain path groups and why we use them.
Path groups allow grouping paths sharing the same timing assumptions (e.g., same clock group or
analysis mode) so that specific exceptions, derates, or reports can be applied distinctly—helpful
for complex MCMM environments and hierarchical analysis.
15. Difference between path-based analysis (PBA) and graph-based analysis (GBA).
GBA builds timing graphs and computes arrival/required times using STA equations—fast and scalable.
PBA analyzes explicit path topologies with detailed delay calculations for specific paths—more
accurate for corner/voltage-aware checks and late-stage debugging. PBA is used for signoff-critical
path verification.
16. How does crosstalk delay affect setup/hold?
Crosstalk can add delay (or sometimes reduce delay) depending on switching patterns. Victim nets can
see increased delay (harmful for setup) or decreased delay (risking hold). STA includes coupling-
aware parasitics and may model worst-case aggressor patterns to capture crosstalk impact.
17. What are timing derates and why are they applied?
Derates (or margins) are conservative adjustments applied to delays (in/out/clock) to account for
modeling uncertainties, OCV, and signoff margins. They ensure robustness by tightening required
times or loosening arrival times based on known uncertainties.
18. Explain On-Chip Variation (OCV), AOCV, POCV.
OCV models intra-die variation. AOCV (advanced OCV) uses statistical or path-specific derates for
more accurate margins. POCV (parametric OCV) applies parametric spreads per library/corner. These
methods affect how pessimism is applied to timing analysis.
19. How does MCMM affect STA closure?
MCMM requires meeting timing across many corners and modes—often conflicting. Closure involves
prioritizing common critical paths across corners, using composite metrics, and applying mode-
specific constraints. It increases runtimes and complexity and requires strategic fixes that
generalize across corners.
20. What is CRPR (Clock Reconvergence Pessimism Removal)?
CRPR reduces artificial pessimism caused by different clock paths reconverging at a register, by
identifying and compensating for reconvergence-induced skew pessimism. Tools implement algorithms
to
remove pessimism where safe, improving slack without structural changes.
21. You see -200 ps slack in a critical setup path. How would you debug and fix it?
Identify path with report_timing; check net delays, buffer sizes, and routing-induced parasitics.
Strategies: move cells closer, upsizing cells on the path, buffer insertion or resizing, re-
synthesis logic restructuring, reduce net capacitance, and explore retiming. Also check for corner
mismatch (ensure correct corner used).
22. How do you fix hold violations in post-route STA without affecting setup?
Add localized delay (hold buffers), insert small nets or latch alignment adjustments, enable fillers
or buffer insertion at victim nets, use buffer library cells with minimal timing impact, or apply
hold-specific constraints. Avoid blanket upsizing that affects setup paths.
23. Explain buffer insertion vs cell upsizing in timing ECO.
Buffer insertion introduces delay and can break long nets to meet timing or fix hold; upsizing
increases drive strength reducing delay (helpful for setup). ECO choice depends: buffer insertion
for hold/fanout balancing; upsizing for improving setup on slow nets. Both affect power and area
trade-offs.
24. How do you prioritize fixing setup violations across corners?
Rank violating paths by slack severity, cross-corner criticality (paths failing in multiple corners
get higher priority), and product-impact (functional critical paths). Start with fixes that improve
the most corners, then target corner-specific fixes if necessary.
25. How do you analyze a timing loop in STA?
Timing loops arise from combinational loops or improper constraints. Use report_timing -loop to
identify cycles, trace netlist to find functional loops, confirm if they are intentional (e.g.,
latch feedback) or erroneous, and correct RTL or constraints. Remove artificial loops by fixing
false paths or clock definitions.
26. Which STA reports are most useful for debugging?
report_timing (detailed path), report_timing_summary (WNS/TNS), report_clock, report_skew,
report_net, report_timing -capability, and parasitic-aware reports. Use histograms and path group
reports for trend analysis.
27. What does a report_timing include and how do you read it?
report_timing shows required_time, arrival_time, slack, path endpoints, cell delays, net delays, and
transition info. Read bottom-up: slack, then per-pin arrival/required, then cell/net contributions
to understand which element causes the worst delay.
28. How do you identify the critical path in STA?
Sort report_timing by slack (worst negative slack). Review top failing paths across corners, examine
per-instance delay contributions, and trace parasitic increases from extraction. Use path-based
reports to validate criticality with extracted parasitics.
29. How do you correlate STA results with silicon timing?
Collect silicon measurements (SLA, path delays, yield data), compare with STA predicted delays,
adjust derates/OCV models, reconcile environmental differences, and update constraints or models.
Use silicon correlation to tune signoff margins and improve prediction accuracy.
30. How do you ensure timing signoff across foundry corners?
Run STA across all foundry-specified corners/modes, include PVT variations, apply appropriate
derates/OCV/AOCV, use parasitic extraction with accurate PEX decks, and validate with signoff sign-
off tools. Address corner-specific violations and use conservative margins per foundry guidance.
Notes:
- This document provides concise solutions and practical notes for advanced STA interview preparation (3
years experience).
- Customize strategies based on tool flows (PrimeTime, Tempus, OpenSTA) and foundry signoff
requirements.
- Practice with real timing reports, PEX decks, and silicon correlation data for hands-on readiness.