University of Southern California
Department of Electrical and Computer Engineering
EE557 Spring 2025
Project 3 – Memory System Simulation
Due: 11:59 PM., Tuesday, Arpil 4th
TOTAL SCORE: /5
In this project we will implement different configurations of the memory system in gem5. We will dig
a little bit deeper into gem5 and will not use the example “[Link]” file anymore. Using the knowledge
you gained from project 2, you are asked to simulate the following 4 configurations of the memory
system:
● Configuration A: No cache
● Configuration B: One level cache
● Configuration C: Two level cache
● Configuration D: Three level cache
Project Description:
As stated earlier, you are asked to implement the four configurations and then test them using a
matrix multiplication program. To give you a head start on the project, configuration C is implemented
for you and uploaded to D2L in two files:“two_level.py” and “[Link]”. Please use the same CPU,
CPU frequency, cache buses, cache specifications, … etc. for all the other configurations. Configuration
D adds a unified L3 cache which should have the same specification as L2 except the size which has to
be doubled.
Once you are done with your implementations, you should download the C program “matMul.C” and
compile it using a complier of your choice for X86 machines. Note: you can’t use the gem5 build you
had for project 2.
After simulating the behavior of the four machines using the compiled benchmark, you should report
the MIPS rating for all the runs and comment on their performance.
Now you are almost done with the project, and you are left with only one step. Change the main
memory of Configuration A to a lower power memory, for example LPDDR2_S4_1066_1x32, and
report the MIPS rating of this machine. Comment also on the change in performance.
To understand how configuration C is implemented please read the following tutorial:
[Link]
As learned in project 2, this is how you run a configuration script:
<build/{ISA}/gem5.{variant}> <configuration script> <benchmark binary>
Project Submission:
In this project, you must show that you can import gem5 modules and use them to implement a
specific design. You should also demonstrate a decent knowledge of the effect of different micro-
architectural blocks on the performance.
You must submit a report that answers the following questions:
Q1: Which design resulted in the best MIPS performance? Why?
Q2: Which design resulted in the worst MIPS performance? Why?
Q3: Was there any redundant component in any of the designs, if yes which one and Why?
Q4: Under energy constrained environment where only the provided benchmark will be used, is it
worth it to have a high-power memory for configuration A? Why?
You must submit one zipped file, which must contain the following:
● A report.
● 5 “[Link]” and “[Link]” files. One “[Link]” and one “[Link]” for each design.
● You are not allowed to change any of the gem5 source files, so please submit the only
following files for your designs:
o [Link]
o no_cache.py
o one_level.py
o two_level.py
o three_level.py
o no_cache_low_power.py
This project could be done individually or in teams of two