Creating Processor System

This material exempt per Department of Commerce license exception TSU © Copyright 2018 Xilinx
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 Embedded System Design in Zynq using IP Integrator

Creating Processor System 24- 3 © Copyright 2018 Xilinx

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Embedded Design Architecture in Zynq

Embedded design in Zynq is based on:

– Processor and peripherals
• Dual ARM® Cortex™ -A9 processors of Zynq-7000 AP SoC
• AXI interconnect
• AXI component peripherals
• Reset, clocking, debug ports
– Software platform for processing system
• Standalone OS
• C language support
• Processor services
• C drivers for hardware
– User application
• Interrupt service routines (optional)

Creating Processor System 24- 4 © Copyright 2018 Xilinx

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The PS and the PL

The Zynq-7000 AP SoC architecture consists of two major sections

– PS: Processing system
• Dual ARM Cortex-A9 processor based (Single core versions available)
• Multiple peripherals
• Hard silicon core
– PL: Programmable logic
• Uses the same 7 series programmable logic
– Artix™-based devices: Z-7010, Z-7015, and Z-7020 (high-range I/O banks only)
– Single core versions: Z-7017S, Z-7012S, and Z-7014S
– Kintex™-based devices: Z-7030, Z-7035, Z-7045, and Z-7100 (mix of high-range and high-performance I/O banks)

Creating Processor System 24- 5 © Copyright 2018 Xilinx

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Vivado

What are Vivado, IP Integrator and SDK?

– Vivado is the tool suite for Xilinx FPGA design and includes capability for embedded system design
• IP Integrator, is part of Vivado and allows block level design of the hardware part of an Embedded system
• Integrated into Vivado
• Vivado includes all the tools, IP, and documentation that are required for designing systems with the Zynq-7000
AP SoC hard core and/or Xilinx MicroBlaze soft core processor
• Vivado + IPI replaces ISE/EDK
– SDK is an Eclipse-based software design environment
• Enables the integration of hardware and software components
• Links from Vivado

Vivado is the overall project manager and is used for developing non-embedded
hardware and instantiating embedded systems
– Vivado/IP Integrator flow is recommended for developing Zynq embedded systems

Creating Processor System 24- 6 © Copyright 2018 Xilinx

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Embedded System Design using Vivado
[Link]

1. Launch Vivado
2. Create Block Design

IP Integrator
3. Add PS7
4. Configure PS settings
5. Run Block Automation
6. Add and configure IPs
7. Run Connection Automation
12. Create Board Support Package
8. Create Top-Level HDL 13. Create or add Software Project
9. Add Constraints (file) 14. Build application => .elf
10. Generate Bitstream => .bit
11. Export hardware to SDK SDK
Vivado 15. Program bitstream & .elf into Zynq

ZedBoard Zybo

Creating Processor System 24- 7 © Copyright 2018 Xilinx

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 Creating IP-XACT Hardware Accelerator

Creating Processor System 24- 8 © Copyright 2018 Xilinx

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Port-Level Interfaces

The AXI4 interfaces supported by Vivado HLS include

– The AXI4-Stream (axis)
• Specify on input arguments or output arguments only, not on input/output arguments
– The AXI4 master (m_axi)
• Specify on arrays and pointers (and references in C++) only. You can group multiple arguments into the same
AXI4-Lite interface using the bundle option
– The AXI4-Lite (s_axilite)
• Specify on any type of argument except arrays. You can group multiple arguments into the same AXI4-Lite
interface using the bundle option

Creating Processor System 24- 9 © Copyright 2018 Xilinx

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Interface Modes

Native AXI Interfaces

– AXI4 Slave Lite, AXI4 Master, AXI Stream supported by INTERFACE directive
• Provided in RTL after Synthesis
• Supported by C/RTL Co-simulation
• Supported for Verilog and VHDL axis
s_axilite
m_axi
BRAM Memory Interface
– Identical IO protocol to ap_memory
– Bundled differently in IP Integrator
• Provides easier integration to memories with BRAM interface
bram

Creating Processor System 24- 10 © Copyright 2018 Xilinx

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Native AXI Slave Lite Interface

Interface Mode: s_axilite

– Supported with INTERFACE directive
– Multiple ports may be grouped into the same Slave Lite interface
• All ports which use the same bundle name are grouped

Grouped Ports
– Default mode is ap_none for input ports
– Default mode is ap_vld for output ports
– Default mode ap_ctrl_hs for function (return port)
– Default mode can be changed with additional INTERFACE
directives
void example(char *a, char *b, char *c)
{
#pragma HLS INTERFACE s_axilite port=return bundle=BUS_A
#pragma HLS INTERFACE s_axilite port=a bundle=BUS_A
#pragma HLS INTERFACE s_axilite port=b bundle=BUS_A
#pragma HLS INTERFACE s_axilite port=c bundle=BUS_A
#pragma HLS INTERFACE ap_hs port=a
#pragma HLS INTERFACE ap_vld port=b
#pragma HLS INTERFACE ap_none port=c register

Creating Processor System 24- 11 © Copyright 2018 Xilinx

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Controllable Register Maps in AXI4 Lite

Assigning offset to array (RAM) interfaces

– Specified value is offset to base of array
– Array’s address space is always contiguous and linear

void hls_sig_gen_bram2axis(hls::stream<axis_last_t<data_t> >& dout,

data_t sig_buf[MAX_SIG_PERIOD], short sig_period)
{
#pragma HLS INTERFACE port=return s_axilite bundle=ctrl
#pragma HLS INTERFACE port=sig_buf s_axilite bundle=ctrl offset=0x1000
#pragma HLS INTERFACE port=sig_period s_axilite bundle=ctrl offset=0x0400

C Driver Files include offset information

– In generated driver file xhls_sig_gen_bram2axis.h

...
#define XHLS_SIG_GEN_BRAM2AXIS_CTRL_ADDR_SIG_PERIOD_DATA 0x0400
...
#define XHLS_SIG_GEN_BRAM2AXIS_CTRL_ADDR_SIG_BUF_BASE 0x1000
#define XHLS_SIG_GEN_BRAM2AXIS_CTRL_ADDR_SIG_BUF_HIGH 0x17ff
...

Creating Processor System 24- 12 © Copyright 2018 Xilinx

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Native AXI4 Master

Interface Mode: m_axi

– Supported with INTERFACE directive
Options
– Multiple ports may be grouped into the same AXI4 Master interface
• All ports which use the same bundle name are grouped
– Depth option is required for C/RTL co-simulation
• Required for pointers, not arrays
• Set to the number of values read/written
– Option to support offset or base address

void example(volatile int *a)

{

#pragma HLS INTERFACE m_axi depth=50 port=a

Creating Processor System 24- 13 © Copyright 2018 Xilinx

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Burst Accesses Inferred for AXI4 Master

There are two types of accesses on an AXI Master

Single Access Burst Access
void example(int *a) void example(int *a)
{ {
#pragma HLS INTERFACE m_axi port=a depth=... #pragma HLS INTERFACE m_axi port=a depth=...
... ...
int val[i] = *(a + i); memcpy(vals, a, N * sizeof(int));
... ...

– Burst accesses are more efficient

– Burst access has until now required the use of memcpy()
Burst Accesses are now inferred
– From operations in a for-loop and from sequential operations in the code
– However: there are some limitations
• Single for-loops only, no nested loops

Creating Processor System 24- 18 © Copyright 2018 Xilinx

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Byte-Enable Accesses on AXI4 Master

Byte-Enable Accesses Support on AXI4 Master Interfaces

– Single bytes are now written and read
– Improved AXI4 Master performance
Improved Performance
– This code uses 8-bit data
void example(volatile char *a) {

#pragma HLS INTERFACE m_axi depth=50 port=a

• Previously, accessing this required reading/writing full 32-bit

• This implied a required read-modify-write behavior: Impacted performance
– Similar performance improvement when accessing struct members
• Also often implied read-modify-write behavior
– Improved Port Bundling
• Variables of different sizes can be grouped into same AXI4 Master port

Creating Processor System 24- 19 © Copyright 2018 Xilinx

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AXI4 Port Bundling

AXI4 Master and Lite Port Bundling

– The bundle options groups arguments into the same AXI4 port
– For example, group 3 arguments into AXI4 port “ctrl” :
void hls_sig_gen_bram2axis(hls::stream<data_t>& dout,
data_t sig_buf[MAX_SIG_PERIOD], short sig_period)
{
#pragma HLS INTERFACE port=return s_axilite bundle=ctrl
#pragma HLS INTERFACE port=sig_buf s_axilite bundle=ctrl
#pragma HLS INTERFACE port=sig_period s_axilite bundle=ctrl
#pragma HLS INTERFACE port=dout axis

Arguments can be Bundled into AXI4 Master and AXI4 Lite ports
– If no bundle name is used a default name is used for all arguments
• All go into a single AXI4 Master or AXI4 Lite
• Default name applied if no –bundle option is used
– Group different sized variables into an AXI4 Master port

Creating Processor System 24- 20 © Copyright 2018 Xilinx

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AXI4 Stream Interface: Ease of Use

Native Support for AXI4 Stream Interfaces

– Native = An AXI4 Stream can be specified with set_directive_interface
• No longer required to set the interface then add a resource
• This AXI4 Stream interface is part of the HDL after synthesis
• This AXI4 Stream interface is simulated by RTL co-simulation

Interface Type “axis” is AXI4 Stream

set_directive_interface –mode axis “foo” portA

Or
#pragma HLS interface axis port=portA

Creating Processor System 24- 21 © Copyright 2018 Xilinx

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Generate the hardware accelerator

Select Solution > Export RTL

Select IP Catalog, System Generator for Vivado
or design check point (dcp)
Click on Configuration… if you want to change
the version number or other information
– Default is v1_00_a

Click on OK
– The directory (ip) will be generated under the impl folder
under the current project directory and current
solution
– RTL code will be generated, both for Verilog and VHDL
languages in their respective folders

Creating Processor System 24- 22 © Copyright 2018 Xilinx

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Generated impl Directory

Point IP Catalog to
point to the ip directory

IP Integrator will use

this file

XSDK will use this

directory

Header file for slave

interfaces

Generated Verilog RTL Files

Creating Processor System 24- 23 © Copyright 2018 Xilinx

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C Driver API for AXI4-Lite Interface

Creating Processor System 24- 24 © Copyright 2018 Xilinx

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 Integrating the Hardware Accelerator in AXI System

Creating Processor System 24- 25 © Copyright 2018 Xilinx

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Embedded System Design using Vivado
Create a new Vivado project, or open an existing project
Invoke IP Integrator
Construct(modify) the hardware portion of the embedded design by adding the IP-XACT
hardware accelerator created in Vivado HLS
Create (Update) top level HDL wrapper
Synthesize any non-embedded components and implement in Vivado
Export the hardware description, and launch XSDK
Create a new software board support package and application projects in the XSDK
Compile the software with the GNU cross-compiler in XSDK
Download the programmable logic’s completed bitstream using Xilinx Tools > Program
FPGA in XSDK
Use XSDK to download and execute the program (the ELF file)

Creating Processor System 24- 26 © Copyright 2018 Xilinx

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Creating Processor System 24- 27 © Copyright 2018 Xilinx
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Creating Processor System 24- 28 © Copyright 2018 Xilinx
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