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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

RISC-V CPU Design Using RRAM-CMOS

Standard Cells
Markus Fritscher , Max Uhlmann , Member, IEEE, Philip Ostrovskyy , Daniel Reiser , Junchao Chen ,
Jianan Wen , Carsten Schulze, Gerhard Kahmen , Senior Member, IEEE, Dietmar Fey ,
Marc Reichenbach , Milos Krstic , and Christian Wenger

Abstract—The breakdown of Dennard scaling has been the improvements. In recent years, researchers have repeatedly
driver for many innovations such as multicore CPUs and has revisited this law to investigate whether it is still applica-
fueled the research into novel devices such as resistive random ble [2] [3]. Razavieh et al. [4] have demonstrated that various
access memory (RRAM). These devices might be a means to
extend the scalability of integrated circuits since they allow challenges will need to be faced successfully to further scale
for fast and nonvolatile operation. Unfortunately, large analog down CMOS technology since it is approaching the boundary
circuits need to be designed and integrated in order to benefit of device physics.
from these cells, hindering the implementation of large systems. Novel technology such as memristive devices [5] and its
This work elaborates on a novel solution, namely, creating digital implementations such as RRAM have been integrated into
standard cells utilizing RRAM devices. Albeit this approach can
be used both for small gates and large macroblocks, we illustrate small process nodes and might help with prolonging the
it for a 2T2R-cell. Since RRAM devices can be vertically stacked validity of Moore’s law. Shen et al. [6] have managed to
with transistors, this enables us to construct a NAND standard integrate a 0.03-µ2 RRAM cell into a 28-nm CMOS process.
cell, which merely consumes the area of two transistors. This This renders them an ideal candidate for the design of future
leads to a 25% area reduction compared to an equivalent CMOS high-density ASICs.
NAND gate. We illustrate achievable area savings with a half-
adder circuit and integrate this novel cell into a digital standard RRAM-based building blocks such as crossbars or logic
cell library. A synthesized RISC-V core using RRAM-based cells cells were able to present promising results regarding power
results in a 10.7% smaller area than the equivalent design using and area consumption [7]. However, these blocks are difficult
standard CMOS gates. to integrate into large systems since each individual RRAM
Index Terms—Application-specific integrated circuit, circuit design requires the development of sophisticated and complex
synthesis, logic gates, resistive random access memory (RRAM), analog circuitry. While mixed-signal ASIC-design method-
RISC-V, VLSI. ologies exist these circuits are on the verge of being too
computationally expensive to simulate. This strongly hinders
I. I NTRODUCTION validation and renders meeting timing constraints given by the
digital parts a difficult endeavor.
S HORTLY after the introduction of CMOS technology,
Moore successfully predicted that about every 18 months,
the number of components in an integrated circuit would
The digital ASIC design flow provides approaches to deal
with the ever-increasing complexity of designs. One of these
is the digital standard cell flow, which is used to design large
double [1]. For decades, this has been one of the main drivers
chips from digital standard cells and an HDL description in a
of the semiconductor industry, leading to vast performance
semiautomated way.
Received 18 November 2024; revised 14 February 2025; accepted 8 Moving the RRAM design flow toward this digital stan-
March 2025. This work was supported in part by DFG through the dard cell approach might help mitigate these issues. Small
Project HYB-RISC under Grant 536099247 and DFG through the SPP
MemrisTec under Grant 422738993 and in part by BMBF through the
RRAM-based digital standard cells can serve as basic building
Project KI-IoT under Grant 16ME0092 and the BMBF through the blocks for much larger designs. Given that these cells are
Project iCampus II under Grant 16ES1128K. (Corresponding author: comparatively small, thorough simulations can be undertaken
Markus Fritscher.) to create the timing and power characterizations, which are
Markus Fritscher, Gerhard Kahmen, and Christian Wenger are with IHP -
Leibniz Institut für Innovative Mikroelektronik, 15236 Frankfurt an der required for the digital design flow. This concept is depicted in
Oder, Germany, and also with BTU Cottbus-Senftenberg, 01968 Senftenberg, Fig. 1. Instead of designing large analog blocks, which requires
Germany (e-mail: fritscher@[Link]).
Max Uhlmann, Philip Ostrovskyy, Junchao Chen, Jianan Wen, and Carsten
great care at the analog interfaces, digital cells are being
Schulze are with IHP - Leibniz Institut für Innovative Mikroelektronik, 15236 used, using pure digital inputs and outputs. The successfully
Frankfurt an der Oder, Germany. characterized cells are then provided to the digital synthesis
Daniel Reiser and Marc Reichenbach are with the University of Rostock, tool and put together to form large RRAM-based systems such
18051 Rostock, Germany.
Dietmar Fey is with FAU Erlangen Nürnberg, 91054 Erlangen, Germany. as an RRAM-based RISC-V CPU. This ultimately severely
Milos Krstic is with IHP - Leibniz Institut für Innovative Mikroelektronik, reduces integration timescales and overall design efforts. We
15236 Frankfurt an der Oder, Germany, and also with the University of
Potsdam, 14469 Potsdam, Germany.
believe that this might be one of the last stepping stones
Digital Object Identifier 10.1109/TVLSI.2025.3554476. required for the system integration of RRAM-based cells.

© 2025 The Authors. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
For more information, see [Link]
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

and did individual synthesis procedures to allow for a

more thorough comparison.

II. BACKGROUND AND M OTIVATION

A. RRAM Devices
RRAM can store information by changing the resistance
within a dielectric material. Different dielectric materials have
Fig. 1. Moving the design of RRAM-based systems from analog circuits
to digital standard cells significantly eases the design of large systems. been investigated, one of the most commonly used being
However, integrating RRAM-based designs using the traditional simulative HfO2 . It is a promising emerging technology due to both its
characterization flow poses difficulties. We propose a possible solution and nonvolatility and its high density [10].
demonstrate area benefits.
IHP’s SiGe BiCMOS 130-nm RRAM technology was used
for the fabrication of our devices.1 This RRAM device consists
While this digital standard cell approach is not new, to the of a metal–insulator–metal (MIM) stack (0.4 µm2 ) embedding
best of the authors’ knowledge, this has yet to be applied to a 150-nm TiN top electrode, a 7-nm Ti layer, and an 8-nm
RRAM-based designs. HfO2 switching layer grown by atomic layer deposition [11],
Unfortunately, implementing characterizing simulations for [12]. As part of this work, we will illustrate the potential of
RRAM-based cells is difficult since the current generation of this technology by demonstrating a working vertical stack of
RRAM models was not created with this application in mind. a memristor with a transistor.
First, they are mostly written in Verilog-A, which is difficult Accurate device models are required for the reliable
to integrate with common characterization tools. Second, a design of circuits and systems. While a significant number
significant fraction of RRAM models are merely fit to static of models has been devised, covering different aspects of
measurements, resulting in nonaccurate timing simulations. devices [13] [14], those might not represent actual device
The latter prevents both the synthesis and the place-and-route behavior, especially when the models were only fit to and/or
tool from adequately taking propagation delays and power validated for a limited set of experimental data. Hajri et al.
spikes into account, leading to the synthesis of faulty cir- [15] have compared various models with experimental data
cuits. Subsequently, we propose a way to directly incorporate and found significant deviations. Earlier models such as [16]
measurement data into the characterization flow, providing the were based on SPICE, which can be integrated seamlessly into
synthesis tool with adequately accurate information. the simulation and characterization flow. However, researchers
Our contributions can be summarized as follows: found that they need to accommodate device physics into com-
1) integration of RRAM-based standard cells into the dig- pact models, requiring the integration of complex differential
ital standard cell-based design flow; equations. This requires utilizing the Verilog-A language [17],
2) direct incorporation of measurement data into the char- [18], which hinders their application due to computational
acterization flow to mitigate complex/inaccurate RRAM requirements and limited tool support.
models; In order to mitigate these problems, we will embed raw
3) fabrication and validation of vertically stacked 1T1R measurement data into our proposed characterization flow.
devices and characterization of digital standard cells This enables us to create pure digital cells and models, which
based on RRAM; are accurate to actual device behavior.
4) proposition of an RRAM-NAND gate using the effective
area of two transistors, leading to area savings of 25%; B. Memristive Logic
5) illustration of the flexibility of our approach by syn-
Researchers have devised various memristive logic cells,
thesizing an RISC-V embedding RRAM-based standard
and the concept of synthesizing logic into multiple RRAM
cells
cells has been thoroughly investigated. Kvatinsky et al. [19]
This article is the extension of an article presented at the have devised a logic family named MAGIC, which solely
ISVLSI conference [8]. While the overall structure remains, consists of memristors. This proposed logic family is not
we added the following contributions. limited to individual gates; the authors suggest an approach to
1) We performed a thorough measurement campaign to combine multiple gates within an RRAM crossbar. Shirinzadeh
investigate whether an in-forming procedure of RRAM et al. [20] have spent further efforts, proposing a way for
devices can be implemented successfully. automated crossbar logic synthesis, which has been extended
2) We added further relevant related work. later [21]. Unfortunately, these efforts lack integration into the
3) Since RRAM devices are unlikely to reliably achieve digital flow; these works operate on the analog level, and
a failure rate of 0%, the surrounding system needs to the layout needs to be created manually. In addition, when
be able to cope with possible failures. We describe the using this crossbar approach, complex logic operations require
possible adoption of the Tetrisc platform [9] for this multiple clock cycles and sophisticated control circuitry [22],
endeavor. hindering system integration and possibly counteracting effi-
4) The previous publication limited the comparison to ciency improvements. Another family of logic cells has been
rather simple structures. In order to provide more
insights, we sliced the RISC-V core into its subparts 1 Leibniz-Institut für innovative Mikroelektronik.
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FRITSCHER et al.: RISC-V CPU DESIGN USING RRAM-CMOS STANDARD CELLS 3

devised, namely, memristor ratioed logic [23], which adds the

possibility to add a CMOS inverter, rendering the integration
into larger circuits significantly easier due to well-defined
output levels. Both Bende et al. [24] and Brackmann et al. [25]
have recently experimentally validated its functionality within
a crossbar. While this does not directly translate to individual
fully integrateable gates, this emphasizes the practicality of
the concept. Researchers have devised expansions of these
blocks such as the implementation of ternary logic [26] or
reconfigurable logic cells [27].
As mentioned before, none of these works integrate the logic
cells into the digital flow, preventing the automated synthesis
and layout of ASICs, and forcing the designer to create the
layout manually. The main focus of this work is to fill this gap.
More thorough overviews have been compiled by others [28],
[29], [30].

III. 1T-1R S TRUCTURE AND CMOS I NTEGRATION

This section introduces the vertical stack ultimately leading
Fig. 2. (a) STEM image of the vertical stack (the red circle indicates
to area savings, the cell that we use as an example, and the the RRAM device, while the blue circle indicates the transistor). (b) I/V
involved equipment. characteristics of 100 1T-1R RRAM devices (the bold black line represents
the mean value). (c) Transfer characteristics Vds /Ids of the transistor, ranging
Vg from 0 to 3.6 V (different colors). (a) STEM image. (b) RRAM I/V curve.
A. Vertically Stacked 1T1R Configuration (c) FET VDS .

The RRAM devices fabricated at IHP are located in between

the Metal 2 layer and the Metal 3 layer, which subsequently
allows for the reduction of footprint, since it can be physically
placed on top of a transistor. RRAM devices have to be initial- a promising candidate regarding standard cell compatibility.
ized during a so-called forming procedure, which initializes the Furthermore, we selected the NAND gate as a test vehicle
filament. This poses challenges for RRAM circuits, which are since it has been shown that any combinatorial logic can be
supposed to be fully integrated into digital logic, which is why derived from a combination of NAND gates. The corresponding
we propose an “in-logic-forming” procedure in a later section. schematics are depicted in Fig. 3. The left schematic depicts a
Fig. 2(a) illustrates the physical configuration. We have taken commonly used CMOS NAND gate, consisting of two PMOS-
a scanning transmission electron microscopy (STEM) image and two NMOS transistors. The schematic shown on the right
using a TEM FEI Tecnai Osiris to demonstrate the vertical depicts an RRAM version of a NAND, which is a combination
nature of this stack. of two memristors and a biased inverter. The vertical stacking
We measured the transfer characteristics of the transistor and of RRAM and transistor (as depicted in Fig. 2) enables
cycled the RRAM device 100 times in order to demonstrate the RRAM-enhanced version to be more area-efficient since,
the vertical stack’s functionality. The transistors’ transfer char- merely, the area of Q1 and Q2 is needed.
acteristics Vds /Ids are depicted in Fig. 2(c). We increased the Multiple explanations for the inner workings of this gate
gate voltage linearly from 0 to 3.6 V, increasing the voltage in are viable. Kvatinsky et al. [23] proposed that the two RRAM
steps of 0.6 V. The results indicate that the stacked transistor devices implement an AND gate, changing their resistance
is working as expected. Subsequently, we used the transistor when the inputs change. According to their findings, the
to both form and continuously set and reset the RRAM device two transistors at the output merely act as an inverter, con-
100 times using the following parameters. verting the AND gate to a NAND gate. However, previous
1) Forming: Vgate : 1.7 V; VT E : dc sweep (0 V. . .4 V). research suggests that RRAM devices are unlikely to switch
2) Set: Vgate : 1.4 V; VT E : dc sweep (0 V. . .1.5 V). reliably after as many cycles as we applied in the mea-
3) Reset: Vgate : 2.7 V; VT E : dc sweep (0 V. . .−1.5 V). surements depicted in Section V-B2. In addition, if both
This leads to the plot depicted in Fig. 2(b). The thick black devices switched [e.g., when changing the inputs from (0, 1) to
line depicts the mean current for a given voltage, and the (1, 0)], dynamic hazards should be visible, while the switch-
other lines depict individual cycles. This indicates that both ing process concludes. Another possible explanation for the
the RRAM device and the transistor work reliably in this gate’s functionality lies within both RRAM devices regulating
configuration. themselves toward a similar resistance. Since the inverter is
biased toward Vdd , our simulative investigations found that two
sufficiently similar resistances would successfully implement
B. Proposed RRAM-Based NAND Schematics NAND functionality without further device switching. Doing a
We selected the MRL (see Section II-B) as a starting point thorough investigation of this phenomenon would be beyond
for our investigation since the inverter at its output renders it the scope of this work and will be part of a future publication.
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 3. Comparison of pure CMOS (left) and RRAM-CMOS NAND (right).

Fig. 4. Probes connected for the forming operation.

C. Forming Procedure of RRAM Devices

RRAM cells need to be initialized with a so-called forming
procedure [10]. While this has been successfully implemented
for 1T1R crossbars, which enable strong control over both
applied voltages and applied currents, this is more difficult for
small logic cells. Adding a dedicated forming circuit to each
individual cell yields overhead, which would nullify the area
advantages. In addition, forming might require voltages, which
Fig. 5. Traditional flow to create standard cells clearly separates creating the
are too high for the comparatively small transistors commonly design (brown) and characterizing the design (red). We propose to intermix
used for digital logic. them, enriching the characterization simulations with measurements to make
Researchers are currently investigating different stacks to up for inaccurate models.
lower the forming voltage. One of these approaches consists
of doping the HfO2 stack with aluminum, forming an Al:HfO2 A. Overview
stack, partially reducing the required forming voltages [31],
enabling the integration with low-voltage transistors. The Both the state-of-the-art approach to creating digital stan-
filaments of a fraction of the used RRAM devices were dard cells and our proposal are depicted in Fig. 5. There are
formed at voltages below 1.5 V, which is in line with our two major steps: creating the design (brown) and characteriz-
investigations. ing the design (red). The next step after creating the schematic
Subsequently, in-logic forming operations can be imple- and layout of a cell typically consists of validation, which
mented by: 1) applying proper logic inputs to individual cells entails tapping out the design and measuring its functionality.
and 2) providing a dedicated switchable forming port, which Once this is done, the design netlist is exported and handed
is connected in parallel for a reasonably large number of over to a characterization tool (e.g., Cadence Liberate). The
cells. This adds additional input capacitance to the cell, which tool performs various simulations in order to determine char-
will have to be considered during characterization. However, acteristics such as the cell timing, power characteristics, and
using dedicated ports is not feasible for gates, which are input capacitance and exports the files required for the digital
deeply integrated into a logic circuit. This is why we propose flow. This typically forms a digital standard cell library.
and implement an in-logic forming operation, which does not While this separation works well for pure CMOS circuits,
require additional ports and can be performed just by applying this approach has to be adapted for RRAM-based cells. We
corresponding logic inputs in a later section. propose to enrich the characterization with measurement data
in order to accurately depict device characteristics.

D. Measurement Equipment B. Generation of the Liberty Skeleton

We use a Keithley 4200-SCS combined with a semiauto- In the traditional flow, the only interaction between
mated wafer prober to form the individual RRAM devices “creating the design” and “characterizing the design” consists
within the logic gates and an Advantest V93000 to perform of extracting and importing the netlist. Subsequently, the first
the gate characterizations. Fig. 4 illustrates the wafer during step toward a characterized library is to define arcs, which
one of the forming operations. describe all possible changes at the inputs. An example of a
NAND gate might look like this:
1) A high + B falling/rising;
IV. C HARACTERIZATION OF RRAM-BASED CMOS C ELLS
2) B high + A falling/rising.
This section describes how we propose to integrate RRAM- The characterization tool runs a simulation for each of these
based logic cells into the digital ASIC flow by adapting and arcs to determine the circuit’s behavior (see Fig. 6). In this
extending the flow commonly used to characterize digital example, the tool would determine that the output has settled
standard cells. These can then be used to synthesize more after 200 ps and create an entry in the liberty file accordingly.
complex structures such as multipliers or entire CPUs. Similarly, additional simulations are run for other relevant
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FRITSCHER et al.: RISC-V CPU DESIGN USING RRAM-CMOS STANDARD CELLS 5

Fig. 6. Timing arc simulation for the RRAM-based schematic shown in Fig 3.
Keeping node A [schematic in Fig 3 (right)] constant while dropping node B
from a logic 1 to a logic 0 leads to the depicted output swing at node C. The
output settles after about 200 ps.

Fig. 8. Two instances of the proposed RRAM-NAND gate (red boxes) fully
compatible with pure CMOS gates within a grid row.

Fig. 7. Proposed method to introduce measurements to the characterization.

be used by the designer. The same approach can be applied
to far more complicated cells; however, great care must be
characteristics. While the tool might be able to detect nec- taken to appropriately select the involved arcs. Since the
essary arcs automatically, we found that it does not properly number of arcs exponentially increases with the number of
recognize RRAM-based cells, requiring manual arc definition. pins, more automated approaches need to be developed in
order to accommodate them.
C. Integration of Experimental Data Into the Digital Cell
V. E VALUATION OF THE P ROPOSED A PPROACH
The proposed approach to implement the experimental data
to the characterization is depicted in Fig. 7. We use scripts to Within this section, we will use the methodology described
automatically derive parameters such as timing or power con- earlier to implement a digital RRAM-based NAND cell with a
sumption from raw data and use these to replace entries within small area footprint and compare it to traditional CMOS cells.
the Liberty library. These need to be reimported and exported
to both get consistent libraries and get accurately annotated A. Layout of RRAM-Based NAND Devices
behavioral Verilog descriptions. This multistep approach is The layout of the implemented RRAM-NAND is illustrated
required to provide enough information to the tool to generate in Fig. 8. One can see the vertically stacked transistors and
a Liberty skeleton. RRAM devices (orange). Since the RRAM devices are cur-
According to the simulated arc depicted in Fig. 6, the rently situated between Metal 2 and Metal 3, a corresponding
logic gates output settles within 200 ps. Hosoi et al. [32] via stack is required (middle). This layout uses an area of
devised a way to switch RRAMs using 50-ns pulses, while 5.16 µm2 , which is 25% smaller than the pure-CMOS-NAND
Lee et al. [33] were able to demonstrate a switching speed of implemented in a 130-nm CMOS PDK.
5 ns, which is still more than one order of magnitude slower
than the reported timing arc. Cuppers et al. [34] did thorough
B. Analog Simulation and Characterization
investigations of the switching process and found a strong
voltage–time dependence, which is not suitably represented 1) Simulation: We ran analog simulations of the gate to
by the utilized model. These investigations suggest that such both validate its functionality and have a baseline for the arcs
a fast settling time might be inaccurate for a circuit embedding required for the characterization.
RRAMs. 2) Fabrication and Measurements: We fabricated an imple-
Subsequently, measurements are required to improve the mentation of the proposed RRAM-based NAND gate in IHP
accuracy of the characterization. One needs to take at least 130-nm CMOS technology to validate its functionality and
one measurement for each arc and characterization type gather characterization measurements to include within the
and integrate this into the characterization. Similarly, input digital library. An exemplary output of the measurement
capacitance and power information need to be updated with procedure is shown in Fig. 9. We use a Vdd of 1.65 V and
measurements. apply two logic inputs A and B (shown in blue). The depicted
signal slopes are not indicative of the gates’ switching speed
since these are limited by the measurement setup.
D. Reassembling the Liberty Library We set up the inputs in such a way that each transition
Finally, the Liberty library needs to be reassembled and requires an output toggle in order to gather information for
reimported to the characterization tool in order to check for the arc characterization. As one can see, the gate outputs a
inconsistencies (such as vastly different timings) introduced logical 1 unless both inputs are set to 1, which implements
by the measurement data. If there are no inconsistencies, the NAND functionality. Since logic gates need to operate for many
cell can be exported again, yielding both a version to use cycles, we took measurements after the first cycle (orange)
by the synthesis tool and a behavioral description, which can and after (black) 2.5 × 106 cycles. The behavior is similar,
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 11. Results of applying 3e4 cycles of an in-logic-forming procedure.

Fig. 9. Inputs (blue) and outputs (black and orange) of the proposed RRAM-
based NAND for the first and after 2.5 × 106 logic cycles.

Fig. 12. This histogram illustrates the forming pulse voltages after which the
individual RRAM NAND gates were operational.
Fig. 10. Equivalent circuit used to derive the input capacitance.

TABLE I
indicating that the gate operations are applied without degra- NAND G ATE —A RCS
dation. We characterized 60 of these structures with a similar
procedure.
3) Input Capacitance: The equivalent circuit that can be
used to derive the gates’ input capacitance is given in Fig. 10.
C1 and C2 are given by the RRAM Metal 2 and Metal 3
contacts. C3 is given by the gates of Q1 and Q2 . C1 and C2
can be analytically derived from the physical dimensions to
be 80 aF. The histogram depicting the voltages after which the indi-
vidual RRAM gates were operational is depicted in Fig. 12.
All 20 gates were operational after reaching a pulse amplitude
C. In-Logic Forming of 3.2 V.
We performed an in-logic forming procedure on 20 gates
containing a total of 40 RRAM devices in order to show that
these cells can, indeed, be integrated into larger systems. In D. Digital Standard Cell Generation
order to do so, we applied the following procedure to each We used the flow described in Section IV to generate a
individual gate. digital cell. The arcs were defined, as depicted in Table I.
1) Step 1: Apply signals A and B depicted in Fig. 9 for Any possible combination of Falling (F) and Raising (R)
1 × 103 times using an amplitude of 0.1 V. transitions, which leads to a transition of the output pinout,
2) Step 2: Apply a small readout voltage of 0.2 V at pin needs to be represented with an arc.
F (see Fig. 3), ground the pins A, B in two individual Subsequently, we set up the tool to run arc simulations
measurements, and measure the current flow. and compared the results to the pure analog simulations.
3) Step 3: Evaluate successful gate operation by applying a These results are used to generate a Liberty library skeleton
single pulse, as depicted in Fig. 9. If the gate implements and are updated with measurements as described earlier. This
NAND behavior, stop; otherwise, repeat Steps 1 and 2 ultimately yields a purely digital NAND block, which is usable
while increasing the amplitude by 0.1 V. by the digital synthesis tool. We additionally extract an LEF
4) We stop the procedure when reaching 4 V and consider file from the layout to render this cell usable within the place
the gate nonoperational. and route process. Unfortunately, since the RRAM device is
The output of these current measurements is depicted in positioned between Metal 2 and Metal 3, we had to introduce
Fig. 11. Apparently, device a has been formed after cycle routing halos into the LEF accordingly, posing additional
2.1e4 (which equals 2.1 V), while device b has been formed limitations to the routing of the cells. As a future activity, we
after cycle 2.9e4 (which equals 2.9 V). This gate performs will also investigate the implementability of RRAM devices
NAND operations successfully after the 2.9-V pulses have been between Metal 1 and Metal 2, which would significantly relax
applied. this limitation.
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FRITSCHER et al.: RISC-V CPU DESIGN USING RRAM-CMOS STANDARD CELLS 7

Fig. 13. Half adder built from NAND gates.

TABLE II
T RANSISTOR C OUNT AND C ORRESPONDING A REA W HEN I MPLEMENTING
THE HA IN F IG . 13
Fig. 14. RI5CY RISC-V layout embedding about 1.5e5 instances of the
proposed RRAM-NAND cell. The core requires about 2 mm2 .

on-chip reliability monitoring network, which includes single-

event upset (SEU), aging, and temperature monitors. This
E. Half-Adder—Area Comparison network enables real-time monitoring of environmental and
We created a half adder using our RRAM-based NAND operational conditions, allowing the system to dynamically
gates to illustrate the area benefits compared to pure CMOS configure two-, three-, or four-way core redundancies to
half-adder units. A naı̈ve NAND-based half adder schematic is enhance reliability in response to changing environmental
depicted in Fig. 13. Typically, such an adder would be built demands.
using an XOR gate (typically eight transistors) combined with Since this platform was originally intended for harsh space
an AND gate (typically six transistors) since this is less area- conditions, this is a perfect candidate for the integration of
intensive than building it from NAND gates. This leads to the RRAM gates. On the one hand, RRAM gates might yield
transistor counts and the effective area, as depicted in Table II. area advantages or add further resilience to radiation. On the
The naı̈ve CMOS-RRAM version beats both the naı̈ve and other hand, if an individual gate does not perform within
optimized CMOS versions regarding area by 25% and 15%, specifications due to process variation or endurance problems,
respectively. Implementing more sophisticated gates (or entire the SoC will remain functional.
macrocells) based on RRAM is likely to further increase the 2) RI5CY RISC-V Synthesis and Layout: In order to achieve
overall area savings. this, we added the created (and enhanced) LEF, Liberty, and
Verilog files to a separate library and provided both this
and the CMOS standard cell library to the synthesis tool.
F. RISC-V Implementation Subsequently, we used this gate netlist to create a layout using
In order to emphasize the practicality of our approach, we the digital P&R flow. This yields the layout depicted in Fig 14.
synthesize an individual RI5CY RISC-V CPU core imple- We omitted both I/O cells and power distribution beyond the
menting the RV32IMC instruction set, combining the proposed power ring. This layout contains about 3 × 105 individual
RRAM-based standard cell with traditional pure-CMOS-cells. RRAM devices, which would be tedious if not impossible to
1) TETRISC Platform: The RI5CY core is a four-stage, in- implement manually.
order, 32-bit RISC-V processor designed to improve energy 3) Synthesis Results—Area Comparison: While the pre-
efficiency in ultralow-power processing applications [35]. It vious section has illustrated the feasibility of such an
fully supports the base integer instruction set, compressed implementation, this section investigates achievable area
instructions, and the multiplication extension, with an optional advantages.
configuration for single-precision floating-point instructions. We sliced the before-mentioned RISC-V core into individual
As an open-source design, RI5CY offers significant flexibility parts and performed an individual synthesis in order to investi-
and accessibility for various embedded applications, serving as gate possible area advantages of the proposed design. We used
a core element of the parallel ultralow-power (PULP) platform a stripped-down version of a 130-nm digital library, removing
developed by ETH Zurich [36] to promote energy-efficient everything but simple gates. Furthermore, we matched the
computing. involved capacitances in order to ease the comparison. While
Building on the RI5CY core, the TETRISC (TETra Core this cannot serve as a comparison to the SoA of digital design,
System based on RISC-V) SoC [9] is a resilient quad-core sys- it enables us to investigate the merits of the proposed concept.
tem. The platform’s architecture features a quad-core setup in The results are depicted in Fig. 15. While the overall core
which each core can operate independently or in fault-tolerant area decreases, individual parts benefit differently. Parts such
modes supported by core-level n-modular redundancy (NMR), as the multiplier benefit greatly while others such as the
clock-gating, and integrated on-chip monitors. TETRISC register file achieve smaller area advantages. This appears
employs an adaptive fault-tolerance mechanism using an sensible since register files are comprised of a significant
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 15. Results: we synthesized both the entire RISC-V core and individual parts, both using a stripped-down pure CMOS library and the same library with
the addition of RRAM-CMOS gates. Individual parts benefit differently from these novel cells. (a) Compared absolute numbers. (b) Percentual area reduction.
The right portion of (a) is zoomed in for improved readability. (a) Absolute numbers. (b) Area reduction.

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