Digital Electronics MCQs for VLSI Testing Interview
Logic Gates & Combinational Logic
1. The output of a NAND gate is LOW only when:
A) All inputs are HIGH
B) All inputs are LOW
C) Any input is LOW
D) Inputs are equal
Answer: A) All inputs are HIGH
2. Which of the following is a universal gate?
A) OR
B) AND
C) NOR
D) XOR
Answer: C) NOR
3. The minimum number of inputs required to implement a 4:1 multiplexer is:
A) 2
B) 4
C) 6
D) 8
Answer: C) 6 (4 data + 2 select lines)
4. A decoder with ‘n’ inputs can have a maximum of:
A) n outputs
B) 2^n outputs
C) n^2 outputs
D) 2n outputs
Answer: B) 2^n outputs
Sequential Circuits & Timing
5. A D flip-flop transfers data on:
A) Clock low-to-high transition
B) Clock high-to-low transition
C) Clock high level
D) Both edges
Answer: A) Clock low-to-high transition (in most designs)
6. What is setup time in flip-flops?
A) Minimum time data must be held after the clock
B) Minimum time data must be stable before clock edge
C) Clock-to-Q delay
D) Propagation time of logic
Answer: B) Minimum time data must be stable before clock edge
7. A race condition typically occurs in:
A) Combinational circuits
B) Multiplexers
C) Sequential circuits
D) Static RAM
Answer: C) Sequential circuits
Fault Models & Testing Basics
8. What is a stuck-at-0 fault?
A) Line always reads high
B) Line always reads low
C) Line toggles continuously
D) Flip-flop stuck in hold
Answer: B) Line always reads low
9. Which fault model considers the delay of transitions?
A) Bridging fault
B) Transition fault
C) Stuck-at fault
D) Open fault
Answer: B) Transition fault
10. Bridging fault refers to:
A) Line stuck at Vcc
B) Open connection
C) Two signals shorted together
D) Grounded net
Answer: C) Two signals shorted together
Design for Testability (DFT)
11. What is the main advantage of scan-based testing?
A) Reduces chip area
B) Increases speed
C) Improves controllability and observability
D) Reduces power consumption
Answer: C) Improves controllability and observability
12. In a scan chain, flip-flops are connected as:
A) Tree
B) Ring
C) Serial shift register
D) Parallel array
Answer: C) Serial shift register
13. The main components of BIST include:
A) Shift register and clock
B) Multiplexer and decoder
C) Pattern generator and response analyzer
D) Flip-flop and inverter
Answer: C) Pattern generator and response analyzer
14. Which of the following is an IEEE standard for boundary scan testing?
A) IEEE 802.3
B) IEEE 1149.1
C) IEEE 754
D) IEEE 1687
Answer: B) IEEE 1149.1
15. What does ATPG stand for?
A) Analog Test Pattern Generation
B) Automatic Test Point Generation
C) Automatic Test Pattern Generation
D) Active Test Path Generation
Answer: C) Automatic Test Pattern Generation
Advanced Concepts
16. Which DFT technique is suitable for testing embedded memories?
A) Scan chains
B) Boundary scan
C) Memory BIST
D) Logic BIST
Answer: C) Memory BIST
17. Fault coverage is defined as:
A) Number of flip-flops tested
B) Number of inputs tested
C) Ratio of detected faults to total possible faults
D) Time taken to test
Answer: C) Ratio of detected faults to total possible faults
18. A don’t care value (X) in a test vector means:
A) Logic 0
B) Logic 1
C) Value doesn’t affect output
D) Fault detected
Answer: C) Value doesn’t affect output
19. One major challenge in scan testing is:
A) Increased operating frequency
B) Reduced chip cost
C) Test time and area overhead
D) Higher data bandwidth
Answer: C) Test time and area overhead
20. Logic BIST is mainly used for:
A) Testing processors
B) External testing
C) On-chip self-testing of logic blocks
D) Reducing dynamic power
Answer: C) On-chip self-testing of logic blocks