NAND gate

NAND gate is a digital circuit that has two or more inputs and produces an output, which is
the inversion of logical AND of all those inputs.
The following table shows the truth table of 2-input NAND gate.

A B Y = (A.B)’

0 0 1

0 1 1

1 0 1

1 1 0

The following image shows the symbol of NAND gate, which is having two inputs A, B and
one output, Y.

NAND gate operation is same as that of AND gate followed by an inverter. That’s why the
NAND gate symbol is represented like that.
NOR gate:
NOR gate is a digital circuit that has two or more inputs and produces an output, which is
the inversion of logical OR of all those inputs.
The following table shows the truth table of 2-input NOR gate
A B Y = (A+B)’

0 0 1

0 1 0

1 0 0

1 1 0

The following figure shows the symbol of NOR gate, which is having two inputs A, B and one
output, Y.
NOR gate operation is same as that of OR gate followed by an inverter. That’s why the NOR
gate symbol is represented like that.
Special Gates
Ex-OR & Ex-NOR gates are called as special gates. Because, these two gates are special
cases of OR & NOR gates.
Ex-OR gate:
The full form of Ex-OR gate is Exclusive-OR gate. Its function is same as that of OR gate
except for some cases, when the inputs having even number of ones.
The following table shows the truth table of 2-input Ex-OR gate.

A B Y = A⊕B

0 0 0

0 1 1

1 0 1

1 1 0

The output of Ex-OR gate is ‘1’, when only one of the two inputs is ‘1’. And it is zero, when
both inputs are same.
Below figure shows the symbol of Ex-OR gate, which is having two inputs A, B and one
output, Y.

The output of Ex-OR gate is ‘1’, when odd number of ones present at the inputs. Hence, the
output of Ex-OR gate is also called as an odd function.
Ex-NOR gate:
The full form of Ex-NOR gate is Exclusive-NOR gate. Its function is same as that of NOR
gate except for some cases, when the inputs having even number of ones.
The following table shows the truth table of 2-input Ex-NOR gate.
A B Y = A⊙B

0 0 1

0 1 0

1 0 0

1 1 1
The output of Ex-NOR gate is ‘1’, when both inputs are same. And it is zero, when both the
inputs are different.
The following figure shows the symbol of Ex-NOR gate, which is having two inputs A, B and
one output, Y.

The output of Ex-NOR gate is ‘1’, when even number of ones present at the inputs. Hence,
the output of Ex-NOR gate is also called as an even function.
From the above truth tables of Ex-OR & Ex-NOR logic gates, we can easily notice that the
Ex-NOR operation is just the logical inversion of Ex-OR operation.

1.5 Universal gates and its realization:

We can realise all of the other gates by using just one single type of universal logic gate, the
NAND (NOT AND) or the NOR (NOT OR) gate, thereby reducing the number of different
types of logic gates required, and also the cost. Thus, the NAND and the NOR gates are
commonly referred to as Universal Logic Gates.
Implementation of logic gates using NAND gate only:
Implementation of logic gates using NOR gate only:

1.6 Boolean Algebra:

Boolean Algebra is used to analyse and simplify the digital (logic) circuits. It uses only the
binary numbers i.e., 0 and 1. It is also called as Binary Algebra or logical Algebra. Boolean
algebra was invented by George Boole in 1854.
Boolean Laws
There are six types of Boolean Laws.
Commutative law
Any binary operation which satisfies the following expression is referred to as commutative
operation.

Commutative law states that changing the sequence of the variables does not have any
effect on the output of a logic circuit.
Associative law
This law states that the order in which the logic operations are performed is irrelevant as
their effect is the same.

Distributive law
Distributive law states the following condition.

AND law
These laws use the AND operation. Therefore, they are called as AND laws.
OR law
These laws use the OR operation. Therefore, they are called as OR laws.

INVERSION law
This law uses the NOT operation. The inversion law states that double inversion of a variable
results in the original variable itself.

Boolean Function:
Boolean algebra deals with binary variables and logic operation. A Boolean Function is
described by an algebraic expression called Boolean expression which consists of binary
variables, the constants 0 and 1, and the logic operation symbols. Consider the following
example.

Here the left side of the equation represents the output Y. So we can state equation no. 1

Truth Table Formation

A truth table represents a table having all combinations of inputs and their corresponding
result.
It is possible to convert the switching equation into a truth table. For example, consider the
following switching equation.

The output will be high (1) if A = 1 or BC = 1 or both are 1. The truth table for this equation is
shown by Table (a). The number of rows in the truth table is 2 n where n is the number of input
variables (n=3 for the given equation). Hence there are 2 3 = 8 possible input combination of
inputs.
De Morgan’s 1st theorem states that the complement of the product of all the terms is equal
to the sum of the complement of each term.
(A.B)’ = A’ + B’

De Morgan’s 2nd theorem states that the complement of the sum of all the terms is equal to
the product of the complement of each term.
(A + B)’ = A’. B’

Duality Theorem:
This theorem states that the dual of the Boolean function is obtained by interchanging the
logical AND operator with logical OR operator and zeros with ones. For every Boolean
function, there will be a corresponding Dual function.

Group1 Group2

x+0=x x.1 = x

x+1=1 x.0 = 0

x+x=x x.x = x

x + x’ = 1 x.x’ = 0

x+y=y+x x.y = y.x

2.1 Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder
circuit is designed to add two single bit binary number A and B. It is the basic building block
for addition of two single bit numbers. This circuit has two outputs carry and sum.

Block diagram

Truth Table

Circuit Diagram

Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-
bit numbers A and B, and carry c. The full adder is a three input and two output combinational
circuit.

Block diagram
Truth Table

Circuit Diagram

Implementation of Full Adder using Half Adders

2 Half Adders and a OR gate is required to implement a Full Adder.
With this logic circuit, two bits can be added together, taking a carry from the next lower order
of magnitude, and sending a carry to the next higher order of magnitude.
Implementation of Full Adder using NAND gates:

N-Bit Parallel Adder

The Full Adder is capable of adding only two single digit binary number along with a carry
input. But in practical we need to add binary numbers which are much longer than just one
bit. To add two n-bit binary numbers we need to use the n-bit parallel adder. It uses a number
of full adders in cascade. The carry output of the previous full adder is connected to carry
input of the next full adder.
4 Bit Parallel Adder
In the block diagram, A0 and B0 represent the LSB of the four bit words A and B. Hence Full
Adder-0 is the lowest stage. Hence its Cin has been permanently made 0. The rest of the
connections are exactly same as those of n-bit parallel adder is shown in fig. The four-bit
parallel adder is a very common logic circuit.

Block diagram
Half Subtractors
Half subtractor is a combination circuit with two inputs and two outputs (difference and
borrow). It produces the difference between the two binary bits at the input and also produces
an output (Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called
as Minuend bit and B is called as Subtrahend bit.

Truth Table

Circuit Diagram

Full Subtractors
The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a
combinational circuit with three inputs A,B,C and two output D and C'. A is the 'minuend', B
is 'subtrahend', C is the 'borrow' produced by the previous stage, D is the difference output
and C' is the borrow output.

Truth Table
Circuit Diagram

2.2 Multiplexers
Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and
m select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs and
routes it to the output. The selection of one of the n inputs is done by the selected inputs.
Depending on the digital code applied at the selected inputs, one out of n data sources is
selected and transmitted to the single output Y. E is called the strobe or enable input which
is useful for the cascading. It is generally an active low terminal that means it will perform the
required operation when it is low.

Block diagram
Multiplexers come in multiple variations

 2 : 1 multiplexer
 4 : 1 multiplexer
 16 : 1 multiplexer
 32 : 1 multiplexer

Block Diagram

Truth Table

Demultiplexers
A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and
distributes it over several outputs. It has only one input, n outputs, m select input. At a time
only one output line is selected by the select lines and the input is transmitted to the selected
output line. A de-multiplexer is equivalent to a single pole multiple way switch as shown in
fig.
Demultiplexers comes in multiple variations.

 1 : 2 demultiplexer
 1 : 4 demultiplexer
 1 : 16 demultiplexer
 1 : 32 demultiplexer

Block diagram
Truth Table

4:1 Multiplexer
4:1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y.
The block diagram of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines.
Truth table of 4:1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as
𝑌 = 𝑆1′𝑆0′𝐼0 + 𝑆1′𝑆0𝐼1 + 𝑆1𝑆0′𝐼2 + 𝑆1𝑆0𝐼3
We can implement this Boolean function using Inverters, AND gates & OR gate.
The circuit diagram of 4:1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can implement
8x1 Multiplexer and 16x1 multiplexer by following the same procedure.

1:4 De-Multiplexer
1:4 De-Multiplexer has one input I, two selection lines, s 1 & s0 and four outputs Y3, Y2, Y1 &Y0.
The block diagram of 1:4 De-Multiplexer is shown in the following figure.

The single input ‘I’ will be connected to one of the four outputs, Y 3 to Y0 based on the values
of selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0
 0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each output as
𝑌3 = 𝑠1 𝑠0 𝐼
𝑌2 = 𝑠1𝑠0′𝐼
𝑌1 = 𝑠1′𝑠0𝐼
𝑌0 = 𝑠1′𝑠0′𝐼
We can implement these Boolean functions using Inverters & 3-input AND gates.
The circuit diagram of 1:4 De-Multiplexer is shown in the following figure.

Decoder
A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs. Decoder
is identical to a demultiplexer without any data input. It performs operations which are exactly
opposite to those of an encoder.
Block diagram
Examples of Decoders are following.

 Code converters
 BCD to seven segment decoders
2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A 1 & A0 and four outputs Y3, Y2, Y1 & Y0.
The block diagram of 2 to 4 decoder is shown in the following figure.

One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’.
The Truth table of 2 to 4 decoder is shown below.

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x X 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output as
 𝑌3 = 𝐸. 𝐴1. 𝐴0
𝑌2 = 𝐸. 𝐴1. 𝐴0′

𝑌1 = 𝐸. 𝐴1′. 𝐴0
𝑌0 = 𝐸. 𝐴1′. 𝐴0′
Each output is having one product term. So, there are four product terms in total. We can
implement these four product terms by using four AND gates having three inputs each & two
inverters. The circuit diagram of 2 to 4 decoder is shown in the following figure.

Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input variables
A1 & A0, when enable, E is equal to one. If enable, E is zero, then all the outputs of decoder
will be equal to zero.
Similarly, 3 to 8 decoder produces eight min terms of three input variables A 2, A1 & A0 and 4
to 16 decoder produces sixteen min terms of four input variables A3, A2, A1 & A0.
Encoder
Encoder is a combinational circuit which is designed to perform the inverse operation of the
decoder. An encoder has n number of input lines and m number of output lines. An encoder
produces an m bit binary code corresponding to the digital input number. The encoder
accepts an n input digital word and converts it into an m bit another digital word.

Block diagram

Examples of Encoders are following.

 Priority encoders
 Decimal to BCD encoder
 Octal to binary encoder
 Hexadecimal to binary encoder
4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0.
The block diagram of 4 to 2 Encoder is shown in the following figure.

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code
at the output. The Truth table of 4 to 2 encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From Truth table, we can write the Boolean functions for each output as
𝐴1 = 𝑌3 + 𝑌2
𝐴0 = 𝑌3 + 𝑌1
We can implement the above two Boolean functions by using two input OR gates.
The circuit diagram of 4 to 2 encoder is shown in the following figure.
The above circuit diagram contains two OR gates. These OR gates encode the four inputs
with two bits
Octal to Binary Encoder
Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to
binary encoder is nothing but 8 to 3 encoder.
The block diagram of octal to binary Encoder is shown in the following figure.

At any time, only one of these eight inputs can be ‘1’ in order to get the respective binary
code. The Truth table of octal to binary encoder is shown below.

Inputs Outputs

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0
 1 0 0 0 0 0 0 0 1 1 1

From Truth table, we can write the Boolean functions for each output as
𝐴2 = 𝑌7 + 𝑌6 + 𝑌5 + 𝑌4

𝐴1 = 𝑌7 + 𝑌6 + 𝑌3 + 𝑌2
𝐴0 = 𝑌7 + 𝑌5 + 𝑌3 + 𝑌1
We can implement the above Boolean functions by using four input OR gates.
The circuit diagram of octal to binary encoder is shown in the following figure.

The above circuit diagram contains three 4-input OR gates. These OR gates encode the eight
inputs with three bits.
Digital comparator
The Digital Comparator is another very useful combinational logic circuit used to compare the
value of two binary digits.

1-bit Digital Comparator Circuit

Then the operation of a 1-bit digital comparator is given in the following Truth Table.

Digital Comparator Truth Table

 7 1 1 1 0 0 0 0

8 1 1 1 1 1 1 1

9 1 1 1 1 0 1 1

Therefore, Boolean expression for each decimal digit which requires respective light emitting
diodes (LEDs) are ON or OFF.

UNIT-3
Sequential Logic Circuits
3.1 principles of flip-flops:
Sequential circuit contains a set of inputs and outputs. The outputs of sequential circuit
depend not only on the combination of present inputs but also on the previous outputs.
Previous output is nothing but the present state. Therefore, sequential circuits contain
combinational circuits along with memory storage elements. Some sequential circuits may
not contain combinational circuits, but only memory elements.

Following table shows the differences between combinational circuits and sequential
circuits.

Combinational Circuits Sequential Circuits

Outputs depend only on present Outputs depend on both present inputs and
inputs. present state.

Feedback path is not present. Feedback path is present.

 Memory elements are not required. Memory elements are required.

Clock signal is not required. Clock signal is required.

Easy to design. Difficult to design.

Types of Sequential Circuits

Following are the two types of sequential circuits −

 Asynchronous sequential circuits

 Synchronous sequential circuits

Asynchronous sequential circuits

If some or all the outputs of a sequential circuit do not change affect with respect to active
transition of clock signal, then that sequential circuit is called as Asynchronous sequential
circuit. That means, all the outputs of asynchronous sequential circuits do not
change affect at the same time. Therefore, most of the outputs of asynchronous sequential
circuits are not in synchronous with either only positive edges or only negative edges of
clock signal.

Synchronous sequential circuits

If all the outputs of a sequential circuit change affect with respect to active transition of clock
signal, then that sequential circuit is called as Synchronous sequential circuit. That means,
all the outputs of synchronous sequential circuits change affect at the same time. Therefore,
the outputs of synchronous sequential circuits are in synchronous with either only positive
edges or only negative edges of clock signal.
Clock Signal and Triggering
Clock signal
Clock signal is a periodic signal and its ON time and OFF time need not be the same. We
can represent the clock signal as a square wave, when both its ON time and OFF time are
same. This clock signal is shown in the following figure.

Types of Triggering
Following are the two possible types of triggering that are used in sequential circuits.

 Level triggering
 Edge triggering

Level triggering
There are two levels, namely logic High and logic Low in clock signal. Following are the
two types of level triggering.

 Positive level triggering

 Negative level triggering
If the sequential circuit is operated with the clock signal when it is in Logic High, then that
type of triggering is known as Positive level triggering. It is highlighted in below figure.

If the sequential circuit is operated with the clock signal when it is in Logic Low, then that
type of triggering is known as Negative level triggering. It is highlighted in the following
figure.

Edge triggering

There are two types of transitions that occur in clock signal. That means, the clock signal
transitions either from Logic Low to Logic High or Logic High to Logic Low.
Following are the two types of edge triggering based on the transitions of clock signal.

 Positive edge triggering

 Negative edge triggering
If the sequential circuit is operated with the clock signal that is transitioning from Logic Low
to Logic High, then that type of triggering is known as Positive edge triggering. It is also
called as rising edge triggering. It is shown in the following figure.

If the sequential circuit is operated with the clock signal that is transitioning from Logic High
to Logic Low, then that type of triggering is known as Negative edge triggering. It is also
called as falling edge triggering. It is shown in the following figure.

There are two types of memory elements based on the type of triggering that is suitable to
operate it.

 Latches
  Flip-flops
Latches operate with enable signal, which is level sensitive. Whereas, flip-flops are edge
sensitive.
There are 4 types of flip flops:

 SR Flip-Flop
 D Flip-Flop
 JK Flip-Flop
 T Flip-Flop

3.2 SR Flip-Flop
SR flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, SR latch operates with enable signal.
The circuit diagram of SR flip-flop is shown in the following figure.

This circuit has two inputs S & R and two outputs Q& Q’. The operation of SR flipflop is similar
to SR Latch. But, this flip-flop affects the outputs only when positive transition of the clock
signal is applied instead of active enable.
The following table shows the state table of SR flip-flop.

S R Qt+1

0 0 Q

0 1 0

1 0 1

1 1 -

Here, Q & Qt+1 are present state & next state respectively. So, SR flip-flop can be used for
one of these three functions such as Hold, Reset & Set based on the input conditions, when
positive transition of clock signal is applied.
D Flip-Flop
D flip-flop operates with only positive clock transitions or negative clock transitions. Whereas,
D latch operates with enable signal. That means, the output of D flip-flop is insensitive to the
changes in the input, D except for active transition of the clock signal.
The circuit diagram of D flip-flop is shown in the following figure.

This circuit has single input D and two outputs Q & Q’. The operation of D flip-flop is similar
to D Latch. But, this flip-flop affects the outputs only when positive transition of the clock
signal is applied instead of active enable.
The following table shows the state table of D flip-flop.

D Qt + 1

0 0

1 1

Therefore, D flip-flop always Hold the information, which is available on data input, D of earlier
positive transition of clock signal.
D flip-flops can be used in registers, shift registers and some of the counters.
JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock
transitions or negative clock transitions.
The circuit diagram of JK flip-flop is shown in the following figure.

This circuit has two inputs J & K and two outputs Q & Q’. The operation of JK flip-flop is similar
to SR flip-flop.
The following table shows the state table of JK flip-flop.
 J K Qt+1

0 0 Q

0 1 0

1 0 1

1 1 Q'

Here, Q & Qt+1 are present state & next state respectively. So, JK flip-flop can be used for
one of these four functions such as Hold, Reset, Set & Complement of present state based
on the input conditions, when positive transition of clock signal is applied.
Master-Slave JK Flip Flop

In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then Q output toggle
until the CLK is 1. Thus, the uncertain or unreliable output produces. This problem is referred
to as a race-round condition in JK flip-flop and avoided by ensuring that the CLK set to 1
only for a very short time.

Explanation

The master-slave flip flop is constructed by combining two J K flip flop. These flip flops are
connected in a series configuration. In these two flip flops, the 1st flip flop work as "master",
called the master flip flop, and the 2nd work as a "slave", called slave flip flop.

In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate is also used.
For passing the inverted clock pulse to the "slave" flip flop, the inverter is connected to the
clock's pulse. In simple words, when CP set to false for "master", then CP is set to true for
"slave", and when CP set to true for "master", then CP is set to false for "slave".

Working:
 o When the clock pulse is true, the slave flip flop will be in the isolated state, and the
system's state may be affected by the J and K inputs. The "slave" remains isolated
until the CP is 1. When the CP set to 0, the master flip-flop passes the information to
the slave flip flop to obtain the output.
o The master flip flop responds first from the slave because the master flip flop is the
positive level trigger, and the slave flip flop is the negative level trigger.
o The output Q'=1 of the master flip flop is passed to the slave flip flop as an input K
when the input J set to 0 and K set to 1. The clock forces the slave flip flop to work as
reset, and then the slave copies the master flip flop.
o When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The clock's
negative transition sets the slave and copies the master.
o The master flip flop toggles on the clock's positive transition when the inputs J and K
set to 1. At that time, the slave flip flop toggles on the clock's negative transition.
o The flip flop will be disabled, and Q remains unchanged when both the inputs of the
JK flip flop set to 0.

Timing Diagram of a Master Flip Flop:

o When the clock pulse set to 1, the output of the master flip flop will be one until the
clock input remains 0.
o When the clock pulse becomes high again, then the master's output is 0, which will be
set to 1 when the clock becomes one again.
o The master flip flop is operational when the clock pulse is 1. The slave's output remains
0 until the clock is not set to 0 because the slave flip flop is not operational.
o The slave flip flop is operational when the clock pulse is 0. The output of the master
remains one until the clock is not set to 0 again.
o Toggling occurs during the entire process because the output changes once in the
cycle.
T Flip-Flop
T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the same input
‘T’ to both inputs of JK flip-flop. It operates with only positive clock transitions or negative
clock transitions.
The circuit diagram of T flip-flop is shown in the following figure.

This circuit has single input T and two outputs Q & Q’. The operation of T flip-flop is same as
that of JK flip-flop. Here, we considered the inputs of JK flip-flop as J = T and K = T in order
to utilize the modified JK flip-flop for 2 combinations of inputs. So, we eliminated the other
two combinations of J & K, for which those two values are complement to each other in T flip-
flop.
The following table shows the state table of T flip-flop.

D Qt+1

0 Q

1 Q’

Here, Q & Qt+1 are present state & next state respectively. So, T flip-flop can be used for
one of these two functions such as Hold, & Complement of present state based on the input
conditions, when positive transition of clock signal is applied.
The output of T flip-flop always toggles for every positive transition of the clock signal, when
input T remains at logic High 11. Hence, T flip-flop can be used in counters.

UNIT-4
Registers, memories and PLD
4.1 Shift register
 Flip flops can be used to store a single bit of binary data (1or 0).
 However, in order to store multiple bits of data, we need multiple flip flops. N flip flops
are to be connected in an order to store n bits of data.
 A Register is a device which is used to store such information. It is a group of flip
flops connected in series used to store multiple bits of data.
 The information stored within these registers can be transferred with the help of shift
registers.
 Shift Register is a group of flip flops used to store multiple bits of data. The bits stored
in such registers can be made to move within the registers and in/out of the registers
by applying clock pulses.
 An n-bit shift register can be formed by connecting n flip-flops where each flip flop
stores a single bit of data.
Shift registers are basically of 4 types. These are:
1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register

Serial-In Serial-Out Shift Register (SISO) –

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as Serial-In Serial-Out shift register. Since there is
only one output, the data leaves the shift register one bit at a time in a serial pattern, thus
the name Serial-In Serial-Out Shift Register. The circuit consists of four D flip-flops which
are connected in a serial manner. All these flip-flops are synchronous with each other since
the same clock signal is applied to each flip flop. The main use of a SISO is to act as a delay
element.
Serial-In Parallel-Out shift Register (SIPO) –
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as Serial-In Parallel-Out shift register. The circuit
consists of four D flip-flops which are connected. The clear (CLR) signal is connected in
addition to the clock signal to all the 4 flip flops in order to RESET them. The output of the
first flip flop is connected to the input of the next flip flop and so on. All these flip -flops are
synchronous with each other since the same clock signal is applied to each flip flop. They
are used in communication lines where demultiplexing of a data line into several parallel
lines is required because the main use of the SIPO register is to convert serial data into
parallel data.
Parallel IN Serial OUT (PISO)
In the "Parallel IN Serial OUT" register, the data is entered in a parallel way, and the outcome
comes serially. A four-bit "Parallel IN Serial OUT" register is designed below. The input of
the flip flop is the output of the previous Flip Flop. The input and outputs are connected through
the combinational circuit. Through this combinational circuit, the binary input B 0, B1, B2, B3 are
passed. The shift mode and the load mode are the two modes in which the "PISO" circuit
works.
Load mode
The bits B0, B1, B2, and B3 are passed to the corresponding flip flops when the second, fourth,
and sixth "AND" gates are active. These gates are active when the shift or load bar line set to
0. The binary inputs B0, B1, B2, and B3 will be loaded into the respective flip-flops when the
edge of the clock is low. Thus, parallel loading occurs.
Shift mode
The second, fourth, and sixth gates are inactive when the load and shift line set to 0. So, we
are not able to load data in a parallel way. At this time, the first, third, and fifth gates will be
activated, and the shifting of the data will be left to the right bit. In this way, the "Parallel IN
Serial OUT" operation occurs.
A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data.

Parallel IN Parallel OUT (PIPO)

In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel way in the register.
The inputs A0, A1, A2, and A3, are directly passed to the data inputs D 0, D1, D2, and D3 of the
respective flip flop. The bits of the binary input is loaded to the flip flops when the negative
clock edge is applied. The clock pulse is required for loading all the bits. At the output side,
the loaded bits appear.

4.2 Universal shift register

A Universal shift register is a register which has both the right shift and left shift with parallel
load capabilities. Universal shift registers are used as memory elements in computers. A
Unidirectional shift register is capable of shifting in only one direction. A bidirectional shift
register is capable of shifting in both the directions. The Universal shift register is a
combination design of bidirectional shift register and a unidirectional shift register with
parallel load provision
Basic connections –
1. The first input (zeroth pin of multiplexer) is connected to the output pin of the
corresponding flip-flop.
2. The second input (first pin of multiplexer) is connected to the output of the very-
previous flip flop which facilitates the right shift.
3. The third input (second pin of multiplexer) is connected to the output of the
very-next flip-flop which facilitates the left shift.
4. The fourth input (third pin of multiplexer) is connected to the individual bits of
the input data which facilitates parallel loading.
The working of the Universal shift register depends on the inputs given to the select lines.
The register operations performed for the various inputs of select lines are as follows:
S1 S0 Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load

4.3 Counters
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock
signal applied. Counters are of two types.

 Asynchronous or ripple counters.

 Synchronous counters.
Asynchronous or ripple counters
The Asynchronous counter is also known as the ripple counter. Below is a diagram of the
2-bit Asynchronous counter in which we used two T flip-flops or two JK flip flop by setting
both of the inputs to 1 permanently. The external clock pass to the clock input of the first flip
flop, i.e., FF-A and its output, i.e., is passed to clock input of the next flip flop, i.e., FF-B.
Operation:

1. Condition 1: When both the flip flops are in reset condition.

Operation: The outputs of both flip flops, i.e., QA QB, will be 0.
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will toggle, and the output of this flip flop will change
from 0 to 1. The output of this flip flop will be taken by the clock input of the next flip
flop. This output will be taken as a positive edge clock by the second flip flop. This
input will not change the second flip flop's output state because it is the negative
edge triggered flip flop.
So, QA = 1 and QB = 0
3. Condition 3: When the second negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 1 to 0. This output will be taken as a negative edge clock by the second
flip flop. This input will change the second flip flop's output state because it is the
negative edge triggered flip flop.
So, QA = 0 and QB = 1.
4. Condition 4: When the third negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 0 to 1. This output will be taken as a positive edge clock by the second
flip flop. This input will not change the second flip flop's output state because it is the
negative edge triggered flip flop.
So, QA = 1 and QB = 1
5. Condition 5: When the fourth negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 1 to 0. This output will be taken as a negative edge clock by the second
flip flop. This input will change the output state of the second flip flop.
So, QA = 0 and QB = 0

4.4 Classification of counters

Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows −

 Up counters
 Down counters
 Up/Down counters
UP/DOWN Counter
Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode
control (M) input is also provided to select either up or down mode. A combinational circuit is
required to be designed and used between each pair of flip-flop in order to achieve the
up/down operation.

 Type of up/down counters

 UP/DOWN ripple counters
 UP/DOWN synchronous counter
UP/DOWN Counter
Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode
control (M) input is also provided to select either up or down mode. A combinational circuit is
required to be designed and used between each pair of flip-flop in order to achieve the
up/down operation.

 Type of up/down counters

 UP/DOWN ripple counters
 UP/DOWN synchronous counter
UP/DOWN Ripple Counters
In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So, either T flip-flops
or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every
other FF is obtained from (Q = Q bar) output of the previous FF.
 UP counting mode (M=0) − The Q output of the preceding FF is connected to the
clock of the next stage if up counting is to be achieved. For this mode, the mode select
input M is at logic 0 (M=0).
 DOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF
is connected to the next FF. This will operate the counter in the counting mode.
Example
3-bit binary up/down ripple counter.
 3-bit − hence three FFs are required.
 UP/DOWN − So a mode control input is essential.
 For a ripple up counter, the Q output of preceding FF is connected to the clock input
of the next one.
 For a ripple up counter, the Q output of preceding FF is connected to the clock input
of the next one.
 For a ripple down counter, the Q bar output of preceding FF is connected to the clock
input of the next one.
 Let the selection of Q and Q bar output of the preceding FF be controlled by the mode
control input M such that, If M = 0, UP counting. So, connect Q to CLK. If M = 1,
DOWN counting. So, connect Q bar to CLK.
Modulus Counter (MOD-N Counter)
The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-
8 counter. So, in general, an n-bit ripple counter is called as modulo-N counter. Where, MOD
number = 2n.
Type of modulus
 2-bit up or down (MOD-4)
 3-bit up or down (MOD-8)
 4-bit up or down (MOD-16)
Application of counters
 Frequency counters
 Digital clock
 Time measurement
 A to D converter
 Frequency divider circuits
 Digital triangular wave generator.
Decade counter
A decade counter counts ten different states and then reset to its initial states. A simple
decade counter will count from 0 to 9 but we can also make the decade counters which can
go through any ten states between 0 to 15 (for 4 bit counter).

Clock
pulse Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1
 4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

We see from circuit diagram that we have used NAND gate for Q3 and Q1 and feeding this
to clear input line because binary representation of 10 is—1010
And we see Q3 and Q1 are 1 here, if we give NAND of these two bits to clear input then
counter will be clear at 10 and again start from beginning.
Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a
counter is called as synchronous counter.
2-bit Synchronous up counter
The JA and KA inputs of FF-A are tied to logic 1. So, FF-A will work as a toggle flip-flop. The
JB and KB inputs are connected to QA.

Operation
 S.N. Condition Operation

1 Initially let both the FFs be in the reset state QBQA = 00 initially.

2 After 1st negative clock edge

As soon as the first negative clock edge is
applied, FF-A will toggle and QA will
change from 0 to 1.
But at the instant of application of negative
clock edge, QA , JB = KB = 0. Hence FF-B
will not change its state. So QB will remain
0.
QBQA = 01 after the first clock pulse.

3 After 2nd negative clock edge

On the arrival of second negative clock
edge, FF-A toggles again and QA changes
from 1 to 0.
But at this instant QA was 1. So JB = KB= 1
and FF-B will toggle. Hence QB changes
from 0 to 1.
QBQA = 10 after the second clock pulse.

4 After 3rd negative clock edge

On application of the third falling clock
edge, FF-A will toggle from 0 to 1 but there
is no change of state for FF-B.
QBQA = 11 after the third clock pulse.

5 After 4th negative clock edge

On application of the next clock pulse,
QA will change from 1 to 0 as QB will also
change from 1 to 0.
QBQA = 00 after the fourth clock pulse.

4-bit synchronous counter

 The external clock pulses (pulses to be counted) are fed directly to each of the J-K flip-
flops in the counter chain and that both the J and K inputs are all tied together in toggle
mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic
“1” allowing the flip-flop to toggle on every clock pulse.
 Then the synchronous counter follows a predetermined sequence of states in
response to the common clock signal, advancing one state for each pulse.
 The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-
flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from
separate AND gates which are also supplied with signals from the input and output of
the previous stage.
  These additional AND gates generate the required logic for the JK inputs of the next
stage.
 If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop
outputs (Q) are “HIGH” we can obtain the same counting sequence as with the
asynchronous circuit but without the ripple effect, since each flip-flop in this circuit will
be clocked at exactly the same time.
 Then as there is no inherent propagation delay in synchronous counters, because all
the counter stages are triggered in parallel at the same time, the maximum operating
frequency of this type of frequency counter is much higher than that for a similar
asynchronous counter circuit.

Ring counter

 Ring counter is a typical application of Shift resister.

 Ring counter is almost same as the shift counter. The only change is that the output
of the last flip-flop is connected to the input of the first flip-flop in case of ring counter
but in case of shift resister it is taken as output.
 No. of states in Ring counter = No. of flip-flop used
4-bit ring counter

 The clock pulse (CLK) is applied to all the flip-flop simultaneously. Therefore, it is a
Synchronous Counter.
 Also, here we use Overriding input (ORI) to each flip-flop. Preset (PR) and Clear
(CLR) are used as ORI.
 When PR is 0, then the output is 1. And when CLR is 0, then the output is 0. Both
PR and CLR are active low signal that is always works in value 0.
PR = 0, Q = 1
CLR = 0, Q = 0
 These two values are always fixed. They are independent with the value of input D
and the Clock pulse (CLK).
Working–
 Here, ORI is connected to Preset (PR) in FF-0 and it is connected to Clear (CLR) in
FF-1, FF-2, and FF-3.
 Thus, output Q = 1 is generated at FF-0 and rest of the flip-flop generate output Q =
0.
 This output Q = 1 at FF-0 is known as Pre-set 1 which is used to form the ring in the
Ring Counter.

 This Preseted 1 is generated by making ORI low and that time Clock (CLK) becomes
don’t care.
  After that ORI made to high and apply low clock pulse signal as the Clock (CLK) is
negative edge triggered.
 After that, at each clock pulse the preseted 1 is shifted to the next flip -flop and thus
form Ring.
From the above table, we can say that there are 4 states in 4-bit Ring Counter.
4 states are:
1000
0100
0010
0001
4.5 Concept of memories
A memory is just like a human brain. It is used to store data and instruction. Computer
memory is the storage space in computer where data is to be processed and instructions
required for processing are stored.
The memory is divided into large number of small parts. Each part is called a cell. Each
location or cell has a unique address which varies from zero to memory size minus one.
For example if computer has 64k words, then this memory unit has 64 * 1024 = 65536
memory location. The address of these locations varies from 0 to 65535.
Memory is primarily of two types
 Internal Memory − cache memory and primary/main memory
 External Memory − magnetic disk / optical disk etc.
RAM
A RAM constitutes the internal memory of the CPU for storing data, program and program
result. It is read/write memory. It is called random access memory (RAM).
Since access time in RAM is independent of the address to the word that is, each storage
location inside the memory is as easy to reach as other location & takes the same amount of
time. We can reach into the memory at random & extremely fast but can also be quite
expensive.
RAM is volatile, i.e. data stored in it is lost when we switch off the computer or if there is a
power failure. Hence, a backup uninterruptible power system (UPS) is often used with
computers. RAM is small, both in terms of its physical size and in the amount of data it can
hold.
RAM is of two types

 Static RAM (SRAM)

 Dynamic RAM (DRAM)

Static RAM (SRAM)

The word static indicates that the memory retains its contents as long as power remains
applied. However, data is lost when the power gets down due to volatile nature. SRAM chips
use a matrix of 6-transistors and no capacitors. Transistors do not require power to prevent
leakage, so SRAM need not have to be refreshed on a regular basis.
Because of the extra space in the matrix, SRAM uses more chips than DRAM for the same
amount of storage space, thus making the manufacturing costs higher.
Static RAM is used as cache memory needs to be very fast and small.

Dynamic RAM (DRAM)

DRAM, unlike SRAM, must be continually refreshed in order for it to maintain the data. This
is done by placing the memory on a refresh circuit that rewrites the data several hundred
times per second. DRAM is used for most system memory because it is cheap and small. All
DRAMs are made up of memory cells. These cells are composed of one capacitor and one
transistor.
ROM
ROM stands for Read Only Memory. The memory from which we can only read but cannot
write on it. This type of memory is non-volatile. The information is stored permanently in such
memories during manufacture.
A ROM, stores such instruction as are required to start computer when electricity is first
turned on, this operation is referred to as bootstrap. ROM chip are not only used in the
computer but also in other electronic items like washing machine and microwave oven.
Following are the various types of ROM −

MROM (Masked ROM)

The very first ROMs were hard-wired devices that contained a pre-programmed set of data
or instructions. These kind of ROMs are known as masked ROMs. It is inexpensive ROM.

PROM (Programmable Read Only Memory)

PROM is read-only memory that can be modified only once by a user. The user buys a blank
PROM and enters the desired contents using a PROM programmer. Inside the PROM chip
there are small fuses which are burnt open during programming. It can be programmed only
once and is not erasable.

EPROM (Erasable and Programmable Read Only Memory)

The EPROM can be erased by exposing it to ultra-violet light for a duration of upto 40 minutes.
Usually, an EPROM eraser achieves this function. During programming an electrical charge
is trapped in an insulated gate region. The charge is retained for more than ten years because
the charge has no leakage path. For erasing this charge, ultra-violet light is passed through
a quartz crystal window (lid). This exposure to ultra-violet light dissipates the charge. During
normal use the quartz lid is sealed with a sticker.

EEPROM (Electrically Erasable and Programmable Read Only Memory)

The EEPROM is programmed and erased electrically. It can be erased and reprogrammed
about ten thousand times. Both erasing and programming take about 4 to 10 ms
(millisecond). In EEPROM, any location can be selectively erased and programmed.
EEPROMs can be erased one byte at a time, rather than erasing the entire chip. Hence, the
process of re-programming is flexible but slow.
4.6 Programmable Logic Devices (PLD)
The given two functions are in sum of products form. The number of product terms present
in the given Boolean functions A & B are two and three respectively. One product term, Z′X is
common in each function.
So, we require four programmable AND gates & two programmable OR gates for producing
those two functions. The corresponding PLA is shown in the following figure.

The programmable AND gates have the access of both normal and complemented inputs
of variables. In the above figure, the inputs X, X′, Y, Y′, Z & Z′, are available at the inputs of
each AND gate. So, program only the required literals in order to generate one product term
by each AND gate.
All these product terms are available at the inputs of each programmable OR gate. But, only
program the required product terms in order to produce the respective Boolean functions by
each OR gate. The symbol ‘X’ is used for programmable connections.

UNIT-5
A/D and D/A converter
5.1 ADC & DAC
Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) are very important
components in electronic equipment. Since most real-world signals are analog, these two
converting interfaces are necessary to allow digital electronic equipment to process the analog
signals.
Digital to analog converter (DAC)
A Digital to Analog Converter (DAC) converts a digital input signal into an analog output
signal. The digital signal is represented with a binary code, which is a combination of bits 0
and 1. This chapter deals with Digital to Analog Converters in detail.
The block diagram of DAC is shown in the following figure −
A Digital to Analog Converter (DAC) consists of a number of binary inputs and a single output.
In general, the number of binary inputs of a DAC will be a power of two.

Types of DACs

There are two types of DACs

 Weighted Resistor DAC

 R-2R Ladder DAC

5.2 Weighted resistor DAC

A weighted resistor DAC produces an analog output, which is almost equal to the digital
(binary) input by using binary weighted resistors in the inverting adder circuit. In short, a
binary weighted resistor DAC is called as weighted resistor DAC.

The resistor with the lowest value R corresponds to the highest weighted binary input Bit 3
(MSB) [23 = 8], and 2R, 4R, 8R correspond to the binary weights of Bit 2 (2 2 = 4), Bit 1 (21 =
2), and Bit 0 (LSB) [2 0 = 1] respectively. The relationship between the digital inputs (Bit 0 to
Bit 3) and the analog output VOUT is as follow:

5.3 R-2R ladder DAC

R-2R Digital-to-Analogue Converter, or DAC, is a data converter which use two precision
resistors to convert a digital binary number into an analogue output signal proportional to the
value of the digital number. A R-2R resistive ladder network provides a simple means of
converting digital voltage signals into an equivalent analogue output. Input voltages are
applied to the ladder network at various points along its length and the more input points the
better the resolution of the R-2R ladder. The output signal as a result of all these input voltage
points is taken from the end of the ladder which is used to drive the inverting input of an
operational amplifier.

Lets assume all the binary inputs are grounded at 0 volts, that is: V A = VB = VC = VD = 0V
(LOW). The binary code corresponding to these four inputs will therefore be: 0000.

Resistors R1 and R2 are in “parallel” with each other but in “series” with resistor R 3. Then we
can find the equivalent resistance of these three resistors and call it R A for simplicity

Then RA is equivalent to “2R”. Now we can see that the equivalent resistance “R A” is in
parallel with R4 with the parallel combination in series with R 5.

Again, we can find the equivalent resistance of this combination and call it R B.
So, RB combination is equivalent to “2R”. Hopefully we can see that this equivalent
resistance RB is in parallel with R6 with the parallel combination in series with R7 as shown.

As before we find the equivalent resistance and call it R C.

Again, resistor combination RC is equivalent to “2R” which is in parallel with R8 as shown.

As we have shown above, when two equal resistor values are parallel together, the resulting
value is one-half, so 2R in parallel with 2R equals an equivalent resistance of R. So, the
whole 4-bit R-2R resistive ladder network comprising of individual resistors connected
together in parallel and series combinations has an equivalent resistance (R EQ) of “R” when
a binary code of “0000” is applied to its four inputs.
Therefore, with a binary code of “0000” applied as inputs, our basic 4-bit R-2R digital-to-
analogue converter circuit would look something like this:
5.4 Counter type ADC
The circuit functions as follows.
Firstly, to begin with, the counter is reset to all 0s.
Secondly, when a convert signal appears on the start line, the input gate is enabled and
the clock pulses are applied to the clock input of the counter. The counter advances
through its normal binary count sequence.
Thirdly, the counter output feeds a D/A converter and the staircase waveform generated at
the output of the D/A converter forms one of the inputs of the comparator. The other input to
the comparator is the analogue input signal.
Fourthly, Whenever the D/A converter output exceeds the analogue input voltage, the
comparator changes state.
Finally, the gate is disabled and the counter stops. The counter output at that instant of
time is then the required digital output corresponding to the analogue input signal.

5.5 Successive Approximation ADC

 Successive Approximation type ADC is the most widely used and popular ADC
method.
 The conversion time is maintained constant in successive approximation type ADC,
and is proportional to the number of bits in the digital output, unlike the counter and
continuous type A/D converters.
 The basic principle of this type of A/D converter is that the unknown analog input
voltage is approximated against an n-bit digital value by trying one bit at a time,
beginning with the MSB.
 The principle of successive approximation process for a 4-bit conversion is explained
here.
 This type of ADC operates by successively dividing the voltage range by half, as
explained in the following steps.
(1) The MSB is initially set to 1 with the remaining three bits set as 000. The digital
equivalent voltage is compared with the unknown analog input voltage.
(2) If the analog input voltage is higher than the digital equivalent voltage, the MSB is
retained as 1 and the second MSB is set to 1. Otherwise, the MSB is set to 0 and the
second MSB is set to 1. Comparison is made as given in step (1) to decide whether
to retain or reset the second MSB.
 The above steps are more accurately illustrated with the help of an example.
 Let us assume that the 4-bit ADC is used and the analog input voltage is Vin = 11 V.
when the conversion starts, the MSB bit is set to 1.
Now Vin = 11V > Vref = 8V = [1000]2
Since the unknown analog input voltage VA is higher than the equivalent digital
voltage VD, as discussed in step (2), the MSB is retained as 1 and the next MSB bit
is set to 1 as follows
VD = 12V = [1100]2
Now VA = 11V < VD = 12V = [1100]2
Here now, the unknown analog input voltage VA is lower than the equivalent digital voltage
VD. As discussed in step (2), the second MSB is set to 0 and next MSB set to 1 as
VD = 10V = [1010]2

Now again VA = 11V > VD = 10V = [1010]2

Again as discussed in step (2) VA>VD, hence the third MSB is retained to 1 and the last bit
is set to 1. The new code word is
VD = 11V = [1011]2
Now finally VA = VD , and the conversion stops.
The functional block diagram of successive approximation type of ADC is shown below.

It consists of a successive approximation register (SAR), DAC and comparator. The output of
SAR is given to n-bit DAC. The equivalent analog output voltage of DAC, VD is applied to the
non-inverting input of the comparator. The second input to the comparator is the unknown
analog input voltage VA. The output of the comparator is used to activate the successive
approximation logic of SAR.
When the start command is applied, the SAR sets the MSB to logic 1 and other bits are made
logic 0, so that the trial code becomes 1000.

Advantages:
1 Conversion time is very small.
2 Conversion time is constant and independent of the amplitude of the analog input signal
VA.

Disadvantages:
1 Circuit is complex.
2 The conversion time is more compared to flash type ADC.

UNIT-6
Logic families
6.1 Logic Families
In Digital Designs, our primary aim is to create an Integrated Circuit (IC). A Circuit
configuration or arrangement of the circuit elements in a special manner will result in a
particular Logic Family.
Different types of logic families
1. Resistor Transistor Logic (RTL)