RISC Assignment
1. Co-Processor Instructions
Co-processors are auxiliary processors designed to perform specialized, computation-heavy tasks.
They operate alongside the main CPU, enhancing efficiency by handling operations like
floating-point arithmetic, memory management, or signal processing.
Key Points:
• Purpose: Offload specialized tasks such as Floating-Point Arithmetic (FPU), Memory
Management (MMU), or Digital Signal Processing (DSP).
• RISC Example (e.g., ARM): ARM architecture supports up to 16 co-processors (P0 to P15).
• Instruction Categories:
• • Data Transfer – Moves data between ARM registers and co-processor registers (MCR, MRC).
• • Data Operation – Performs internal co-processor operations (CDP).
• • Load/Store – Moves data between memory and co-processor registers (LDC, STC).
Example Instruction:
MRC p15, 0, R0, c1, c0, 0 — Reads data from co-processor p15 register c1 into CPU register R0.
Here, 'MRC' stands for Move from Co-processor Register, 'p15' identifies the co-processor, and 'R0'
is a general-purpose CPU register.
Functions of Co-Processors:
• Managing cache and memory subsystems.
• Performing floating-point calculations.
• Monitoring and controlling system status.
2. Loading Constants
RISC architectures use fixed-length instructions (usually 32 bits). Due to this, immediate constants
embedded in instructions are limited in size, so larger constants require multiple instructions to
load.
Key Points to Understand:
• Immediate Field Limitation: Only a small portion (typically 8–16 bits) of an instruction can store
immediate constants.
• Small Constants: Can be directly loaded using arithmetic or logic instructions (e.g., ADDI R1,
R0, #100).
• Large Constants: Require two-step loading using Load Upper Immediate (LUI) and another
instruction like ORI or ADDI to set the lower bits.
• Assemblers often simplify this process with pseudo-instructions such as MOV or LI (Load
Immediate).
Example:
LUI R1, 0x12340000 — Loads upper 16 bits of R1 with 0x1234.
ORI R1, R1, 0x5678 — Combines lower 16 bits with 0x5678, resulting in R1 = 0x12345678.
3. Program Status Register (PSR) Instructions
The Program Status Register (PSR) holds flags and control bits that represent the CPU's current
operating state. It stores results of ALU operations and manages processor control settings such as
mode and interrupt enable states.
Important Details:
• PSR Variants: In ARM, known as CPSR (Current Program Status Register) or APSR
(Application Program Status Register).
• Flag Bits:
• • N – Negative flag (result < 0).
• • Z – Zero flag (result = 0).
• • C – Carry flag (unsigned overflow).
• • V – Overflow flag (signed overflow).
• Control Bits: Manage processor mode (User/System/Supervisor) and interrupt enables (I and F
bits).
• PSR Instructions:
• • MSR – Move data from a register to PSR (write).
• • MRS – Move data from PSR to a register (read).
• Conditional Execution: PSR flags determine conditional branching in RISC architectures like
ARM.